From ce4d35aa85652ceca29acece158a07d5ec24fff5 Mon Sep 17 00:00:00 2001 From: Veripool API Bot <57024651+veripoolbot@users.noreply.github.com> Date: Tue, 3 Mar 2026 07:21:24 -0500 Subject: [PATCH] Verilog format --- test_regress/t/t_a1_first_cc.v | 19 +- test_regress/t/t_alias_unsup.v | 14 +- test_regress/t/t_array_backw_index_bad.out | 42 +- test_regress/t/t_array_backw_index_bad.v | 36 +- test_regress/t/t_array_compare.v | 70 +- test_regress/t/t_array_in_struct.v | 76 +- test_regress/t/t_array_index_increment.v | 216 +++--- test_regress/t/t_array_index_side.v | 60 +- test_regress/t/t_array_list_bad.out | 12 +- test_regress/t/t_array_list_bad.v | 53 +- test_regress/t/t_array_mda.v | 114 +-- test_regress/t/t_array_method_bad.out | 6 +- test_regress/t/t_array_method_bad.v | 12 +- test_regress/t/t_array_method_map.out | 12 +- test_regress/t/t_array_method_map.v | 20 +- test_regress/t/t_array_non_blocking_loop.v | 47 +- test_regress/t/t_array_packed_endian.v | 134 ++-- test_regress/t/t_array_packed_sign.v | 82 +- test_regress/t/t_array_packed_sysfunct.v | 285 ++++--- test_regress/t/t_array_packed_write_read.v | 256 +++--- test_regress/t/t_array_pattern_2d.v | 58 +- test_regress/t/t_array_pattern_bad.out | 6 +- test_regress/t/t_array_pattern_bad.v | 23 +- test_regress/t/t_array_pattern_bad2.out | 6 +- test_regress/t/t_array_pattern_bad2.v | 23 +- test_regress/t/t_array_pattern_bad3.out | 20 +- test_regress/t/t_array_pattern_bad3.v | 28 +- test_regress/t/t_array_pattern_enum.v | 32 +- test_regress/t/t_array_pattern_packed.v | 246 +++--- test_regress/t/t_array_pattern_unpacked.v | 84 +- test_regress/t/t_array_query.v | 74 +- test_regress/t/t_array_query_with.v | 110 +-- test_regress/t/t_array_rev.v | 76 +- test_regress/t/t_array_sel_wide.v | 34 +- test_regress/t/t_array_type_methods.v | 34 +- test_regress/t/t_array_unpacked_public.v | 10 +- test_regress/t/t_assert_always_unsup.out | 24 +- test_regress/t/t_assert_always_unsup.v | 61 +- test_regress/t/t_assert_basic.v | 88 ++- test_regress/t/t_assert_casez.v | 40 +- test_regress/t/t_assert_clock_event_unsup.out | 6 +- test_regress/t/t_assert_clock_event_unsup.v | 47 +- test_regress/t/t_assert_comp.v | 42 +- test_regress/t/t_assert_cover.v | 230 +++--- test_regress/t/t_assert_ctl_arg.dat.out | 304 ++++---- test_regress/t/t_assert_ctl_arg.out | 726 +++++++++--------- test_regress/t/t_assert_ctl_arg.v | 293 ++++--- test_regress/t/t_assert_ctl_arg_unsup.out | 24 +- test_regress/t/t_assert_ctl_arg_unsup.v | 22 +- test_regress/t/t_assert_ctl_concurrent.v | 44 +- test_regress/t/t_assert_ctl_immediate.out | 10 +- test_regress/t/t_assert_ctl_immediate.v | 90 +-- test_regress/t/t_assert_ctl_unsup.out | 200 ++--- test_regress/t/t_assert_ctl_unsup.v | 274 +++---- test_regress/t/t_assert_disable_bad.out | 6 +- test_regress/t/t_assert_disable_bad.v | 32 +- test_regress/t/t_assert_disable_count.v | 93 +-- test_regress/t/t_assert_dup_bad.out | 12 +- test_regress/t/t_assert_dup_bad.v | 18 +- test_regress/t/t_assert_elab.v | 31 +- test_regress/t/t_assert_iff.v | 72 +- test_regress/t/t_assert_iff_clk_unsup.out | 6 +- test_regress/t/t_assert_iff_clk_unsup.v | 22 +- test_regress/t/t_assert_imm_nz_bad.out | 6 +- test_regress/t/t_assert_imm_nz_bad.v | 11 +- test_regress/t/t_assert_implication.v | 145 ++-- test_regress/t/t_assert_inside_cond.v | 44 +- test_regress/t/t_assert_on.v | 19 +- test_regress/t/t_assert_past.v | 41 +- .../t/t_assert_procedural_clk_bad.out | 16 +- test_regress/t/t_assert_procedural_clk_bad.v | 38 +- test_regress/t/t_assert_question.v | 34 +- test_regress/t/t_assert_sampled.v | 134 ++-- test_regress/t/t_assert_synth.v | 155 ++-- test_regress/t/t_assert_synth_full.out | 10 +- test_regress/t/t_assert_synth_full_vlt.out | 10 +- test_regress/t/t_assert_synth_parallel.out | 10 +- test_regress/t/t_assert_synth_parallel.vlt | 2 +- .../t/t_assert_synth_parallel_vlt.out | 10 +- test_regress/t/t_assert_unique_case_bad.v | 96 +-- test_regress/t/t_assign_expr.v | 120 +-- test_regress/t/t_assign_inline.v | 74 +- test_regress/t/t_assign_slice_overflow.v | 265 +++---- .../t/t_assigndly_dynamic_notiming_bad.out | 8 +- .../t/t_assigndly_dynamic_notiming_bad.v | 24 +- test_regress/t/t_assigndly_task.v | 8 +- test_regress/t/t_assoc.v | 289 ++++--- test_regress/t/t_assoc2.v | 62 +- test_regress/t/t_assoc_compare.v | 104 +-- test_regress/t/t_assoc_enum.v | 40 +- test_regress/t/t_assoc_method.v | 7 +- test_regress/t/t_assoc_method_bad.out | 96 +-- test_regress/t/t_assoc_method_bad.v | 38 +- test_regress/t/t_assoc_method_map.out | 6 +- test_regress/t/t_assoc_method_map.v | 22 +- test_regress/t/t_assoc_ref_type.v | 108 +-- test_regress/t/t_assoc_wildcard.v | 84 +- test_regress/t/t_assoc_wildcard_bad.out | 114 +-- test_regress/t/t_assoc_wildcard_bad.v | 54 +- test_regress/t/t_assoc_wildcard_map.out | 6 +- test_regress/t/t_assoc_wildcard_map.v | 20 +- test_regress/t/t_assoc_wildcard_method.v | 244 +++--- test_regress/t/t_attr_parenstar.v | 57 +- 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| 24 +- test_regress/t/t_castdyn_enum.v | 108 +-- test_regress/t/t_castdyn_unsup_bad.out | 6 +- test_regress/t/t_castdyn_unsup_bad.v | 10 +- test_regress/t/t_checker.v | 58 +- test_regress/t/t_checker_unsup.out | 34 +- test_regress/t/t_checker_unsup.v | 108 ++- test_regress/t/t_class1.v | 48 +- test_regress/t/t_class2.v | 62 +- test_regress/t/t_class_builtin_bad.out | 12 +- test_regress/t/t_class_builtin_bad.v | 18 +- test_regress/t/t_class_eq.v | 2 +- test_regress/t/t_class_extends_arg.v | 2 +- test_regress/t/t_class_new_typed.v | 2 +- test_regress/t/t_class_wide.v | 2 +- test_regress/t/t_clocked_release_combo.v | 20 +- test_regress/t/t_clocker.v | 72 +- test_regress/t/t_clocking_empty_block.v | 2 +- test_regress/t/t_comb_do_not_convert_to.v | 60 +- test_regress/t/t_comb_input_0.v | 8 +- test_regress/t/t_comb_input_1.v | 8 +- test_regress/t/t_comb_input_2.v | 8 +- .../t/t_comb_loop_through_unpacked_array.v | 12 +- test_regress/t/t_compiler_include.v | 7 +- test_regress/t/t_compiler_include_dpi.v | 41 +- test_regress/t/t_concat_casts.v | 46 +- test_regress/t/t_concat_impure.v | 22 +- test_regress/t/t_concat_link_bad.out | 42 +- test_regress/t/t_concat_link_bad.v | 6 +- test_regress/t/t_concat_opt.v | 100 ++- test_regress/t/t_concat_or.v | 128 +-- test_regress/t/t_concat_sel.v | 116 +-- test_regress/t/t_concat_string.v | 36 +- test_regress/t/t_concat_unpack.v | 50 +- test_regress/t/t_const.v | 24 +- test_regress/t/t_const_bad.out | 18 +- test_regress/t/t_const_bad.v | 20 +- test_regress/t/t_const_bitoptree_bug3096.v | 26 +- test_regress/t/t_const_dec_mixed_bad.out | 6 +- test_regress/t/t_const_dec_mixed_bad.v | 2 +- test_regress/t/t_const_hi.v | 81 +- test_regress/t/t_const_number_bad.out | 48 +- test_regress/t/t_const_number_bad.v | 14 +- test_regress/t/t_const_number_unsized.v | 75 +- test_regress/t/t_const_number_v_bad.out | 36 +- test_regress/t/t_const_number_v_bad.v | 16 +- test_regress/t/t_const_op_red_scope.v | 192 ++--- test_regress/t/t_const_overflow_bad.out | 30 +- test_regress/t/t_const_overflow_bad.v | 16 +- test_regress/t/t_const_sel_sel_extend.v | 20 +- test_regress/t/t_const_slicesel.v | 16 +- test_regress/t/t_const_string_func.v | 25 +- test_regress/t/t_constraint_cls_arr_member.v | 10 +- test_regress/t/t_cover_toggle_min.v | 2 +- test_regress/t/t_cover_trace_always.v | 2 +- .../t/t_covergroup_func_override_bad.v | 2 +- .../t/t_covergroup_new_override_bad.v | 2 +- test_regress/t/t_cuse_forward.v | 12 +- test_regress/t/t_dpi_binary.v | 2 +- test_regress/t/t_dpi_context.v | 2 +- test_regress/t/t_dpi_display.v | 2 +- test_regress/t/t_dpi_display_bad.v | 2 +- test_regress/t/t_dpi_dup_bad.v | 2 +- test_regress/t/t_dpi_import_mix_bad.v | 2 +- test_regress/t/t_dpi_name_bad.v | 2 +- test_regress/t/t_dpi_string.v | 2 +- test_regress/t/t_dpi_sys.v | 2 +- test_regress/t/t_enum_bad_value.v | 2 +- test_regress/t/t_enum_const_methods.v | 2 +- test_regress/t/t_enum_name2.v | 2 +- test_regress/t/t_event_control_assign.v | 2 +- test_regress/t/t_event_control_pass.v | 2 +- test_regress/t/t_event_control_star.v | 2 +- test_regress/t/t_final.v | 2 +- test_regress/t/t_flag_fi.v | 2 +- test_regress/t/t_flag_ldflags.v | 2 +- .../t/t_fork_block_item_declaration.v | 2 +- test_regress/t/t_fork_initial.v | 2 +- test_regress/t/t_fork_join_none_any_nested.v | 2 +- test_regress/t/t_fork_join_none_class_cap.v | 2 +- test_regress/t/t_fork_join_none_virtual.v | 2 +- test_regress/t/t_fork_output_arg.v | 2 +- test_regress/t/t_func_automatic_clear.v | 2 +- test_regress/t/t_func_complex.v | 2 +- test_regress/t/t_func_real_param.v | 2 +- test_regress/t/t_func_refio_bad.v | 2 +- test_regress/t/t_func_v.v | 2 +- test_regress/t/t_fuzz_triand_bad.v | 2 +- test_regress/t/t_gate_opt.v | 2 +- test_regress/t/t_iface_self_ref_typedef.v | 8 +- .../t/t_iface_typedef_struct_member.v | 24 +- test_regress/t/t_iface_typedef_wrong_clone.v | 28 +- test_regress/t/t_initial_delay_assign.v | 2 +- test_regress/t/t_inside_nonint.v | 2 +- test_regress/t/t_interface_ar2a.v | 2 +- test_regress/t/t_interface_ar2b.v | 2 +- test_regress/t/t_interface_array_nocolon.v | 2 +- .../t/t_interface_array_nocolon_bad.v | 2 +- test_regress/t/t_interface_gen10.v | 2 +- test_regress/t/t_interface_gen11.v | 2 +- test_regress/t/t_interface_gen5.v | 2 +- test_regress/t/t_interface_gen6.v | 2 +- test_regress/t/t_interface_gen7.v | 2 +- test_regress/t/t_interface_gen8.v | 2 +- test_regress/t/t_interface_gen9.v | 2 +- test_regress/t/t_interface_localparam.v | 2 +- test_regress/t/t_interface_mp_func.v | 2 +- .../t/t_interface_nested_struct_param.v | 97 ++- .../t/t_interface_param_another_bad.v | 2 +- .../t/t_jumps_uninit_destructor_call.v | 4 +- test_regress/t/t_lint_const_func_dpi_bad.v | 2 +- test_regress/t/t_lint_const_func_gen_bad.v | 2 +- test_regress/t/t_lint_infinite_bad.v | 2 +- test_regress/t/t_lint_once_bad.v | 2 +- test_regress/t/t_lint_only.v | 2 +- test_regress/t/t_lint_repeat_bad.v | 2 +- test_regress/t/t_lint_restore_bad.v | 2 +- test_regress/t/t_lint_restore_prag_bad.v | 2 +- test_regress/t/t_lint_subout_bad.v | 2 +- test_regress/t/t_lint_width.v | 2 +- test_regress/t/t_lint_width_bad.v | 2 +- test_regress/t/t_lparam_assign_iface_const.v | 29 +- .../t/t_lparam_assign_iface_typedef_bad.v | 14 +- test_regress/t/t_lparam_dep_iface0.v | 25 +- test_regress/t/t_lparam_dep_iface1.v | 27 +- test_regress/t/t_lparam_dep_iface10.v | 29 +- test_regress/t/t_lparam_dep_iface11.v | 33 +- test_regress/t/t_lparam_dep_iface12.v | 39 +- test_regress/t/t_lparam_dep_iface13.v | 66 +- test_regress/t/t_lparam_dep_iface14.v | 56 +- test_regress/t/t_lparam_dep_iface15.v | 50 +- test_regress/t/t_lparam_dep_iface16.v | 47 +- test_regress/t/t_lparam_dep_iface2.v | 28 +- test_regress/t/t_lparam_dep_iface3.v | 64 +- test_regress/t/t_lparam_dep_iface4.v | 31 +- test_regress/t/t_lparam_dep_iface5.v | 42 +- test_regress/t/t_lparam_dep_iface6.v | 37 +- test_regress/t/t_lparam_dep_iface7.v | 31 +- test_regress/t/t_lparam_dep_iface8.v | 33 +- test_regress/t/t_lparam_dep_iface9.v | 33 +- test_regress/t/t_mailbox_concurrent.v | 2 +- test_regress/t/t_math_width.v | 2 +- test_regress/t/t_mod_interface_clocking_bad.v | 2 +- test_regress/t/t_mod_longname.v | 2 +- test_regress/t/t_name_collision.v | 2 +- test_regress/t/t_opt_merge_cond_relaxed.v | 46 +- test_regress/t/t_package_abs.v | 2 +- test_regress/t/t_package_ddecl.v | 2 +- test_regress/t/t_param_default_override.v | 2 +- test_regress/t/t_param_pattern2.v | 2 +- test_regress/t/t_param_real.v | 2 +- test_regress/t/t_param_real2.v | 2 +- test_regress/t/t_param_type_cmp.v | 2 +- .../t/t_param_type_from_iface_struct.v | 60 +- test_regress/t/t_param_up_bad.v | 2 +- .../t/t_paramgraph_ascrange_prelim_cfg.v | 16 +- test_regress/t/t_paramgraph_bisect1.v | 53 +- test_regress/t/t_paramgraph_bits_corruption.v | 10 +- .../t/t_paramgraph_bits_iface_typedef.v | 42 +- test_regress/t/t_paramgraph_cloned_refdtype.v | 21 +- test_regress/t/t_paramgraph_comined_iface.v | 41 +- .../t/t_paramgraph_iface_array_ports.v | 16 +- test_regress/t/t_paramgraph_iface_cfg_zero.v | 14 +- test_regress/t/t_paramgraph_iface_deadmod.v | 16 +- .../t/t_paramgraph_iface_dependency1.v | 30 +- .../t/t_paramgraph_iface_dependency2.v | 24 +- .../t/t_paramgraph_iface_dependency3.v | 34 +- .../t/t_paramgraph_iface_param_from_port.v | 38 +- test_regress/t/t_paramgraph_iface_pin.v | 26 +- .../t/t_paramgraph_iface_port_typedef.v | 31 +- .../t/t_paramgraph_iface_template_mismatch.v | 22 +- .../t/t_paramgraph_iface_template_mismatch2.v | 22 +- .../t/t_paramgraph_iface_template_mismatch3.v | 26 +- .../t/t_paramgraph_iface_template_nested.v | 48 +- ...t_paramgraph_member_refdtype_iface_chain.v | 2 +- ..._paramgraph_member_refdtype_iface_struct.v | 2 +- ...paramgraph_member_refdtype_iface_typedef.v | 2 +- .../t_paramgraph_member_refdtype_pkg_iface.v | 14 +- test_regress/t/t_paramgraph_minimal_sibling.v | 29 +- .../t/t_paramgraph_nested_iface_typedef.v | 44 +- test_regress/t/t_paramgraph_param_not_const.v | 25 +- .../t/t_paramgraph_paramtype_default.v | 36 +- test_regress/t/t_paramgraph_refdtype_iface.v | 2 +- .../t/t_paramgraph_refdtype_unlinked.v | 12 +- test_regress/t/t_paramgraph_selbit_dtype.v | 85 +- ...t_paramgraph_simple_cache_localparam_cfg.v | 73 +- .../t/t_paramgraph_simple_cache_types_if.v | 51 +- test_regress/t/t_pp_lib.v | 2 +- test_regress/t/t_preproc_str_undef.v | 2 +- test_regress/t/t_process_propagation.v | 2 +- test_regress/t/t_process_task.v | 2 +- test_regress/t/t_public_clk.v | 2 +- test_regress/t/t_queue_insert_at_end.v | 2 +- test_regress/t/t_randomize_std_static.v | 9 +- test_regress/t/t_real_param.v | 2 +- test_regress/t/t_recursive_typedef_bad.v | 2 +- test_regress/t/t_select_bound3.v | 2 +- test_regress/t/t_selrange_iface_type_param.v | 550 +++++++------ test_regress/t/t_semaphore_concurrent.v | 2 +- test_regress/t/t_split_var_1_bad.v | 2 +- .../t/t_static_function_in_class_noparen.v | 2 +- test_regress/t/t_std_process_self.v | 2 +- test_regress/t/t_struct_genfor.v | 2 +- test_regress/t/t_structu_wide.v | 2 +- test_regress/t/t_sys_readmem_eof.v | 2 +- test_regress/t/t_timing_dynscope.v | 2 +- test_regress/t/t_timing_split.v | 2 +- test_regress/t/t_trace_split_cfuncs.v | 2 +- .../t/t_trace_split_cfuncs_dpi_export.v | 2 +- test_regress/t/t_type_param.v | 2 +- test_regress/t/t_udp_nonsequential_x.v | 2 +- test_regress/t/t_var_extern_method_lifetime.v | 2 +- test_regress/t/t_var_in_fork.v | 2 +- test_regress/t/t_x_rand_scoped_is_random.v | 2 +- 340 files changed, 7037 insertions(+), 6797 deletions(-) diff --git a/test_regress/t/t_a1_first_cc.v b/test_regress/t/t_a1_first_cc.v index 03a9a497f..5a21736e5 100644 --- a/test_regress/t/t_a1_first_cc.v +++ b/test_regress/t/t_a1_first_cc.v @@ -4,17 +4,14 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - - // Test loop - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // Test loop + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_alias_unsup.v b/test_regress/t/t_alias_unsup.v index 3fc958d2e..ca79ccc37 100644 --- a/test_regress/t/t_alias_unsup.v +++ b/test_regress/t/t_alias_unsup.v @@ -19,9 +19,9 @@ module t ( /*AUTOARG*/ input clk; - int cyc; - reg [63:0] crc; - reg [63:0] sum; + int cyc; + reg [63:0] crc; + reg [63:0] sum; // Values to swap and locations for the swapped values. wire [31:0] x_fwd = crc[31:0]; @@ -51,11 +51,11 @@ module t ( /*AUTOARG*/ // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; - end else if (cyc < 10) begin + end + else if (cyc < 10) begin sum <= '0; - end else - if (cyc < 90) begin - end else if (cyc == 99) begin + end + else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); `checkh(crc, 64'hc77bb9b3784ea091); // What checksum will we end up with (above print should match) diff --git a/test_regress/t/t_array_backw_index_bad.out b/test_regress/t/t_array_backw_index_bad.out index 4f63b9cb9..15104534a 100644 --- a/test_regress/t/t_array_backw_index_bad.out +++ b/test_regress/t/t_array_backw_index_bad.out @@ -1,30 +1,30 @@ -%Error: t/t_array_backw_index_bad.v:17:19: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]' +%Error: t/t_array_backw_index_bad.v:17:17: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]' : ... note: In instance 't' - 17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; - | ^ + 17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_array_backw_index_bad.v:18:20: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]' +%Error: t/t_array_backw_index_bad.v:18:18: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]' : ... note: In instance 't' - 18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; - | ^ -%Error: t/t_array_backw_index_bad.v:19:20: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]' + 18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; + | ^ +%Error: t/t_array_backw_index_bad.v:19:18: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]' : ... note: In instance 't' - 19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; - | ^ -%Error: t/t_array_backw_index_bad.v:20:21: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]' + 19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; + | ^ +%Error: t/t_array_backw_index_bad.v:20:19: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]' : ... note: In instance 't' - 20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; - | ^ -%Error: t/t_array_backw_index_bad.v:22:19: Slice selection index '[4:3]' outside data type's '[3:0]' - : ... note: In instance 't' - 22 | array_assign[4:3] = '{32'd4, 32'd3}; + 20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; | ^ -%Error: t/t_array_backw_index_bad.v:23:19: Slice selection index '[1:-1]' outside data type's '[3:0]' +%Error: t/t_array_backw_index_bad.v:22:17: Slice selection index '[4:3]' outside data type's '[3:0]' : ... note: In instance 't' - 23 | array_assign[1:-1] = '{32'd4, 32'd3}; - | ^ -%Error: t/t_array_backw_index_bad.v:23:28: Assignment pattern missed initializing elements: -1 + 22 | array_assign[4:3] = '{32'd4, 32'd3}; + | ^ +%Error: t/t_array_backw_index_bad.v:23:17: Slice selection index '[1:-1]' outside data type's '[3:0]' : ... note: In instance 't' - 23 | array_assign[1:-1] = '{32'd4, 32'd3}; - | ^~ + 23 | array_assign[1:-1] = '{32'd4, 32'd3}; + | ^ +%Error: t/t_array_backw_index_bad.v:23:26: Assignment pattern missed initializing elements: -1 + : ... note: In instance 't' + 23 | array_assign[1:-1] = '{32'd4, 32'd3}; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_array_backw_index_bad.v b/test_regress/t/t_array_backw_index_bad.v index fddcfa3a0..1651ce17e 100644 --- a/test_regress/t/t_array_backw_index_bad.v +++ b/test_regress/t/t_array_backw_index_bad.v @@ -6,27 +6,27 @@ module t; - logic [31:0] array_assign [3:0]; + logic [31:0] array_assign[3:0]; - logic [31:0] larray_assign [0:3]; + logic [31:0] larray_assign[0:3]; - logic [31:0] array_assign2 [6:3]; + logic [31:0] array_assign2[6:3]; - logic [31:0] larray_assign2 [3:6]; - initial begin - array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; - larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; - array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; - larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; + logic [31:0] larray_assign2[3:6]; + initial begin + array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; + larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; + array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; + larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; - array_assign[4:3] = '{32'd4, 32'd3}; - array_assign[1:-1] = '{32'd4, 32'd3}; - array_assign[1:1] = '{32'd4}; // Ok - larray_assign[1:1] = '{32'd4}; // Ok - array_assign2[4:4] = '{32'd4}; // Ok - larray_assign2[4:4] = '{32'd4}; // Ok + array_assign[4:3] = '{32'd4, 32'd3}; + array_assign[1:-1] = '{32'd4, 32'd3}; + array_assign[1:1] = '{32'd4}; // Ok + larray_assign[1:1] = '{32'd4}; // Ok + array_assign2[4:4] = '{32'd4}; // Ok + larray_assign2[4:4] = '{32'd4}; // Ok - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_compare.v b/test_regress/t/t_array_compare.v index e27d03a0f..ffae2101f 100644 --- a/test_regress/t/t_array_compare.v +++ b/test_regress/t/t_array_compare.v @@ -8,52 +8,52 @@ module t; - reg [3:0] array_1 [2:0]; - reg [3:0] array_2 [2:0]; - reg [3:0] array_3 [3:1]; + reg [3:0] array_1[2:0]; + reg [3:0] array_2[2:0]; + reg [3:0] array_3[3:1]; - reg [3:0] elem; + reg [3:0] elem; - reg array_1_ne_array_2; - reg array_1_eq_array_2; - reg array_1_ne_array_3; - reg array_1_eq_array_3; + reg array_1_ne_array_2; + reg array_1_eq_array_2; + reg array_1_ne_array_3; + reg array_1_eq_array_3; - initial begin - array_1[0] = 4'b1000; - array_1[1] = 4'b1000; - array_1[2] = 4'b1000; + initial begin + array_1[0] = 4'b1000; + array_1[1] = 4'b1000; + array_1[2] = 4'b1000; - array_2[0] = 4'b1000; - array_2[1] = 4'b1000; - array_2[2] = 4'b1000; + array_2[0] = 4'b1000; + array_2[1] = 4'b1000; + array_2[2] = 4'b1000; - array_3[1] = 4'b1000; - array_3[2] = 4'b0100; - array_3[3] = 4'b0100; + array_3[1] = 4'b1000; + array_3[2] = 4'b0100; + array_3[3] = 4'b0100; - array_1_ne_array_2 = array_1 != array_2; // 0 - array_1_eq_array_2 = array_1 == array_2; // 0 - array_1_ne_array_3 = array_1 != array_3; // 1 - array_1_eq_array_3 = array_1 == array_3; // 1 + array_1_ne_array_2 = array_1 != array_2; // 0 + array_1_eq_array_2 = array_1 == array_2; // 0 + array_1_ne_array_3 = array_1 != array_3; // 1 + array_1_eq_array_3 = array_1 == array_3; // 1 - //Not legal: array_rxor = ^ array_1; - //Not legal: array_rxnor = ^~ array_1; - //Not legal: array_ror = | array_1; - //Not legal: array_rand = & array_1; + //Not legal: array_rxor = ^ array_1; + //Not legal: array_rxnor = ^~ array_1; + //Not legal: array_ror = | array_1; + //Not legal: array_rand = & array_1; `ifdef TEST_VERBOSE - $write("array_1_ne_array2==%0d\n", array_1_ne_array_2); - $write("array_1_ne_array3==%0d\n", array_1_ne_array_3); + $write("array_1_ne_array2==%0d\n", array_1_ne_array_2); + $write("array_1_ne_array3==%0d\n", array_1_ne_array_3); `endif - if (array_1_ne_array_2 !== 0) $stop; - if (array_1_eq_array_2 !== 1) $stop; - if (array_1_ne_array_3 !== 1) $stop; - if (array_1_eq_array_3 !== 0) $stop; + if (array_1_ne_array_2 !== 0) $stop; + if (array_1_eq_array_2 !== 1) $stop; + if (array_1_ne_array_3 !== 1) $stop; + if (array_1_eq_array_3 !== 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_in_struct.v b/test_regress/t/t_array_in_struct.v index 9c331c894..73cdcea97 100644 --- a/test_regress/t/t_array_in_struct.v +++ b/test_regress/t/t_array_in_struct.v @@ -7,55 +7,51 @@ //bug991 module t; - typedef struct { - logic [31:0] arr [3:0]; - } a_t; + typedef struct {logic [31:0] arr[3:0];} a_t; - typedef struct { - logic [31:0] arr [0:3]; - } b_t; + typedef struct {logic [31:0] arr[0:3];} b_t; - a_t array_assign; - a_t array_other; + a_t array_assign; + a_t array_other; - b_t larray_assign; - b_t larray_other; + b_t larray_assign; + b_t larray_other; - initial begin - array_assign.arr[0] = 32'd1; - array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2}; + initial begin + array_assign.arr[0] = 32'd1; + array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2}; - array_other.arr[0] = array_assign.arr[0]+10; - array_other.arr[3:1] = array_assign.arr[3:1]; - if (array_other.arr[0] != 11) $stop; - if (array_other.arr[1] != 2) $stop; - if (array_other.arr[2] != 3) $stop; - if (array_other.arr[3] != 4) $stop; + array_other.arr[0] = array_assign.arr[0] + 10; + array_other.arr[3:1] = array_assign.arr[3:1]; + if (array_other.arr[0] != 11) $stop; + if (array_other.arr[1] != 2) $stop; + if (array_other.arr[2] != 3) $stop; + if (array_other.arr[3] != 4) $stop; - larray_assign.arr[0] = 32'd1; - larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2}; + larray_assign.arr[0] = 32'd1; + larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2}; - larray_other.arr[0] = larray_assign.arr[0]+10; - larray_other.arr[1:3] = larray_assign.arr[1:3]; - if (larray_other.arr[0] != 11) $stop; - if (larray_other.arr[1] != 4) $stop; - if (larray_other.arr[2] != 3) $stop; - if (larray_other.arr[3] != 2) $stop; + larray_other.arr[0] = larray_assign.arr[0] + 10; + larray_other.arr[1:3] = larray_assign.arr[1:3]; + if (larray_other.arr[0] != 11) $stop; + if (larray_other.arr[1] != 4) $stop; + if (larray_other.arr[2] != 3) $stop; + if (larray_other.arr[3] != 2) $stop; - larray_other.arr = '{5, 6, 7, 8}; - if (larray_other.arr[0] != 5) $stop; - if (larray_other.arr[1] != 6) $stop; - if (larray_other.arr[2] != 7) $stop; - if (larray_other.arr[3] != 8) $stop; + larray_other.arr = '{5, 6, 7, 8}; + if (larray_other.arr[0] != 5) $stop; + if (larray_other.arr[1] != 6) $stop; + if (larray_other.arr[2] != 7) $stop; + if (larray_other.arr[3] != 8) $stop; - larray_other.arr = larray_assign.arr; - if (larray_other.arr[0] != 1) $stop; - if (larray_other.arr[1] != 4) $stop; - if (larray_other.arr[2] != 3) $stop; - if (larray_other.arr[3] != 2) $stop; + larray_other.arr = larray_assign.arr; + if (larray_other.arr[0] != 1) $stop; + if (larray_other.arr[1] != 4) $stop; + if (larray_other.arr[2] != 3) $stop; + if (larray_other.arr[3] != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_index_increment.v b/test_regress/t/t_array_index_increment.v index b7588d035..567af8001 100644 --- a/test_regress/t/t_array_index_increment.v +++ b/test_regress/t/t_array_index_increment.v @@ -6,122 +6,124 @@ module t; - string test_string = "abcd"; + string test_string = "abcd"; - int array3d[2][3][4] = '{ - '{ - '{ 0, 1, 2, 3}, - '{ 4, 5, 6, 7}, - '{ 8, 9, 10, 11} - }, - '{ - '{ 12, 13, 14, 15}, - '{ 16, 17, 18, 19}, - '{ 20, 21, 22, 23} - } - }; - int pos; - int val; - int i; - byte b; + // verilog_format: off + int array3d[2][3][4] = '{ + '{'{ 0, 1, 2, 3}, + '{ 4, 5, 6, 7}, + '{ 8, 9, 10, 11} + }, + '{'{ 12, 13, 14, 15}, + '{ 16, 17, 18, 19}, + '{ 20, 21, 22, 23} + } + }; + // verilog_format: on + int pos; + int val; + int i; + byte b; - int data[4] = '{1, 2, 3, 4}; + int data[4] = '{1, 2, 3, 4}; - generate - genvar j; - int gdata[4]; - for (j=0; j < 5; j++) begin - initial if (j >= 5) $stop; - end + generate + genvar j; + int gdata[4]; + for (j = 0; j < 5; j++) begin + initial if (j >= 5) $stop; + end - for (j=0; j < 5; ++j) begin - initial if (j >= 5) $stop; - end + for (j = 0; j < 5; ++j) begin + initial if (j >= 5) $stop; + end - for (j=10; j >= 5; j--) begin - initial if (j < 5) $stop; - end + for (j = 10; j >= 5; j--) begin + initial if (j < 5) $stop; + end - for (j=10; j >= 5; --j) begin - initial if (j < 5) $stop; - end - endgenerate + for (j = 10; j >= 5; --j) begin + initial if (j < 5) $stop; + end + endgenerate - initial begin - pos = 0; + initial begin + pos = 0; + pos++; + if (pos != 1) $stop; + + array3d[0][0][0]++; + if (array3d[0][0][0] != 1) $stop; + + --array3d[0][0][0]; + if (array3d[0][0][0] != 0) $stop; + + pos = 2; + b = test_string[--pos]; + if (b !== "b") $stop; + if (pos !== 1) $stop; + + pos = 1; + b = test_string[++pos]; + if (b !== "c") $stop; + if (pos !== 2) $stop; + + pos = 3; + b = test_string[pos--]; + if (b !== "d") $stop; + if (pos !== 2) $stop; + + pos = 0; + b = test_string[pos++]; + if (b !== "a") $stop; + if (pos !== 1) $stop; + + pos = 0; + val = array3d[++pos][--pos][++pos]; + if (pos !== 1) $stop; + if (val !== 13) $stop; + + pos = 0; + val = array3d[++pos][pos--][++pos]; + if (pos !== 1) $stop; + if (val !== 17) $stop; + + for (i = 0; data[++i] < 4;) begin + // loop with multiple statements + pos = i; + val = data[i]; + end + + if (pos !== 2) $stop; + if (i !== 3) $stop; + if (val !== 3) $stop; + + i = 0; + while (data[ + i++ + ] < 4) begin + // loop with multiple statements + pos = i; + val = data[i]; + end + + if (pos !== 3) $stop; + if (i !== 4) $stop; + if (val !== 4) $stop; + + + pos = 0; + if (1 == 1) begin pos++; - if (pos != 1) $stop; + end + if (pos != 1) $stop; - array3d[0][0][0]++; - if (array3d[0][0][0] != 1) $stop; + pos = 0; + if (1 == 1) pos++; + if (pos != 1) $stop; - --array3d[0][0][0]; - if (array3d[0][0][0] != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; - pos = 2; - b = test_string[--pos]; - if (b !== "b") $stop; - if (pos !== 1) $stop; - - pos = 1; - b = test_string[++pos]; - if (b !== "c") $stop; - if (pos !== 2) $stop; - - pos = 3; - b = test_string[pos--]; - if (b !== "d") $stop; - if (pos !== 2) $stop; - - pos = 0; - b = test_string[pos++]; - if (b !== "a") $stop; - if (pos !== 1) $stop; - - pos = 0; - val = array3d[++pos][--pos][++pos]; - if (pos !== 1) $stop; - if (val !== 13) $stop; - - pos = 0; - val = array3d[++pos][pos--][++pos]; - if (pos !== 1) $stop; - if (val !== 17) $stop; - - for (i=0; data[++i]<4;) begin - // loop with multiple statements - pos = i; - val = data[i]; - end - - if (pos !== 2) $stop; - if (i !== 3) $stop; - if (val !== 3) $stop; - - i = 0; - while (data[i++]<4) begin - // loop with multiple statements - pos = i; - val = data[i]; - end - - if (pos !== 3) $stop; - if (i !== 4) $stop; - if (val !== 4) $stop; - - - pos = 0; - if (1 == 1) begin - pos++; - end - if (pos != 1) $stop; - - pos = 0; - if (1 == 1) pos++; - if (pos != 1) $stop; - - $write("*-* All Finished *-*\n"); - $finish; - - end + end endmodule diff --git a/test_regress/t/t_array_index_side.v b/test_regress/t/t_array_index_side.v index 5992f9898..fb00ee94b 100644 --- a/test_regress/t/t_array_index_side.v +++ b/test_regress/t/t_array_index_side.v @@ -10,47 +10,47 @@ // verilog_format: on class Cls; - int m_index; + int m_index; - function automatic int get_index(); - int rtn; - rtn = m_index; - ++m_index; + function automatic int get_index(); + int rtn; + rtn = m_index; + ++m_index; `ifdef VERILATOR - return $c(rtn); // Avoid optimizations + return $c(rtn); // Avoid optimizations `else - return rtn; + return rtn; `endif - endfunction + endfunction endclass module t; - Cls cls; - int array[10]; + Cls cls; + int array[10]; - initial begin - cls = new; - // Common UVM construct 'id_cnt[get_id()]++;' - // Properly avoid/handle SIDEEFF warnings - cls.m_index = 5; - array[5] = 50; - array[6] = 60; - array[7] = 70; - array[8] = 80; + initial begin + cls = new; + // Common UVM construct 'id_cnt[get_id()]++;' + // Properly avoid/handle SIDEEFF warnings + cls.m_index = 5; + array[5] = 50; + array[6] = 60; + array[7] = 70; + array[8] = 80; - array[cls.get_index()]++; - `checkd(array[5], 51); - array[cls.get_index()]++; - `checkd(array[6], 61); + array[cls.get_index()]++; + `checkd(array[5], 51); + array[cls.get_index()]++; + `checkd(array[6], 61); - ++array[cls.get_index()]; - `checkd(array[7], 71); - ++array[cls.get_index()]; - `checkd(array[8], 81); + ++array[cls.get_index()]; + `checkd(array[7], 71); + ++array[cls.get_index()]; + `checkd(array[8], 81); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_list_bad.out b/test_regress/t/t_array_list_bad.out index c298dd605..5d24a7452 100644 --- a/test_regress/t/t_array_list_bad.out +++ b/test_regress/t/t_array_list_bad.out @@ -1,12 +1,12 @@ -%Error: t/t_array_list_bad.v:38:25: Assignment pattern missed initializing elements: 'logic' 't3' +%Error: t/t_array_list_bad.v:37:21: Assignment pattern missed initializing elements: 'logic' 't3' : ... note: In instance 't' - 38 | test_out <= '{'0, '0}; - | ^~ + 37 | test_out <= '{'0, '0}; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-WIDTHEXPAND: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. +%Warning-WIDTHEXPAND: t/t_array_list_bad.v:37:18: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. : ... note: In instance 't' - 38 | test_out <= '{'0, '0}; - | ^~ + 37 | test_out <= '{'0, '0}; + | ^~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_array_list_bad.v b/test_regress/t/t_array_list_bad.v index 8841a602e..8ac05b927 100644 --- a/test_regress/t/t_array_list_bad.v +++ b/test_regress/t/t_array_list_bad.v @@ -5,38 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - typedef struct packed { - logic t1; - logic t2; - logic t3; - } type_t; + typedef struct packed { + logic t1; + logic t2; + logic t3; + } type_t; endpackage : pkg -module t - ( - input logic sys_clk, - input logic sys_rst_n, - input logic sys_ena, +module t ( + input logic sys_clk, + input logic sys_rst_n, + input logic sys_ena, - input pkg::type_t test_in, - output pkg::type_t test_out - ); + input pkg::type_t test_in, + output pkg::type_t test_out +); - import pkg::*; + import pkg::*; - always_ff @(posedge sys_clk or negedge sys_rst_n) begin - if (~sys_rst_n) begin - test_out <= '{'0, '0, '0}; + always_ff @(posedge sys_clk or negedge sys_rst_n) begin + if (~sys_rst_n) begin + test_out <= '{'0, '0, '0}; + end + else begin + if (sys_ena) begin + test_out.t1 <= ~test_in.t1; + test_out.t2 <= ~test_in.t2; + test_out.t3 <= ~test_in.t3; end else begin - if(sys_ena) begin - test_out.t1 <= ~test_in.t1; - test_out.t2 <= ~test_in.t2; - test_out.t3 <= ~test_in.t3; - end - else begin - test_out <= '{'0, '0}; /* Inconsistent array list; */ - end + test_out <= '{'0, '0}; /* Inconsistent array list; */ end - end -endmodule: t + end + end +endmodule : t diff --git a/test_regress/t/t_array_mda.v b/test_regress/t/t_array_mda.v index bfa7116e9..3259fad33 100644 --- a/test_regress/t/t_array_mda.v +++ b/test_regress/t/t_array_mda.v @@ -4,66 +4,66 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // msg2946 - int A [7][1], B [8][1]; - int a [1], b [1]; - always_ff @(posedge clk) begin - a <= A[crc[2:0]]; - b <= B[crc[2:0]]; - end - wire [63:0] result = {a[0], b[0]}; + // msg2946 + int A[7][1], B[8][1]; + int a[1], b[1]; + always_ff @(posedge clk) begin + a <= A[crc[2:0]]; + b <= B[crc[2:0]]; + end + wire [63:0] result = {a[0], b[0]}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - A[0][0] <= 32'h1_0; - A[1][0] <= 32'h1_1; - A[2][0] <= 32'h1_2; - A[3][0] <= 32'h1_3; - A[4][0] <= 32'h1_4; - A[5][0] <= 32'h1_5; - A[6][0] <= 32'h1_6; - B[0][0] <= 32'h2_0; - B[1][0] <= 32'h2_1; - B[2][0] <= 32'h2_2; - B[3][0] <= 32'h2_3; - B[4][0] <= 32'h2_4; - B[5][0] <= 32'h2_5; - B[6][0] <= 32'h2_6; - B[7][0] <= 32'h2_7; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h619f75c3a6d948bd - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + A[0][0] <= 32'h1_0; + A[1][0] <= 32'h1_1; + A[2][0] <= 32'h1_2; + A[3][0] <= 32'h1_3; + A[4][0] <= 32'h1_4; + A[5][0] <= 32'h1_5; + A[6][0] <= 32'h1_6; + B[0][0] <= 32'h2_0; + B[1][0] <= 32'h2_1; + B[2][0] <= 32'h2_2; + B[3][0] <= 32'h2_3; + B[4][0] <= 32'h2_4; + B[5][0] <= 32'h2_5; + B[6][0] <= 32'h2_6; + B[7][0] <= 32'h2_7; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h619f75c3a6d948bd + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_array_method_bad.out b/test_regress/t/t_array_method_bad.out index 8e2cf6c76..6c6358d9f 100644 --- a/test_regress/t/t_array_method_bad.out +++ b/test_regress/t/t_array_method_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_array_method_bad.v:11:9: Unknown built-in array method 'mex' +%Error: t/t_array_method_bad.v:11:7: Unknown built-in array method 'mex' : ... note: In instance 't' - 11 | q.mex; - | ^~~ + 11 | q.mex; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_array_method_bad.v b/test_regress/t/t_array_method_bad.v index 5f8250831..b27f98591 100644 --- a/test_regress/t/t_array_method_bad.v +++ b/test_regress/t/t_array_method_bad.v @@ -5,12 +5,12 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - int q[5]; + initial begin + int q[5]; - q.mex; + q.mex; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_method_map.out b/test_regress/t/t_array_method_map.out index 054088ab2..3e1bac262 100644 --- a/test_regress/t/t_array_method_map.out +++ b/test_regress/t/t_array_method_map.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_array_method_map.v:19:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5) +%Error-UNSUPPORTED: t/t_array_method_map.v:19:13: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' - 19 | res = a.map(el) with (el == 200); - | ^~~ + 19 | res = a.map(el) with (el == 200); + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_array_method_map.v:19:15: Unknown built-in array method 'map' +%Error: t/t_array_method_map.v:19:13: Unknown built-in array method 'map' : ... note: In instance 't' - 19 | res = a.map(el) with (el == 200); - | ^~~ + 19 | res = a.map(el) with (el == 200); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_array_method_map.v b/test_regress/t/t_array_method_map.v index 8025971f7..849307035 100644 --- a/test_regress/t/t_array_method_map.v +++ b/test_regress/t/t_array_method_map.v @@ -11,15 +11,15 @@ module t; - initial begin - automatic int res[]; - automatic int a[3] = '{100, 200, 300}; + initial begin + automatic int res[]; + automatic int a[3] = '{100, 200, 300}; - // TODO results not known to be correct - res = a.map(el) with (el == 200); - `checkh(res.size, 3); - `checkh(res[0], 0); - `checkh(res[1], 1); - `checkh(res[2], 0); - end + // TODO results not known to be correct + res = a.map(el) with (el == 200); + `checkh(res.size, 3); + `checkh(res[0], 0); + `checkh(res[1], 1); + `checkh(res[2], 0); + end endmodule diff --git a/test_regress/t/t_array_non_blocking_loop.v b/test_regress/t/t_array_non_blocking_loop.v index f7bab41db..e7ba5a267 100644 --- a/test_regress/t/t_array_non_blocking_loop.v +++ b/test_regress/t/t_array_non_blocking_loop.v @@ -5,34 +5,31 @@ // SPDX-License-Identifier: CC0-1.0 -interface intf - #( - parameter int WRITE_DATA_WIDTH) (); - logic [WRITE_DATA_WIDTH-1:0] writedata; +interface intf #( + parameter int WRITE_DATA_WIDTH +) (); + logic [WRITE_DATA_WIDTH-1:0] writedata; endinterface -module t( /*AUTOARG*/ +module t ( /*AUTOARG*/ clk ); - input clk; - generate - genvar num_chunks; - for (num_chunks = 1; num_chunks <= 2; num_chunks++) begin : gen_n - localparam int decoded_width = 55 * num_chunks; - intf #( - .WRITE_DATA_WIDTH(decoded_width)) - the_intf (); - always @(posedge clk) begin - for (int i = 0; i < decoded_width; i++) - the_intf.writedata[i] <= '1; - $display("%0d", the_intf.writedata); - end - end - endgenerate + input clk; + generate + genvar num_chunks; + for (num_chunks = 1; num_chunks <= 2; num_chunks++) begin : gen_n + localparam int decoded_width = 55 * num_chunks; + intf #(.WRITE_DATA_WIDTH(decoded_width)) the_intf (); + always @(posedge clk) begin + for (int i = 0; i < decoded_width; i++) the_intf.writedata[i] <= '1; + $display("%0d", the_intf.writedata); + end + end + endgenerate - // finish report - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // finish report + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_packed_endian.v b/test_regress/t/t_array_packed_endian.v index 43787bd2a..bf2ab8c90 100644 --- a/test_regress/t/t_array_packed_endian.v +++ b/test_regress/t/t_array_packed_endian.v @@ -4,28 +4,28 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: off + +typedef struct packed {logic [7:0] a;} tb_t; typedef struct packed { - logic [7:0] a; -} tb_t; - -typedef struct packed { - // verilator lint_off ASCRANGE - logic [0:7] a; - // verilator lint_on ASCRANGE + // verilator lint_off ASCRANGE + logic [0:7] a; + // verilator lint_on ASCRANGE } tl_t; typedef struct packed { - logic [7:0] bb; - // verilator lint_off ASCRANGE - tb_t [0:1] cbl; - tb_t [1:0] cbb; - tl_t [0:1] cll; - tl_t [1:0] clb; - logic [0:7] dl; - // verilator lint_on ASCRANGE + logic [7:0] bb; + // verilator lint_off ASCRANGE + tb_t [0:1] cbl; + tb_t [1:0] cbb; + tl_t [0:1] cll; + tl_t [1:0] clb; + logic [0:7] dl; + // verilator lint_on ASCRANGE } t2; logic [2:0][31:0] test2l; @@ -36,60 +36,60 @@ logic [0:2][31:0] test1b; logic [2:0][31:0] test1l; module t; - t2 t; - initial begin - t = 80'hcd_1f2f3f4f_5f6f7f8f_c2; - `checkh(t.bb, 8'hcd); - `checkh(t.cbl[0].a, 8'h1f); - `checkh(t.cbl[1].a, 8'h2f); - `checkh(t.cbb[0].a, 8'h4f); - `checkh(t.cbb[1].a, 8'h3f); - `checkh(t.cll[0].a, 8'h5f); - `checkh(t.cll[1].a, 8'h6f); - `checkh(t.clb[0].a, 8'h8f); - `checkh(t.clb[1].a, 8'h7f); - `checkh(t.dl, 8'hc2); + t2 t; + initial begin + t = 80'hcd_1f2f3f4f_5f6f7f8f_c2; + `checkh(t.bb, 8'hcd); + `checkh(t.cbl[0].a, 8'h1f); + `checkh(t.cbl[1].a, 8'h2f); + `checkh(t.cbb[0].a, 8'h4f); + `checkh(t.cbb[1].a, 8'h3f); + `checkh(t.cll[0].a, 8'h5f); + `checkh(t.cll[1].a, 8'h6f); + `checkh(t.clb[0].a, 8'h8f); + `checkh(t.clb[1].a, 8'h7f); + `checkh(t.dl, 8'hc2); - t = '0; - t.bb = 8'h13; - t.cbl[0].a = 8'hac; - t.cbl[1].a = 8'had; - t.cbb[0].a = 8'hae; - t.cbb[1].a = 8'haf; - t.cll[0].a = 8'hbc; - t.cll[1].a = 8'hbd; - t.clb[0].a = 8'hbe; - t.clb[1].a = 8'hbf; - t.dl = 8'h31; - `checkh(t, 80'h13_acadafae_bcbdbfbe_31); + t = '0; + t.bb = 8'h13; + t.cbl[0].a = 8'hac; + t.cbl[1].a = 8'had; + t.cbb[0].a = 8'hae; + t.cbb[1].a = 8'haf; + t.cll[0].a = 8'hbc; + t.cll[1].a = 8'hbd; + t.clb[0].a = 8'hbe; + t.clb[1].a = 8'hbf; + t.dl = 8'h31; + `checkh(t, 80'h13_acadafae_bcbdbfbe_31); - t = '0; - t.bb[7] = 1'b1; - t.cbl[1].a[1] = 1'b1; - t.cbb[1].a[2] = 1'b1; - t.cll[1].a[3] = 1'b1; - t.clb[1].a[4] = 1'b1; - t.dl[7] = 1'b1; - `checkh(t, 80'h80_0002040000100800_01); + t = '0; + t.bb[7] = 1'b1; + t.cbl[1].a[1] = 1'b1; + t.cbb[1].a[2] = 1'b1; + t.cll[1].a[3] = 1'b1; + t.clb[1].a[4] = 1'b1; + t.dl[7] = 1'b1; + `checkh(t, 80'h80_0002040000100800_01); - test1b = '{0, 1, 2}; - test1l = test1b; - test2l = '{2, 1, 0}; - test2b = test2l; - `checkh(test2l[0], 0); - `checkh(test2l[2], 2); - `checkh(test2l, {32'h2, 32'h1, 32'h0}); - `checkh(test2b[0], 2); - `checkh(test2b[2], 0); - `checkh(test2b, {32'h2, 32'h1, 32'h0}); - `checkh(test1b[0], 0); - `checkh(test1b[2], 2); - `checkh(test1b, {32'h0, 32'h1, 32'h2}); - `checkh(test1l[0], 2); - `checkh(test1l[2], 0); - `checkh(test1l, {32'h0, 32'h1, 32'h2}); + test1b = '{0, 1, 2}; + test1l = test1b; + test2l = '{2, 1, 0}; + test2b = test2l; + `checkh(test2l[0], 0); + `checkh(test2l[2], 2); + `checkh(test2l, {32'h2, 32'h1, 32'h0}); + `checkh(test2b[0], 2); + `checkh(test2b[2], 0); + `checkh(test2b, {32'h2, 32'h1, 32'h0}); + `checkh(test1b[0], 0); + `checkh(test1b[2], 2); + `checkh(test1b, {32'h0, 32'h1, 32'h2}); + `checkh(test1l[0], 2); + `checkh(test1l[2], 0); + `checkh(test1l, {32'h0, 32'h1, 32'h2}); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_packed_sign.v b/test_regress/t/t_array_packed_sign.v index 0f39b5505..7ee6f23aa 100644 --- a/test_regress/t/t_array_packed_sign.v +++ b/test_regress/t/t_array_packed_sign.v @@ -11,50 +11,50 @@ // unless they are of a named type declared as signed. module t; - typedef logic signed [2:0] named_t; - typedef named_t [1:0] named_named_t; - typedef logic signed [1:0][2:0] named_unnamed_t; + typedef logic signed [2:0] named_t; + typedef named_t [1:0] named_named_t; + typedef logic signed [1:0][2:0] named_unnamed_t; - named_named_t [1:0] named_named; - named_unnamed_t [1:0] named_unnamed; - logic signed [1:0][1:0][2:0] unnamed; + named_named_t [1:0] named_named; + named_unnamed_t [1:0] named_unnamed; + logic signed [1:0][1:0][2:0] unnamed; - initial begin - // Set 1 to MSB(=sign bit) - named_named = 12'b100000_000000; - named_unnamed = 12'b100000_000000; - unnamed = 12'b100000_000000; + initial begin + // Set 1 to MSB(=sign bit) + named_named = 12'b100000_000000; + named_unnamed = 12'b100000_000000; + unnamed = 12'b100000_000000; - if ($signed((named_named >>> 1) >> 11) != 0) begin - $stop; - end - if ($signed((named_named[1] >>> 1) >> 5) != 0) begin - $stop; - end - if ($signed((named_named[1][1] >>> 1) >> 2) != 1) begin - $stop; - end + if ($signed((named_named >>> 1) >> 11) != 0) begin + $stop; + end + if ($signed((named_named[1] >>> 1) >> 5) != 0) begin + $stop; + end + if ($signed((named_named[1][1] >>> 1) >> 2) != 1) begin + $stop; + end - if ($signed((named_unnamed >>> 1) >> 11) != 0) begin - $stop; - end - if ($signed((named_unnamed[1] >>> 1) >> 5) != 1) begin - $stop; - end - if ($signed((named_unnamed[1][1] >>> 1) >> 2) != 0) begin - $stop; - end + if ($signed((named_unnamed >>> 1) >> 11) != 0) begin + $stop; + end + if ($signed((named_unnamed[1] >>> 1) >> 5) != 1) begin + $stop; + end + if ($signed((named_unnamed[1][1] >>> 1) >> 2) != 0) begin + $stop; + end - if ($signed((unnamed >>> 1) >> 11) != 1) begin - $stop;// - end - if ($signed((unnamed[1] >>> 1) >> 5) != 0) begin - $stop; - end - if ($signed((unnamed[1][1] >>> 1) >> 2) != 0) begin - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + if ($signed((unnamed >>> 1) >> 11) != 1) begin + $stop; // + end + if ($signed((unnamed[1] >>> 1) >> 5) != 0) begin + $stop; + end + if ($signed((unnamed[1][1] >>> 1) >> 2) != 0) begin + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_packed_sysfunct.v b/test_regress/t/t_array_packed_sysfunct.v index fa081a1c3..e31d38929 100644 --- a/test_regress/t/t_array_packed_sysfunct.v +++ b/test_regress/t/t_array_packed_sysfunct.v @@ -4,168 +4,167 @@ // SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk + ); - input clk; + // parameters for array sizes + localparam WA = 4; + localparam WB = 6; + localparam WC = 8; - // parameters for array sizes - localparam WA = 4; - localparam WB = 6; - localparam WC = 8; + // 2D packed arrays + logic [WA+1:2] [WB+1:2] [WC+1:2] array_dsc; // descending range array + /* verilator lint_off ASCRANGE */ + logic [2:WA+1] [2:WB+1] [2:WC+1] array_asc; // ascending range array + /* verilator lint_on ASCRANGE */ - // 2D packed arrays - logic [WA+1:2] [WB+1:2] [WC+1:2] array_dsc; // descending range array - /* verilator lint_off ASCRANGE */ - logic [2:WA+1] [2:WB+1] [2:WC+1] array_asc; // ascending range array - /* verilator lint_on ASCRANGE */ + logic [1:0] array_unpk [3:2][1:0]; - logic [1:0] array_unpk [3:2][1:0]; + integer cnt = 0; + integer slc = 0; // slice type + integer dim = 0; // dimension + integer wdt = 0; // width - integer cnt = 0; - integer slc = 0; // slice type - integer dim = 0; // dimension - integer wdt = 0; // width - - initial begin - `checkh($dimensions (array_unpk), 3); + initial begin + `checkh($dimensions (array_unpk), 3); `ifndef VCS - `checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009 + `checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009 `endif - `checkh($bits (array_unpk), 2*2*2); - `checkh($low (array_unpk), 2); - `checkh($high (array_unpk), 3); - `checkh($left (array_unpk), 3); - `checkh($right(array_unpk), 2); - `checkh($increment(array_unpk), 1); - `checkh($size (array_unpk), 2); - end + `checkh($bits (array_unpk), 2*2*2); + `checkh($low (array_unpk), 2); + `checkh($high (array_unpk), 3); + `checkh($left (array_unpk), 3); + `checkh($right(array_unpk), 2); + `checkh($increment(array_unpk), 1); + `checkh($size (array_unpk), 2); + end - // event counter - always @ (posedge clk) begin - cnt <= cnt + 1; - end + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end - // finish report - always @ (posedge clk) - if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // finish report + always @ (posedge clk) + if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin + $write("*-* All Finished *-*\n"); + $finish; + end - integer slc_next; + integer slc_next; - // calculation of dimention sizes - always @ (posedge clk) begin - // slicing type counter - case (cnt[3:2]) - 2'd0 : begin slc_next = 0; end // full array - 2'd1 : begin slc_next = 1; end // single array element - 2'd2 : begin slc_next = 2; end // half array - default: begin slc_next = 0; end - endcase - slc <= slc_next; - // dimension counter - case (cnt[1:0]) - 2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end - 2'd1 : begin dim <= 2; wdt <= WB; end - 2'd2 : begin dim <= 3; wdt <= WC; end - default: begin dim <= 0; wdt <= 0; end - endcase - end + // calculation of dimention sizes + always @ (posedge clk) begin + // slicing type counter + case (cnt[3:2]) + 2'd0 : begin slc_next = 0; end // full array + 2'd1 : begin slc_next = 1; end // single array element + 2'd2 : begin slc_next = 2; end // half array + default: begin slc_next = 0; end + endcase + slc <= slc_next; + // dimension counter + case (cnt[1:0]) + 2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end + 2'd1 : begin dim <= 2; wdt <= WB; end + 2'd2 : begin dim <= 3; wdt <= WC; end + default: begin dim <= 0; wdt <= 0; end + endcase + end - always @ (posedge clk) begin + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt); + $write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt); `endif - if (cnt[30:4]==1) begin - // descending range - if (slc==0) begin - // full array - `checkh($dimensions (array_dsc), 3); - `checkh($bits (array_dsc), WA*WB*WC); - if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_dsc, dim), wdt+1); - `checkh($right (array_dsc, dim), 2 ); - `checkh($low (array_dsc, dim), 2 ); - `checkh($high (array_dsc, dim), wdt+1); - `checkh($increment (array_dsc, dim), 1 ); - `checkh($size (array_dsc, dim), wdt ); - end - end else if (slc==1) begin - // single array element - `checkh($dimensions (array_dsc[2]), 2); - `checkh($bits (array_dsc[2]), WB*WC); - if ((dim>=2)&&(dim<=3)) begin - `checkh($left (array_dsc[2], dim-1), wdt+1); - `checkh($right (array_dsc[2], dim-1), 2 ); - `checkh($low (array_dsc[2], dim-1), 2 ); - `checkh($high (array_dsc[2], dim-1), wdt+1); - `checkh($increment (array_dsc[2], dim-1), 1 ); - `checkh($size (array_dsc[2], dim-1), wdt ); - end + if (cnt[30:4]==1) begin + // descending range + if (slc==0) begin + // full array + `checkh($dimensions (array_dsc), 3); + `checkh($bits (array_dsc), WA*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_dsc, dim), wdt+1); + `checkh($right (array_dsc, dim), 2 ); + `checkh($low (array_dsc, dim), 2 ); + `checkh($high (array_dsc, dim), wdt+1); + `checkh($increment (array_dsc, dim), 1 ); + `checkh($size (array_dsc, dim), wdt ); + end + end else if (slc==1) begin + // single array element + `checkh($dimensions (array_dsc[2]), 2); + `checkh($bits (array_dsc[2]), WB*WC); + if ((dim>=2)&&(dim<=3)) begin + `checkh($left (array_dsc[2], dim-1), wdt+1); + `checkh($right (array_dsc[2], dim-1), 2 ); + `checkh($low (array_dsc[2], dim-1), 2 ); + `checkh($high (array_dsc[2], dim-1), wdt+1); + `checkh($increment (array_dsc[2], dim-1), 1 ); + `checkh($size (array_dsc[2], dim-1), wdt ); + end `ifndef VERILATOR // Unsupported slices don't maintain size correctly - end else if (slc==2) begin - // half array - `checkh($dimensions (array_dsc[WA/2+1:2]), 3); - `checkh($bits (array_dsc[WA/2+1:2]), WA/2*WB*WC); - if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_dsc[WA/2+1:2], dim), wdt+1); - `checkh($right (array_dsc[WA/2+1:2], dim), 2 ); - `checkh($low (array_dsc[WA/2+1:2], dim), 2 ); - `checkh($high (array_dsc[WA/2+1:2], dim), wdt+1); - `checkh($increment (array_dsc[WA/2+1:2], dim), 1 ); - `checkh($size (array_dsc[WA/2+1:2], dim), wdt); - end + end else if (slc==2) begin + // half array + `checkh($dimensions (array_dsc[WA/2+1:2]), 3); + `checkh($bits (array_dsc[WA/2+1:2]), WA/2*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_dsc[WA/2+1:2], dim), wdt+1); + `checkh($right (array_dsc[WA/2+1:2], dim), 2 ); + `checkh($low (array_dsc[WA/2+1:2], dim), 2 ); + `checkh($high (array_dsc[WA/2+1:2], dim), wdt+1); + `checkh($increment (array_dsc[WA/2+1:2], dim), 1 ); + `checkh($size (array_dsc[WA/2+1:2], dim), wdt); + end `endif - end - end else if (cnt[30:4]==2) begin - // ascending range - if (slc==0) begin - // full array - `checkh($dimensions (array_asc), 3); - `checkh($bits (array_asc), WA*WB*WC); - if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_asc, dim), 2 ); - `checkh($right (array_asc, dim), wdt+1); - `checkh($low (array_asc, dim), 2 ); - `checkh($high (array_asc, dim), wdt+1); - `checkh($increment (array_asc, dim), -1 ); - `checkh($size (array_asc, dim), wdt ); - end - end else if (slc==1) begin - // single array element - `checkh($dimensions (array_asc[2]), 2); - `checkh($bits (array_asc[2]), WB*WC); - if ((dim>=2)&&(dim<=3)) begin - `checkh($left (array_asc[2], dim-1), 2 ); - `checkh($right (array_asc[2], dim-1), wdt+1); - `checkh($low (array_asc[2], dim-1), 2 ); - `checkh($high (array_asc[2], dim-1), wdt+1); - `checkh($increment (array_asc[2], dim-1), -1 ); - `checkh($size (array_asc[2], dim-1), wdt ); - end -`ifndef VERILATOR // Unsupported slices don't maintain size correctly - end else if (slc==2) begin - // half array - `checkh($dimensions (array_asc[2:WA/2+1]), 3); - `checkh($bits (array_asc[2:WA/2+1]), WA/2*WB*WC); - if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_asc[2:WA/2+1], dim), 2 ); - `checkh($right (array_asc[2:WA/2+1], dim), wdt+1); - `checkh($low (array_asc[2:WA/2+1], dim), 2 ); - `checkh($high (array_asc[2:WA/2+1], dim), wdt+1); - `checkh($increment (array_asc[2:WA/2+1], dim), -1 ); - `checkh($size (array_asc[2:WA/2+1], dim), wdt ); - end -`endif - end end - end + end else if (cnt[30:4]==2) begin + // ascending range + if (slc==0) begin + // full array + `checkh($dimensions (array_asc), 3); + `checkh($bits (array_asc), WA*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_asc, dim), 2 ); + `checkh($right (array_asc, dim), wdt+1); + `checkh($low (array_asc, dim), 2 ); + `checkh($high (array_asc, dim), wdt+1); + `checkh($increment (array_asc, dim), -1 ); + `checkh($size (array_asc, dim), wdt ); + end + end else if (slc==1) begin + // single array element + `checkh($dimensions (array_asc[2]), 2); + `checkh($bits (array_asc[2]), WB*WC); + if ((dim>=2)&&(dim<=3)) begin + `checkh($left (array_asc[2], dim-1), 2 ); + `checkh($right (array_asc[2], dim-1), wdt+1); + `checkh($low (array_asc[2], dim-1), 2 ); + `checkh($high (array_asc[2], dim-1), wdt+1); + `checkh($increment (array_asc[2], dim-1), -1 ); + `checkh($size (array_asc[2], dim-1), wdt ); + end +`ifndef VERILATOR // Unsupported slices don't maintain size correctly + end else if (slc==2) begin + // half array + `checkh($dimensions (array_asc[2:WA/2+1]), 3); + `checkh($bits (array_asc[2:WA/2+1]), WA/2*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_asc[2:WA/2+1], dim), 2 ); + `checkh($right (array_asc[2:WA/2+1], dim), wdt+1); + `checkh($low (array_asc[2:WA/2+1], dim), 2 ); + `checkh($high (array_asc[2:WA/2+1], dim), wdt+1); + `checkh($increment (array_asc[2:WA/2+1], dim), -1 ); + `checkh($size (array_asc[2:WA/2+1], dim), wdt ); + end +`endif + end + end + end endmodule diff --git a/test_regress/t/t_array_packed_write_read.v b/test_regress/t/t_array_packed_write_read.v index 9fca1c2cc..1628d4907 100644 --- a/test_regress/t/t_array_packed_write_read.v +++ b/test_regress/t/t_array_packed_write_read.v @@ -4,145 +4,143 @@ // SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // parameters for array sizes + localparam WA = 8; // address dimension size + localparam WB = 8; // bit dimension size - // parameters for array sizes - localparam WA = 8; // address dimension size - localparam WB = 8; // bit dimension size + localparam NO = 10; // number of access events - localparam NO = 10; // number of access events + // 2D packed arrays + logic [WA-1:0][WB-1:0] array_dsc; // descending range array + /* verilator lint_off ASCRANGE */ + logic [0:WA-1][0:WB-1] array_asc; // ascending range array + /* verilator lint_on ASCRANGE */ - // 2D packed arrays - logic [WA-1:0] [WB-1:0] array_dsc; // descending range array - /* verilator lint_off ASCRANGE */ - logic [0:WA-1] [0:WB-1] array_asc; // ascending range array - /* verilator lint_on ASCRANGE */ + integer cnt = 0; - integer cnt = 0; + // msg926 + logic [3:0][31:0] packedArray; + initial packedArray = '0; - // msg926 - logic [3:0][31:0] packedArray; - initial packedArray = '0; + // event counter + always @(posedge clk) begin + cnt <= cnt + 1; + end - // event counter - always @ (posedge clk) begin - cnt <= cnt + 1; - end - - // finish report - always @ (posedge clk) - if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin + // finish report + always @(posedge clk) + if ((cnt[30:2] == NO) && (cnt[1:0] == 2'd0)) begin $write("*-* All Finished *-*\n"); $finish; - end + end - // descending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaaults (all bits to 0) - if (cnt[30:2]==0) array_dsc <= '0; - else if (cnt[30:2]==1) array_dsc <= '0; - else if (cnt[30:2]==2) array_dsc <= '0; - else if (cnt[30:2]==3) array_dsc <= '0; - else if (cnt[30:2]==4) array_dsc <= '0; - else if (cnt[30:2]==5) array_dsc <= '0; - else if (cnt[30:2]==6) array_dsc <= '0; - else if (cnt[30:2]==7) array_dsc <= '0; - else if (cnt[30:2]==8) array_dsc <= '0; - else if (cnt[30:2]==9) array_dsc <= '0; - end else if (cnt[1:0]==2'd1) begin - // write value to array - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) array_dsc <= {WA *WB +0{1'b1}}; - else if (cnt[30:2]==2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; - else if (cnt[30:2]==9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; - end else if (cnt[1:0]==2'd2) begin - // check array value - if (cnt[30:2]==0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end - end else if (cnt[1:0]==2'd3) begin - // read value from array (not a very good test for now) - if (cnt[30:2]==0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end - else if (cnt[30:2]==1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end - else if (cnt[30:2]==9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end - end + // descending range + // verilog_format: off + always @ (posedge clk) + if (cnt[1:0] == 2'd0) begin + // initialize to defaaults (all bits to 0) + if (cnt[30:2] == 0) array_dsc <= '0; + else if (cnt[30:2] == 1) array_dsc <= '0; + else if (cnt[30:2] == 2) array_dsc <= '0; + else if (cnt[30:2] == 3) array_dsc <= '0; + else if (cnt[30:2] == 4) array_dsc <= '0; + else if (cnt[30:2] == 5) array_dsc <= '0; + else if (cnt[30:2] == 6) array_dsc <= '0; + else if (cnt[30:2] == 7) array_dsc <= '0; + else if (cnt[30:2] == 8) array_dsc <= '0; + else if (cnt[30:2] == 9) array_dsc <= '0; + end else if (cnt[1:0] == 2'd1) begin + // write value to array + if (cnt[30:2] == 0) begin end + else if (cnt[30:2] == 1) array_dsc <= {WA *WB +0{1'b1}}; + else if (cnt[30:2] == 2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2] == 3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2] == 4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2] == 5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2] == 6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2] == 7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2] == 8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2] == 9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; + end else if (cnt[1:0] == 2'd2) begin + // check array value + if (cnt[30:2] == 0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + end else if (cnt[1:0] == 2'd3) begin + // read value from array (not a very good test for now) + if (cnt[30:2] == 0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end + else if (cnt[30:2] == 1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2] == 7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2] == 8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end + end - // ascending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaaults (all bits to 0) - if (cnt[30:2]==0) array_asc <= '0; - else if (cnt[30:2]==1) array_asc <= '0; - else if (cnt[30:2]==2) array_asc <= '0; - else if (cnt[30:2]==3) array_asc <= '0; - else if (cnt[30:2]==4) array_asc <= '0; - else if (cnt[30:2]==5) array_asc <= '0; - else if (cnt[30:2]==6) array_asc <= '0; - else if (cnt[30:2]==7) array_asc <= '0; - else if (cnt[30:2]==8) array_asc <= '0; - else if (cnt[30:2]==9) array_asc <= '0; - end else if (cnt[1:0]==2'd1) begin - // write value to array - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) array_asc <= {WA *WB +0{1'b1}}; - else if (cnt[30:2]==2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==4) array_asc [0 ] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==5) array_asc [ WA -1] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}}; - else if (cnt[30:2]==9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; - end else if (cnt[1:0]==2'd2) begin - // check array value - if (cnt[30:2]==0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end - end else if (cnt[1:0]==2'd3) begin - // read value from array (not a very good test for now) - if (cnt[30:2]==0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end - else if (cnt[30:2]==1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end - else if (cnt[30:2]==9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end - end + // ascending range + always @ (posedge clk) + if (cnt[1:0] == 2'd0) begin + // initialize to defaaults (all bits to 0) + if (cnt[30:2] == 0) array_asc <= '0; + else if (cnt[30:2] == 1) array_asc <= '0; + else if (cnt[30:2] == 2) array_asc <= '0; + else if (cnt[30:2] == 3) array_asc <= '0; + else if (cnt[30:2] == 4) array_asc <= '0; + else if (cnt[30:2] == 5) array_asc <= '0; + else if (cnt[30:2] == 6) array_asc <= '0; + else if (cnt[30:2] == 7) array_asc <= '0; + else if (cnt[30:2] == 8) array_asc <= '0; + else if (cnt[30:2] == 9) array_asc <= '0; + end else if (cnt[1:0] == 2'd1) begin + // write value to array + if (cnt[30:2] == 0) begin end + else if (cnt[30:2] == 1) array_asc <= {WA *WB +0{1'b1}}; + else if (cnt[30:2] == 2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2] == 3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2] == 4) array_asc [0 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2] == 5) array_asc [ WA -1] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2] == 6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2] == 7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2] == 8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2] == 9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; + end else if (cnt[1:0] == 2'd2) begin + // check array value + if (cnt[30:2] == 0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end + end else if (cnt[1:0] == 2'd3) begin + // read value from array (not a very good test for now) + if (cnt[30:2] == 0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end + else if (cnt[30:2] == 1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2] == 7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2] == 8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end + end endmodule diff --git a/test_regress/t/t_array_pattern_2d.v b/test_regress/t/t_array_pattern_2d.v index 8df3b6fed..4e3934107 100644 --- a/test_regress/t/t_array_pattern_2d.v +++ b/test_regress/t/t_array_pattern_2d.v @@ -7,41 +7,41 @@ //bug991 module t; - logic [31:0] array_assign [3:0]; - logic [31:0] array_other [3:0]; + logic [31:0] array_assign[3:0]; + logic [31:0] array_other[3:0]; - logic [31:0] larray_assign [0:3]; - logic [31:0] larray_other [0:3]; + logic [31:0] larray_assign[0:3]; + logic [31:0] larray_other[0:3]; - logic [31:0] array_neg [-1:1]; + logic [31:0] array_neg[-1:1]; - initial begin - array_assign[0] = 32'd1; - array_assign[3:1] = '{32'd4, 32'd3, 32'd2}; + initial begin + array_assign[0] = 32'd1; + array_assign[3:1] = '{32'd4, 32'd3, 32'd2}; - array_other[0] = array_assign[0]+10; - array_other[3:1] = array_assign[3:1]; - if (array_other[0] != 11) $stop; - if (array_other[1] != 2) $stop; - if (array_other[2] != 3) $stop; - if (array_other[3] != 4) $stop; + array_other[0] = array_assign[0] + 10; + array_other[3:1] = array_assign[3:1]; + if (array_other[0] != 11) $stop; + if (array_other[1] != 2) $stop; + if (array_other[2] != 3) $stop; + if (array_other[3] != 4) $stop; - larray_assign[0] = 32'd1; - larray_assign[1:3] = '{32'd4, 32'd3, 32'd2}; + larray_assign[0] = 32'd1; + larray_assign[1:3] = '{32'd4, 32'd3, 32'd2}; - larray_other[0] = larray_assign[0]+10; - larray_other[1:3] = larray_assign[1:3]; - if (larray_other[0] != 11) $stop; - if (larray_other[1] != 4) $stop; - if (larray_other[2] != 3) $stop; - if (larray_other[3] != 2) $stop; + larray_other[0] = larray_assign[0] + 10; + larray_other[1:3] = larray_assign[1:3]; + if (larray_other[0] != 11) $stop; + if (larray_other[1] != 4) $stop; + if (larray_other[2] != 3) $stop; + if (larray_other[3] != 2) $stop; - array_neg = '{-1: 5, 1: 7, default: 'd6}; - if (array_neg[-1] != 5) $stop; - if (array_neg[0] != 6) $stop; - if (array_neg[1] != 7) $stop; + array_neg = '{-1: 5, 1: 7, default: 'd6}; + if (array_neg[-1] != 5) $stop; + if (array_neg[0] != 6) $stop; + if (array_neg[1] != 7) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_pattern_bad.out b/test_regress/t/t_array_pattern_bad.out index c93c13306..f27c98d53 100644 --- a/test_regress/t/t_array_pattern_bad.out +++ b/test_regress/t/t_array_pattern_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_array_pattern_bad.v:24:18: Assignment pattern key 'valids' not found as member +%Error: t/t_array_pattern_bad.v:21:39: Assignment pattern key 'valids' not found as member : ... note: In instance 't' - 24 | valids: '1}; - | ^~~~~~ + 21 | always_comb myinfo = '{default: '0, valids: '1}; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_array_pattern_bad.v b/test_regress/t/t_array_pattern_bad.v index c35f191b1..f6ac3b989 100644 --- a/test_regress/t/t_array_pattern_bad.v +++ b/test_regress/t/t_array_pattern_bad.v @@ -6,21 +6,18 @@ // bug1364 -module t (/*AUTOARG*/ - // Inputs - clk, res - ); - input clk; - input res; +module t ( /*AUTOARG*/ + // Inputs + clk, + res +); + input clk; + input res; - typedef struct packed { - logic [3:0] port_num; - } info_t; + typedef struct packed {logic [3:0] port_num;} info_t; - info_t myinfo; + info_t myinfo; - always_comb - myinfo = '{default: '0, - valids: '1}; + always_comb myinfo = '{default: '0, valids: '1}; endmodule diff --git a/test_regress/t/t_array_pattern_bad2.out b/test_regress/t/t_array_pattern_bad2.out index 5b81d55ec..f94cbf81a 100644 --- a/test_regress/t/t_array_pattern_bad2.out +++ b/test_regress/t/t_array_pattern_bad2.out @@ -1,6 +1,6 @@ -%Error: t/t_array_pattern_bad2.v:22:16: Multiple '{ default: } clauses +%Error: t/t_array_pattern_bad2.v:20:24: Multiple '{ default: } clauses : ... note: In instance 't' - 22 | myinfo = '{default: '0, - | ^~ + 20 | always_comb myinfo = '{default: '0, default: '1}; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_array_pattern_bad2.v b/test_regress/t/t_array_pattern_bad2.v index 4aa91b236..6ed67309e 100644 --- a/test_regress/t/t_array_pattern_bad2.v +++ b/test_regress/t/t_array_pattern_bad2.v @@ -6,20 +6,17 @@ // bug1364 -module t (/*AUTOARG*/ - // Inputs - clk, res - ); - input clk; - input res; +module t ( /*AUTOARG*/ + // Inputs + clk, + res +); + input clk; + input res; - typedef struct packed { - logic [3:0] port_num; - } info_t; + typedef struct packed {logic [3:0] port_num;} info_t; - info_t myinfo; - always_comb - myinfo = '{default: '0, - default: '1}; // Bad + info_t myinfo; + always_comb myinfo = '{default: '0, default: '1}; // Bad endmodule diff --git a/test_regress/t/t_array_pattern_bad3.out b/test_regress/t/t_array_pattern_bad3.out index 05fbe3d6a..2faded42e 100644 --- a/test_regress/t/t_array_pattern_bad3.out +++ b/test_regress/t/t_array_pattern_bad3.out @@ -1,14 +1,14 @@ -%Error: t/t_array_pattern_bad3.v:20:15: Assignment pattern key used multiple times: 1 - : ... note: In instance 't' - 20 | 1: '1}; - | ^ +%Error: t/t_array_pattern_bad3.v:19:9: Assignment pattern key used multiple times: 1 + : ... note: In instance 't' + 19 | 1: '1 + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_array_pattern_bad3.v:21:13: Assignment pattern with too many elements +%Error: t/t_array_pattern_bad3.v:21:11: Assignment pattern with too many elements : ... note: In instance 't' - 21 | arr = '{'0, '1, '0, '1}; - | ^~ -%Error: t/t_array_pattern_bad3.v:22:13: Assignment pattern missed initializing elements: 2 + 21 | arr = '{'0, '1, '0, '1}; + | ^~ +%Error: t/t_array_pattern_bad3.v:22:11: Assignment pattern missed initializing elements: 2 : ... note: In instance 't' - 22 | arr = '{'0, '1}; - | ^~ + 22 | arr = '{'0, '1}; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_array_pattern_bad3.v b/test_regress/t/t_array_pattern_bad3.v index 2e487c1e8..b8004a8d8 100644 --- a/test_regress/t/t_array_pattern_bad3.v +++ b/test_regress/t/t_array_pattern_bad3.v @@ -6,20 +6,20 @@ // bug1364 -module t (/*AUTOARG*/ - // Inputs - clk, res - ); - input clk; - input res; +module t ( + input clk, + input res +); - int arr[3]; - initial begin - arr = '{default: '0, - 1: '0, - 1: '1}; // Bad - arr = '{'0, '1, '0, '1}; // Bad, too many - arr = '{'0, '1}; // Bad, too few - end + int arr[3]; + initial begin + arr = '{ + default: '0, // + 1: '0, // + 1: '1 + }; // Bad + arr = '{'0, '1, '0, '1}; // Bad, too many + arr = '{'0, '1}; // Bad, too few + end endmodule diff --git a/test_regress/t/t_array_pattern_enum.v b/test_regress/t/t_array_pattern_enum.v index eeae8c36e..e09b9b686 100644 --- a/test_regress/t/t_array_pattern_enum.v +++ b/test_regress/t/t_array_pattern_enum.v @@ -5,28 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 package Pkg; - typedef enum { - RED=0, - GREEN=1, - BLUE=2 - } color_t; + typedef enum { + RED = 0, + GREEN = 1, + BLUE = 2 + } color_t; - typedef struct { - color_t pixels[32]; - } line_t; + typedef struct {color_t pixels[32];} line_t; - typedef struct { - line_t line[32]; - } screen_t; + typedef struct {line_t line[32];} screen_t; endpackage module t; - Pkg::screen_t screen; + Pkg::screen_t screen; - initial begin - screen = '{ default: '0, Pkg::color_t: Pkg::RED}; - $display("%p", screen); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + screen = '{default: '0, Pkg::color_t: Pkg::RED}; + $display("%p", screen); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_pattern_packed.v b/test_regress/t/t_array_pattern_packed.v index 45afbad31..cb5903594 100644 --- a/test_regress/t/t_array_pattern_packed.v +++ b/test_regress/t/t_array_pattern_packed.v @@ -4,150 +4,148 @@ // SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + logic [1:0][3:0][3:0] array_simp; // descending range array - logic [1:0] [3:0] [3:0] array_simp; // descending range array + logic [3:0] array_oned; - logic [3:0] array_oned; + // verilog_format: off + initial begin + array_oned = '{2:1'b1, 0:1'b1, default:1'b0}; + if (array_oned != 4'b0101) $stop; - initial begin - array_oned = '{2:1'b1, 0:1'b1, default:1'b0}; - if (array_oned != 4'b0101) $stop; + array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; + if (array_simp[0] !== 16'h3210) $stop; - array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; - if (array_simp[0] !== 16'h3210) $stop; + // verilator lint_off WIDTH + array_simp[0] = '{ 3 ,2 ,1, 0 }; + // verilator lint_on WIDTH + if (array_simp[0] !== 16'h3210) $stop; - // verilator lint_off WIDTH - array_simp[0] = '{ 3 ,2 ,1, 0 }; - // verilator lint_on WIDTH - if (array_simp[0] !== 16'h3210) $stop; + // Doesn't seem to work for unpacked arrays in other simulators + //if (array_simp[0] !== 16'h3210) $stop; + //array_simp[0] = '{ 1:4'd3, default:13}; + //if (array_simp[0] !== 16'hDD3D) $stop; - // Doesn't seem to work for unpacked arrays in other simulators - //if (array_simp[0] !== 16'h3210) $stop; - //array_simp[0] = '{ 1:4'd3, default:13}; - //if (array_simp[0] !== 16'hDD3D) $stop; + array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; + if (array_simp !== 32'h3210_1234) $stop; - array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; - if (array_simp !== 32'h3210_1234) $stop; + // IEEE says '{} allowed only on assignments, not !=, ==. - // IEEE says '{} allowed only on assignments, not !=, ==. + // Doesn't seem to work for unpacked arrays in other simulators + array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; + if (array_simp !== 32'h3210_3210) $stop; - // Doesn't seem to work for unpacked arrays in other simulators - array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; - if (array_simp !== 32'h3210_3210) $stop; + array_simp = '{2{ '{4{ 4'd3 }} }}; + if (array_simp !== 32'h3333_3333) $stop; - array_simp = '{2{ '{4{ 4'd3 }} }}; - if (array_simp !== 32'h3333_3333) $stop; + // Not legal in other simulators - replication doesn't match + // However IEEE suggests this is legal. + //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} - // Not legal in other simulators - replication doesn't match - // However IEEE suggests this is legal. - //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} + $write("*-* All Finished *-*\n"); + $finish; + end - $write("*-* All Finished *-*\n"); - $finish; - end + //==================== - //==================== + // parameters for array sizes + localparam WA = 4; // address dimension size + localparam WB = 4; // bit dimension size - // parameters for array sizes - localparam WA = 4; // address dimension size - localparam WB = 4; // bit dimension size + localparam NO = 11; // number of access events - localparam NO = 11; // number of access events + // 2D packed arrays + logic [WA-1:0] [WB-1:0] array_dsc; // descending range array + /* verilator lint_off ASCRANGE */ + logic [0:WA-1] [0:WB-1] array_asc; // ascending range array + /* verilator lint_on ASCRANGE */ - // 2D packed arrays - logic [WA-1:0] [WB-1:0] array_dsc; // descending range array - /* verilator lint_off ASCRANGE */ - logic [0:WA-1] [0:WB-1] array_asc; // ascending range array - /* verilator lint_on ASCRANGE */ + integer cnt = 0; - integer cnt = 0; + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end - // event counter - always @ (posedge clk) begin - cnt <= cnt + 1; - end + // finish report + always @ (posedge clk) + if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin + $write("*-* All Finished *-*\n"); + $finish; + end - // finish report - always @ (posedge clk) - if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // descending range + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'b0) + if (cnt[30:2]== 0) array_dsc <= '0; + else if (cnt[30:2]== 1) array_dsc <= '0; + else if (cnt[30:2]== 2) array_dsc <= '0; + else if (cnt[30:2]== 3) array_dsc <= '0; + else if (cnt[30:2]== 4) array_dsc <= '0; + else if (cnt[30:2]== 5) array_dsc <= '0; + else if (cnt[30:2]== 6) array_dsc <= '0; + else if (cnt[30:2]== 7) array_dsc <= '0; + else if (cnt[30:2]== 8) array_dsc <= '0; + else if (cnt[30:2]== 9) array_dsc <= '0; + else if (cnt[30:2]==10) array_dsc <= '0; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]== 0) begin end + else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]== 2) array_dsc <= '{default:13}; + else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7}; + else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13}; + else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end + end - // descending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaults (all bits 1'b0) - if (cnt[30:2]== 0) array_dsc <= '0; - else if (cnt[30:2]== 1) array_dsc <= '0; - else if (cnt[30:2]== 2) array_dsc <= '0; - else if (cnt[30:2]== 3) array_dsc <= '0; - else if (cnt[30:2]== 4) array_dsc <= '0; - else if (cnt[30:2]== 5) array_dsc <= '0; - else if (cnt[30:2]== 6) array_dsc <= '0; - else if (cnt[30:2]== 7) array_dsc <= '0; - else if (cnt[30:2]== 8) array_dsc <= '0; - else if (cnt[30:2]== 9) array_dsc <= '0; - else if (cnt[30:2]==10) array_dsc <= '0; - end else if (cnt[1:0]==2'd1) begin - // write data into whole or part of the array using literals - if (cnt[30:2]== 0) begin end - else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 }; - else if (cnt[30:2]== 2) array_dsc <= '{default:13}; - else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7}; - else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13}; - else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }}; - else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; - end else if (cnt[1:0]==2'd2) begin - // chack array agains expected value - if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end - end - - // ascending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaults (all bits 1'b0) - if (cnt[30:2]== 0) array_asc <= '0; - else if (cnt[30:2]== 1) array_asc <= '0; - else if (cnt[30:2]== 2) array_asc <= '0; - else if (cnt[30:2]== 3) array_asc <= '0; - else if (cnt[30:2]== 4) array_asc <= '0; - else if (cnt[30:2]== 5) array_asc <= '0; - else if (cnt[30:2]== 6) array_asc <= '0; - else if (cnt[30:2]== 7) array_asc <= '0; - else if (cnt[30:2]== 8) array_asc <= '0; - else if (cnt[30:2]== 9) array_asc <= '0; - else if (cnt[30:2]==10) array_asc <= '0; - end else if (cnt[1:0]==2'd1) begin - // write data into whole or part of the array using literals - if (cnt[30:2]== 0) begin end - else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 }; - else if (cnt[30:2]== 2) array_asc <= '{default:13}; - else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7}; - else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13}; - else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }}; - else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; - end else if (cnt[1:0]==2'd2) begin - // chack array agains expected value - if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end - end + // ascending range + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'b0) + if (cnt[30:2]== 0) array_asc <= '0; + else if (cnt[30:2]== 1) array_asc <= '0; + else if (cnt[30:2]== 2) array_asc <= '0; + else if (cnt[30:2]== 3) array_asc <= '0; + else if (cnt[30:2]== 4) array_asc <= '0; + else if (cnt[30:2]== 5) array_asc <= '0; + else if (cnt[30:2]== 6) array_asc <= '0; + else if (cnt[30:2]== 7) array_asc <= '0; + else if (cnt[30:2]== 8) array_asc <= '0; + else if (cnt[30:2]== 9) array_asc <= '0; + else if (cnt[30:2]==10) array_asc <= '0; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]== 0) begin end + else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]== 2) array_asc <= '{default:13}; + else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7}; + else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13}; + else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end + end endmodule diff --git a/test_regress/t/t_array_pattern_unpacked.v b/test_regress/t/t_array_pattern_unpacked.v index 601d85db2..0e1c8f1b6 100644 --- a/test_regress/t/t_array_pattern_unpacked.v +++ b/test_regress/t/t_array_pattern_unpacked.v @@ -6,58 +6,58 @@ module t; - logic [3:0] array_simp [1:0] [3:0]; // descending range array - wire [2:0] array_wire [1:0] = '{3'd1, 3'd2}; + logic [3:0] array_simp [1:0] [3:0]; // descending range array + wire [2:0] array_wire [1:0] = '{3'd1, 3'd2}; - int irep[1:2][1:6]; + int irep[1:2][1:6]; - initial begin - if (array_wire[0] !== 3'd2) $stop; - if (array_wire[1] !== 3'd1) $stop; + initial begin + if (array_wire[0] !== 3'd2) $stop; + if (array_wire[1] !== 3'd1) $stop; - array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; - if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} - !== 16'h3210) $stop; + array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; + if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} + !== 16'h3210) $stop; - // verilator lint_off WIDTH - array_simp[0] = '{ 3 ,2 ,1, 0 }; - // verilator lint_on WIDTH - if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} - !== 16'h3210) $stop; + // verilator lint_off WIDTH + array_simp[0] = '{ 3 ,2 ,1, 0 }; + // verilator lint_on WIDTH + if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} + !== 16'h3210) $stop; - // Doesn't seem to work for unpacked arrays in other simulators - //array_simp[0] = '{ 1:4'd3, default:13 }; - //if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop; + // Doesn't seem to work for unpacked arrays in other simulators + //array_simp[0] = '{ 1:4'd3, default:13 }; + //if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop; - array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; - if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], - array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} - !== 32'h3210_1234) $stop; + array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; + if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], + array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} + !== 32'h3210_1234) $stop; - // Doesn't seem to work for unpacked arrays in other simulators - array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; - if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], - array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} - !== 32'h3210_3210) $stop; + // Doesn't seem to work for unpacked arrays in other simulators + array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; + if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], + array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} + !== 32'h3210_3210) $stop; - array_simp = '{2{ '{4{ 4'd3 }} }}; - if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], - array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} - !== 32'h3333_3333) $stop; + array_simp = '{2{ '{4{ 4'd3 }} }}; + if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], + array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} + !== 32'h3333_3333) $stop; - // Not legal in other simulators - replication doesn't match - // However IEEE suggests this is legal. - //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} + // Not legal in other simulators - replication doesn't match + // However IEEE suggests this is legal. + //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} - // Replication - irep = '{2{ '{3 {4, 5}}}}; - if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]} - != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; - if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]} - != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; + // Replication + irep = '{2{ '{3 {4, 5}}}}; + if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]} + != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; + if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]} + != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_query.v b/test_regress/t/t_array_query.v index 0585a59ff..db0873bec 100644 --- a/test_regress/t/t_array_query.v +++ b/test_regress/t/t_array_query.v @@ -7,60 +7,56 @@ // SPDX-FileCopyrightText: 2012 Jeremy Bennett, Embecosm // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - wire a = clk; - wire b = 1'b0; - reg c; + wire a = clk; + wire b = 1'b0; + reg c; - array_test array_test_i (/*AUTOINST*/ - // Inputs - .clk (clk)); + array_test array_test_i ( /*AUTOINST*/ + // Inputs + .clk(clk) + ); endmodule // Check the array sizing functions work correctly. -module array_test +module array_test #( + parameter LEFT = 5, + RIGHT = 55 +) ( /*AUTOARG*/ + // Inputs + clk +); - #( parameter - LEFT = 5, - RIGHT = 55) + input clk; - (/*AUTOARG*/ - // Inputs - clk - ); + // verilator lint_off ASCRANGE + reg [7:0] a[LEFT:RIGHT]; + // verilator lint_on ASCRANGE - input clk; + typedef reg [7:0] r_t; - // verilator lint_off ASCRANGE - reg [7:0] a [LEFT:RIGHT]; - // verilator lint_on ASCRANGE + integer l; + integer r; + integer s; - typedef reg [7:0] r_t; - - integer l; - integer r; - integer s; - - always @(posedge clk) begin - l = $left (a); - r = $right (a); - s = $size (a); + always @(posedge clk) begin + l = $left(a); + r = $right(a); + s = $size(a); `ifdef TEST_VERBOSE - $write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s); + $write("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s); `endif - if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop; - if ($left(r_t)!=7 || $right(r_t)!=0 || $size(r_t)!=8 || $bits(r_t) !=8) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop; + if ($left(r_t) != 7 || $right(r_t) != 0 || $size(r_t) != 8 || $bits(r_t) != 8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_query_with.v b/test_regress/t/t_array_query_with.v index eec4685b0..1e5c4bc9f 100644 --- a/test_regress/t/t_array_query_with.v +++ b/test_regress/t/t_array_query_with.v @@ -5,70 +5,70 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - static function bit get_true(); - return 1'b1; - endfunction + static function bit get_true(); + return 1'b1; + endfunction - static function bit test_find_index_in_class(); - if (get_true) begin - int q[$] = {0, -1, 3, 1, 4, 1}; - int found_idx[$]; - found_idx = q.find_index(node) with (node == 1); - return found_idx[0] == 3; - end - return 0; - endfunction + static function bit test_find_index_in_class(); + if (get_true) begin + int q[$] = {0, -1, 3, 1, 4, 1}; + int found_idx[$]; + found_idx = q.find_index(node) with (node == 1); + return found_idx[0] == 3; + end + return 0; + endfunction endclass -module t (/*AUTOARG*/ - ); +module t ( /*AUTOARG*/ +); - function bit test_find; - string bar[$]; - string found[$]; - bar.push_back("baz"); - bar.push_back("qux"); - found = bar.find(x) with (x == "baz"); - return found.size() == 1; - endfunction + function bit test_find; + string bar[$]; + string found[$]; + bar.push_back("baz"); + bar.push_back("qux"); + found = bar.find(x) with (x == "baz"); + return found.size() == 1; + endfunction - function static bit test_find_index; - int q[$] = {1, 2, 3, 4}; - int found[$] = q.find_index(x) with (x <= 2); - return found.size() == 2; - endfunction + function static bit test_find_index; + int q[$] = {1, 2, 3, 4}; + int found[$] = q.find_index(x) with (x <= 2); + return found.size() == 2; + endfunction - function static bit test_find_first_index; - int q[] = {1, 2, 3, 4, 5, 6}; - int first_even_idx[$] = q.find_first_index(x) with (x % 2 == 0); - return first_even_idx[0] == 1; - endfunction + function static bit test_find_first_index; + int q[] = {1, 2, 3, 4, 5, 6}; + int first_even_idx[$] = q.find_first_index(x) with (x % 2 == 0); + return first_even_idx[0] == 1; + endfunction - function bit is_even(int a); - return a % 2 == 0; - endfunction + function bit is_even(int a); + return a % 2 == 0; + endfunction - function static bit test_find_first_index_by_func; - int q[] = {1, 2, 3, 4, 5, 6}; - int first_even_idx[$] = q.find_first_index(x) with (is_even(x)); - return first_even_idx[0] == 1; - endfunction + function static bit test_find_first_index_by_func; + int q[] = {1, 2, 3, 4, 5, 6}; + int first_even_idx[$] = q.find_first_index(x) with (is_even(x)); + return first_even_idx[0] == 1; + endfunction - function automatic bit test_sort; - int q[] = {-5, 2, -3, 0, 4}; - q.sort(x) with (x >= 0 ? x : -x); - return q[1] == 2; - endfunction + function automatic bit test_sort; + int q[] = {-5, 2, -3, 0, 4}; + q.sort(x) with (x >= 0 ? x : -x); + return q[1] == 2; + endfunction - initial begin - if (!test_find()) $stop; - if (!test_find_index()) $stop; - if (!test_find_first_index()) $stop; - if (!test_find_first_index_by_func()) $stop; - if (!test_sort()) $stop; - if (!Cls::test_find_index_in_class()) $stop; + initial begin + if (!test_find()) $stop; + if (!test_find_index()) $stop; + if (!test_find_first_index()) $stop; + if (!test_find_first_index_by_func()) $stop; + if (!test_sort()) $stop; + if (!Cls::test_find_index_in_class()) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_rev.v b/test_regress/t/t_array_rev.v index c8c63c58f..f77fba0c6 100644 --- a/test_regress/t/t_array_rev.v +++ b/test_regress/t/t_array_rev.v @@ -4,58 +4,54 @@ // SPDX-FileCopyrightText: 2016 Geoff Barrett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc = 0; + // verilator lint_off ASCRANGE + logic arrd[0:1] = '{1'b1, 1'b0}; + // verilator lint_on ASCRANGE + logic y0, y1; + logic localbkw[1:0]; - integer cyc = 0; - // verilator lint_off ASCRANGE - logic arrd [0:1] = '{ 1'b1, 1'b0 }; - // verilator lint_on ASCRANGE - logic y0, y1; - logic localbkw [1:0]; + arr_rev arr_rev_u ( + .arrbkw(arrd), + .y0(y0), + .y1(y1) + ); - arr_rev arr_rev_u ( - .arrbkw (arrd), - .y0(y0), - .y1(y1) - ); + always @(posedge clk) begin + if (arrd[0] != 1'b1) $stop; + if (arrd[1] != 1'b0) $stop; - always @ (posedge clk) begin - if (arrd[0] != 1'b1) $stop; - if (arrd[1] != 1'b0) $stop; - - localbkw = arrd; + localbkw = arrd; `ifdef TEST_VERBOSE - $write("localbkw[0]=%b\n", localbkw[0]); - $write("localbkw[1]=%b\n", localbkw[1]); + $write("localbkw[0]=%b\n", localbkw[0]); + $write("localbkw[1]=%b\n", localbkw[1]); `endif - if (localbkw[0] != 1'b0) $stop; - if (localbkw[1] != 1'b1) $stop; + if (localbkw[0] != 1'b0) $stop; + if (localbkw[1] != 1'b1) $stop; `ifdef TEST_VERBOSE - $write("y0=%b\n", y0); - $write("y1=%b\n", y1); + $write("y0=%b\n", y0); + $write("y1=%b\n", y1); `endif - if (y0 != 1'b0) $stop; - if (y1 != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (y0 != 1'b0) $stop; + if (y1 != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module arr_rev - ( - input var logic arrbkw [1:0], - output var logic y0, - output var logic y1 - ); +module arr_rev ( + input var logic arrbkw[1:0], + output var logic y0, + output var logic y1 +); - always_comb y0 = arrbkw[0]; - always_comb y1 = arrbkw[1]; + always_comb y0 = arrbkw[0]; + always_comb y1 = arrbkw[1]; endmodule diff --git a/test_regress/t/t_array_sel_wide.v b/test_regress/t/t_array_sel_wide.v index 24601b694..5964e0109 100644 --- a/test_regress/t/t_array_sel_wide.v +++ b/test_regress/t/t_array_sel_wide.v @@ -5,26 +5,26 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - nnext, - // Inputs - inibble, onibble - ); + // Outputs + nnext, + // Inputs + inibble, onibble + ); - input [3:0] inibble; - input [106:0] onibble; + input [3:0] inibble; + input [106:0] onibble; - output reg [3:0] nnext [0:7]; + output reg [3:0] nnext [0:7]; - // verilator lint_off WIDTH - wire [2:0] selline = (onibble >>> 102) & 7; - // verilator lint_on WIDTH + // verilator lint_off WIDTH + wire [2:0] selline = (onibble >>> 102) & 7; + // verilator lint_on WIDTH - always_comb begin - for (integer i=0; i<8; i=i+1) begin - nnext[i] = '0; - end - nnext[selline] = inibble; - end + always_comb begin + for (integer i=0; i<8; i=i+1) begin + nnext[i] = '0; + end + nnext[selline] = inibble; + end endmodule diff --git a/test_regress/t/t_array_type_methods.v b/test_regress/t/t_array_type_methods.v index 7b3c71110..ad2c7d2c2 100644 --- a/test_regress/t/t_array_type_methods.v +++ b/test_regress/t/t_array_type_methods.v @@ -4,30 +4,32 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - logic [3:0] foo [1:0]; - logic [3:0] fooe [1:0]; - initial begin - foo[0] = 4'b0101; - foo[1] = 4'b0011; + logic [3:0] foo[1:0]; + logic [3:0] fooe[1:0]; + initial begin + foo[0] = 4'b0101; + foo[1] = 4'b0011; - `checkh(foo.or, 4'b0111); - `checkh(foo.and, 4'b0001); - `checkh(foo.xor, 4'b0110); - `checkh(foo.sum, 4'b1000); - `checkh(foo.product, 4'b1111); + `checkh(foo.or, 4'b0111); + `checkh(foo.and, 4'b0001); + `checkh(foo.xor, 4'b0110); + `checkh(foo.sum, 4'b1000); + `checkh(foo.product, 4'b1111); - fooe[0] = 4'b0101; - fooe[1] = 4'b0011; - if (foo != fooe) $stop; + fooe[0] = 4'b0101; + fooe[1] = 4'b0011; + if (foo != fooe) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_unpacked_public.v b/test_regress/t/t_array_unpacked_public.v index b74d6de54..a16595f07 100644 --- a/test_regress/t/t_array_unpacked_public.v +++ b/test_regress/t/t_array_unpacked_public.v @@ -4,10 +4,10 @@ // SPDX-FileCopyrightText: 2020 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 -module t(); - logic din [0:15]; +module t; + logic din[0:15]; - array_test array_test_inst(.din(din)); + array_test array_test_inst (.din(din)); initial begin $write("*-* All Finished *-*\n"); @@ -15,7 +15,7 @@ module t(); end endmodule -module array_test( - input din [0:15] +module array_test ( + input din[0:15] ); endmodule diff --git a/test_regress/t/t_assert_always_unsup.out b/test_regress/t/t_assert_always_unsup.out index f33c70fe2..7bbe0404c 100644 --- a/test_regress/t/t_assert_always_unsup.out +++ b/test_regress/t/t_assert_always_unsup.out @@ -1,16 +1,16 @@ -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:21:7: Unsupported: always[] (in property expression) - 21 | always [2:5] a; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_assert_always_unsup.v:20:5: Unsupported: always[] (in property expression) + 20 | always [2:5] a; + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:25:7: Unsupported: s_always (in property expression) - 25 | s_always [2:5] a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:29:7: Unsupported: eventually[] (in property expression) - 29 | eventually [2:5] a; - | ^~~~~~~~~~ -%Error: t/t_assert_always_unsup.v:33:20: syntax error, unexpected ']', expecting ':' - 33 | eventually [2] a; - | ^ +%Error-UNSUPPORTED: t/t_assert_always_unsup.v:24:5: Unsupported: s_always (in property expression) + 24 | s_always [2:5] a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_always_unsup.v:28:5: Unsupported: eventually[] (in property expression) + 28 | eventually [2:5] a; + | ^~~~~~~~~~ +%Error: t/t_assert_always_unsup.v:32:18: syntax error, unexpected ']', expecting ':' + 32 | eventually [2] a; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_assert_always_unsup.v b/test_regress/t/t_assert_always_unsup.v index 3165d4420..332064fee 100644 --- a/test_regress/t/t_assert_always_unsup.v +++ b/test_regress/t/t_assert_always_unsup.v @@ -4,45 +4,44 @@ // SPDX-FileCopyrightText: 2022-2025 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic val = 0; + int cyc = 0; + logic val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - property p_alw; - always [2:5] a; - endproperty + property p_alw; + always [2:5] a; + endproperty - property p_s_alw; - s_always [2:5] a; - endproperty + property p_s_alw; + s_always [2:5] a; + endproperty - property p_ev; - eventually [2:5] a; - endproperty + property p_ev; + eventually [2:5] a; + endproperty - property p_evc; - eventually [2] a; - endproperty + property p_evc; + eventually [2] a; + endproperty - property p_s_ev; - s_eventually [2:5] a; - endproperty + property p_s_ev; + s_eventually [2:5] a; + endproperty - property p_s_alw_ev; - always s_eventually [2:5] a; - endproperty + property p_s_alw_ev; + always s_eventually [2:5] a; + endproperty - property p_s_ev_alw; - s_eventually always [2:5] a; - endproperty + property p_s_ev_alw; + s_eventually always [2:5] a; + endproperty endmodule diff --git a/test_regress/t/t_assert_basic.v b/test_regress/t/t_assert_basic.v index 768a9f823..7d96ac19c 100644 --- a/test_regress/t/t_assert_basic.v +++ b/test_regress/t/t_assert_basic.v @@ -4,50 +4,62 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg toggle; - reg toggle; + integer cyc; + initial cyc = 1; + wire [7:0] cyc_copy = cyc[7:0]; - integer cyc; initial cyc=1; - wire [7:0] cyc_copy = cyc[7:0]; + always @(negedge clk) begin + AssertionFalse1 : assert (cyc < 100); + assert (!(cyc == 5) || toggle); + // FIX cover {cyc==3 || cyc==4}; + // FIX cover {cyc==9} report "DefaultClock,expect=1"; + // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; + end - always @ (negedge clk) begin - AssertionFalse1: assert (cyc<100); - assert (!(cyc==5) || toggle); - // FIX cover {cyc==3 || cyc==4}; - // FIX cover {cyc==9} report "DefaultClock,expect=1"; - // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; - end - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - toggle <= !cyc[0]; - if (cyc==7) assert (cyc[0] == cyc[1]); // bug743 - if (cyc==9) begin + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc == 7) assert (cyc[0] == cyc[1]); // bug743 + if (cyc == 9) begin `ifdef FAILING_ASSERTIONS - assert (0) else $info; - assert (0) else $info("Info message"); - assume (0) else $info("Info message from failing assumption"); - assert (0) else $info("Info message, cyc=%d", cyc); - InWarningBlock: assert (0) else $warning; - InWarningMBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); - InErrorBlock: assert (0) else $error; - InErrorMBlock: assert (0) else $error("Error...."); - assert (0) else $fatal(1, "Fatal...."); - assert (0) else $fatal; + assert (0) + else $info; + assert (0) + else $info("Info message"); + assume (0) + else $info("Info message from failing assumption"); + assert (0) + else $info("Info message, cyc=%d", cyc); + InWarningBlock : + assert (0) + else $warning; + InWarningMBlock : + assert (0) + else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); + InErrorBlock : + assert (0) + else $error; + InErrorMBlock : + assert (0) + else $error("Error...."); + assert (0) + else $fatal(1, "Fatal...."); + assert (0) + else $fatal; `endif - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end end - end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_assert_casez.v b/test_regress/t/t_assert_casez.v index a906454de..4b1c4b336 100644 --- a/test_regress/t/t_assert_casez.v +++ b/test_regress/t/t_assert_casez.v @@ -6,25 +6,25 @@ module t; - reg [1:0] value; + reg [1:0] value; - initial begin - value = 2'b00; - unique casez (value) - 2'b00 : ; - 2'b01 : ; - 2'b1? : ; - endcase - value = 2'b11; - unique casez (value) - 2'b00 : ; - 2'b01 : ; - 2'b1? : ; - endcase - unique casez (1'b1) - default: ; - endcase - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + value = 2'b00; + unique casez (value) + 2'b00: ; + 2'b01: ; + 2'b1?: ; + endcase + value = 2'b11; + unique casez (value) + 2'b00: ; + 2'b01: ; + 2'b1?: ; + endcase + unique casez (1'b1) + default: ; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_clock_event_unsup.out b/test_regress/t/t_assert_clock_event_unsup.out index 56484ebb6..c1afa7434 100644 --- a/test_regress/t/t_assert_clock_event_unsup.out +++ b/test_regress/t/t_assert_clock_event_unsup.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_assert_clock_event_unsup.v:26:7: Unsupported: Clock event before property call and in its body - 26 | @(negedge clk) - | ^ +%Error-UNSUPPORTED: t/t_assert_clock_event_unsup.v:24:5: Unsupported: Clock event before property call and in its body + 24 | @(negedge clk) check( + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assert_clock_event_unsup.v b/test_regress/t/t_assert_clock_event_unsup.v index eaac7d402..db7323c78 100644 --- a/test_regress/t/t_assert_clock_event_unsup.v +++ b/test_regress/t/t_assert_clock_event_unsup.v @@ -4,34 +4,33 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic val = 0; + int cyc = 0; + logic val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - property check(int cyc_mod_2, logic expected); - @(posedge clk) - cyc % 2 == cyc_mod_2 |=> val == expected; - endproperty + property check(int cyc_mod_2, logic expected); + @(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected; + endproperty - property check_if_1(int cyc_mod_2); - @(negedge clk) - check(cyc_mod_2, 1); - endproperty + property check_if_1(int cyc_mod_2); + @(negedge clk) check( + cyc_mod_2, 1 + ); + endproperty - assert property(check_if_1(1)) - else begin - // Assertion should fail - $write("*-* All Finished *-*\n"); - $finish; - end + assert property (check_if_1(1)) + else begin + // Assertion should fail + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_comp.v b/test_regress/t/t_assert_comp.v index 970ac4b1a..ff8797118 100644 --- a/test_regress/t/t_assert_comp.v +++ b/test_regress/t/t_assert_comp.v @@ -6,28 +6,28 @@ module t; - localparam TEN = 10; - localparam string PCTPCT = "%%"; + localparam TEN = 10; + localparam string PCTPCT = "%%"; - if (0) begin - $info; - $info("User elaboration-time info"); - $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); - $warning; - $warning("User elaboration-time warning"); - $warning(1); // Check can convert arguments to format - $error("User elaboration-time error"); - end + if (0) begin + $info; + $info("User elaboration-time info"); + $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); + $warning; + $warning("User elaboration-time warning"); + $warning(1); // Check can convert arguments to format + $error("User elaboration-time error"); + end - initial begin - $info; - $info("User run-time info"); - $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); - $warning; - $warning("User run-time warning"); - $warning(1); // Check can convert arguments to format + initial begin + $info; + $info("User run-time info"); + $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); + $warning; + $warning("User run-time warning"); + $warning(1); // Check can convert arguments to format - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_cover.v b/test_regress/t/t_assert_cover.v index 1fc90b039..0844864b8 100644 --- a/test_regress/t/t_assert_cover.v +++ b/test_regress/t/t_assert_cover.v @@ -4,156 +4,154 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg toggle; - integer cyc; initial cyc=1; + reg toggle; + integer cyc; initial cyc=1; - Test test (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle), - .cyc (cyc[31:0])); + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); - Sub sub1 (.*); - Sub sub2 (.*); + Sub sub1 (.*); + Sub sub2 (.*); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - toggle <= !cyc[0]; - if (cyc==9) begin - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc==9) begin end - end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module Test ( - input clk, - input toggle, - input [31:0] cyc - ); + input clk, + input toggle, + input [31:0] cyc + ); - // Simple cover - cover property (@(posedge clk) cyc==3); + // Simple cover + cover property (@(posedge clk) cyc==3); - // With statement, in generate - generate if (1) begin - cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4"); - end - endgenerate + // With statement, in generate + generate if (1) begin + cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4"); + end + endgenerate - // Labeled cover - cyc_eq_5: - cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); + // Labeled cover + cyc_eq_5: + cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); - // Using default clock - default clocking @(posedge clk); endclocking - cover property (cyc==6) $display("*COVER: Cyc==6"); + // Using default clock + default clocking @(posedge clk); endclocking + cover property (cyc==6) $display("*COVER: Cyc==6"); - // Disable statement - // Note () after disable are required - cover property (@(posedge clk) disable iff (toggle) cyc==8) - $display("*COVER: Cyc==8"); - cover property (@(posedge clk) disable iff (!toggle) cyc==8) - $stop; + // Disable statement + // Note () after disable are required + cover property (@(posedge clk) disable iff (toggle) cyc==8) + $display("*COVER: Cyc==8"); + cover property (@(posedge clk) disable iff (!toggle) cyc==8) + $stop; - always_ff @ (posedge clk) begin - labeled_icov: cover (cyc==3 || cyc==4); - end + always_ff @ (posedge clk) begin + labeled_icov: cover (cyc==3 || cyc==4); + end - // Immediate cover - labeled_imm0: cover #0 (cyc == 0); - labeled_immf: cover final (cyc == 0); + // Immediate cover + labeled_imm0: cover #0 (cyc == 0); + labeled_immf: cover final (cyc == 0); - // Immediate assert - labeled_imas: assert #0 (1); - assert final (1); + // Immediate assert + labeled_imas: assert #0 (1); + assert final (1); - //============================================================ - // Using a macro and generate - wire reset = (cyc < 2); + //============================================================ + // Using a macro and generate + wire reset = (cyc < 2); `define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn)) - genvar i; - generate - for (i=0; i<32; i=i+1) - begin: cycval - CycCover_i: `covclk( cyc[i] ); - end - endgenerate + genvar i; + generate + for (i=0; i<32; i=i+1) + begin: cycval + CycCover_i: `covclk( cyc[i] ); + end + endgenerate - //============================================================ - // Using a more complicated property - property C1; - @(posedge clk) - disable iff (!toggle) - cyc==5; - endproperty - cover property (C1) $display("*COVER: Cyc==5"); + //============================================================ + // Using a more complicated property + property C1; + @(posedge clk) + disable iff (!toggle) + cyc==5; + endproperty + cover property (C1) $display("*COVER: Cyc==5"); `ifndef verilator // Unsupported - //============================================================ - // Using covergroup - // Note a covergroup is really inheritance of a special system "covergroup" class. - covergroup counter1 @ (posedge cyc); - // Automatic methods: stop(), start(), sample(), set_inst_name() + //============================================================ + // Using covergroup + // Note a covergroup is really inheritance of a special system "covergroup" class. + covergroup counter1 @ (posedge cyc); + // Automatic methods: stop(), start(), sample(), set_inst_name() - // Each bin value must be <= 32 bits. Strange. - cyc_value : coverpoint cyc { - } - - cyc_bined : coverpoint cyc { - bins zero = {0}; - bins low = {1,5}; - // Note 5 is also in the bin above. Only the first bin matching is counted. - bins mid = {[5:$]}; - // illegal_bins // Has precidence over "first matching bin", creates assertion - // ignore_bins // Not counted, and not part of total - } - toggle : coverpoint (toggle) { - bins off = {0}; - bins on = {1}; - } - cyc5 : coverpoint (cyc==5) { - bins five = {1}; + // Each bin value must be <= 32 bits. Strange. + cyc_value : coverpoint cyc { } - // option.at_least = {number}; // Default 1 - Hits to be considered covered - // option.auto_bin_max = {number}; // Default 64 - // option.comment = {string}; // Default "" - // option.goal = {number}; // Default 90% - // option.name = {string}; // Default "" - // option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1) - // option.weight = {number}; // Default 1 + cyc_bined : coverpoint cyc { + bins zero = {0}; + bins low = {1,5}; + // Note 5 is also in the bin above. Only the first bin matching is counted. + bins mid = {[5:$]}; + // illegal_bins // Has precidence over "first matching bin", creates assertion + // ignore_bins // Not counted, and not part of total + } + toggle : coverpoint (toggle) { + bins off = {0}; + bins on = {1}; + } + cyc5 : coverpoint (cyc==5) { + bins five = {1}; + } - // CROSS - value_and_toggle: // else default is ___X__ - cross cyc_value, toggle; - endgroup - counter1 c1 = new(); + // option.at_least = {number}; // Default 1 - Hits to be considered covered + // option.auto_bin_max = {number}; // Default 64 + // option.comment = {string}; // Default "" + // option.goal = {number}; // Default 90% + // option.name = {string}; // Default "" + // option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1) + // option.weight = {number}; // Default 1 + + // CROSS + value_and_toggle: // else default is ___X__ + cross cyc_value, toggle; + endgroup + counter1 c1 = new(); `endif endmodule module Sub ( - input clk, - input integer cyc - ); + input clk, + input integer cyc + ); - // Simple cover, per-instance - pi_sub: - cover property (@(posedge clk) cyc == 3); + // Simple cover, per-instance + pi_sub: + cover property (@(posedge clk) cyc == 3); endmodule diff --git a/test_regress/t/t_assert_ctl_arg.dat.out b/test_regress/t/t_assert_ctl_arg.dat.out index a19ca52fa..b83831847 100644 --- a/test_regress/t/t_assert_ctl_arg.dat.out +++ b/test_regress/t/t_assert_ctl_arg.dat.out @@ -1,153 +1,153 @@ # SystemC::Coverage-3 -C 'ft/t_assert_ctl_arg.vl100n32tuserpagev_user/tocover_simple_immediate_100htop.t.cover_simple_immediate_100' 1 -C 'ft/t_assert_ctl_arg.vl100n37tuserpagev_user/tocover_simple_immediate_stmt_100htop.t.cover_simple_immediate_stmt_100' 1 -C 'ft/t_assert_ctl_arg.vl100n40tuserpagev_user/tocover_final_deferred_immediate_100htop.t.cover_final_deferred_immediate_100' 1 -C 'ft/t_assert_ctl_arg.vl100n43tuserpagev_user/tocover_observed_deferred_immediate_100htop.t.cover_observed_deferred_immediate_100' 1 -C 'ft/t_assert_ctl_arg.vl100n45tuserpagev_user/tocover_final_deferred_immediate_stmt_100htop.t.cover_final_deferred_immediate_stmt_100' 1 -C 'ft/t_assert_ctl_arg.vl100n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_100htop.t.cover_observed_deferred_immediate_stmt_100' 1 -C 'ft/t_assert_ctl_arg.vl103n32tuserpagev_user/tocover_simple_immediate_103htop.t.cover_simple_immediate_103' 0 -C 'ft/t_assert_ctl_arg.vl103n37tuserpagev_user/tocover_simple_immediate_stmt_103htop.t.cover_simple_immediate_stmt_103' 0 -C 'ft/t_assert_ctl_arg.vl103n40tuserpagev_user/tocover_final_deferred_immediate_103htop.t.cover_final_deferred_immediate_103' 0 -C 'ft/t_assert_ctl_arg.vl103n43tuserpagev_user/tocover_observed_deferred_immediate_103htop.t.cover_observed_deferred_immediate_103' 0 -C 'ft/t_assert_ctl_arg.vl103n45tuserpagev_user/tocover_final_deferred_immediate_stmt_103htop.t.cover_final_deferred_immediate_stmt_103' 0 -C 'ft/t_assert_ctl_arg.vl103n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_103htop.t.cover_observed_deferred_immediate_stmt_103' 0 -C 'ft/t_assert_ctl_arg.vl106n32tuserpagev_user/tocover_simple_immediate_106htop.t.cover_simple_immediate_106' 1 -C 'ft/t_assert_ctl_arg.vl106n37tuserpagev_user/tocover_simple_immediate_stmt_106htop.t.cover_simple_immediate_stmt_106' 1 -C 'ft/t_assert_ctl_arg.vl106n40tuserpagev_user/tocover_final_deferred_immediate_106htop.t.cover_final_deferred_immediate_106' 1 -C 'ft/t_assert_ctl_arg.vl106n43tuserpagev_user/tocover_observed_deferred_immediate_106htop.t.cover_observed_deferred_immediate_106' 1 -C 'ft/t_assert_ctl_arg.vl106n45tuserpagev_user/tocover_final_deferred_immediate_stmt_106htop.t.cover_final_deferred_immediate_stmt_106' 1 -C 'ft/t_assert_ctl_arg.vl106n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_106htop.t.cover_observed_deferred_immediate_stmt_106' 1 -C 'ft/t_assert_ctl_arg.vl108n32tuserpagev_user/tocover_simple_immediate_108htop.t.cover_simple_immediate_108' 1 -C 'ft/t_assert_ctl_arg.vl108n37tuserpagev_user/tocover_simple_immediate_stmt_108htop.t.cover_simple_immediate_stmt_108' 1 -C 'ft/t_assert_ctl_arg.vl108n40tuserpagev_user/tocover_final_deferred_immediate_108htop.t.cover_final_deferred_immediate_108' 1 -C 'ft/t_assert_ctl_arg.vl108n43tuserpagev_user/tocover_observed_deferred_immediate_108htop.t.cover_observed_deferred_immediate_108' 1 -C 'ft/t_assert_ctl_arg.vl108n45tuserpagev_user/tocover_final_deferred_immediate_stmt_108htop.t.cover_final_deferred_immediate_stmt_108' 1 -C 'ft/t_assert_ctl_arg.vl108n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_108htop.t.cover_observed_deferred_immediate_stmt_108' 1 -C 'ft/t_assert_ctl_arg.vl110n32tuserpagev_user/tocover_simple_immediate_110htop.t.cover_simple_immediate_110' 0 -C 'ft/t_assert_ctl_arg.vl110n37tuserpagev_user/tocover_simple_immediate_stmt_110htop.t.cover_simple_immediate_stmt_110' 0 -C 'ft/t_assert_ctl_arg.vl110n40tuserpagev_user/tocover_final_deferred_immediate_110htop.t.cover_final_deferred_immediate_110' 0 -C 'ft/t_assert_ctl_arg.vl110n43tuserpagev_user/tocover_observed_deferred_immediate_110htop.t.cover_observed_deferred_immediate_110' 0 -C 'ft/t_assert_ctl_arg.vl110n45tuserpagev_user/tocover_final_deferred_immediate_stmt_110htop.t.cover_final_deferred_immediate_stmt_110' 0 -C 'ft/t_assert_ctl_arg.vl110n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_110htop.t.cover_observed_deferred_immediate_stmt_110' 0 -C 'ft/t_assert_ctl_arg.vl112n32tuserpagev_user/tocover_simple_immediate_112htop.t.cover_simple_immediate_112' 1 -C 'ft/t_assert_ctl_arg.vl112n37tuserpagev_user/tocover_simple_immediate_stmt_112htop.t.cover_simple_immediate_stmt_112' 1 -C 'ft/t_assert_ctl_arg.vl112n40tuserpagev_user/tocover_final_deferred_immediate_112htop.t.cover_final_deferred_immediate_112' 1 -C 'ft/t_assert_ctl_arg.vl112n43tuserpagev_user/tocover_observed_deferred_immediate_112htop.t.cover_observed_deferred_immediate_112' 0 -C 'ft/t_assert_ctl_arg.vl112n45tuserpagev_user/tocover_final_deferred_immediate_stmt_112htop.t.cover_final_deferred_immediate_stmt_112' 1 -C 'ft/t_assert_ctl_arg.vl112n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_112htop.t.cover_observed_deferred_immediate_stmt_112' 0 -C 'ft/t_assert_ctl_arg.vl192n22tuserpagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0 -C 'ft/t_assert_ctl_arg.vl193n27tuserpagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0 -C 'ft/t_assert_ctl_arg.vl49n31tuserpagev_user/tocover_simple_immediate_49htop.t.cover_simple_immediate_49' 1 -C 'ft/t_assert_ctl_arg.vl49n36tuserpagev_user/tocover_simple_immediate_stmt_49htop.t.cover_simple_immediate_stmt_49' 1 -C 'ft/t_assert_ctl_arg.vl49n39tuserpagev_user/tocover_final_deferred_immediate_49htop.t.cover_final_deferred_immediate_49' 0 -C 'ft/t_assert_ctl_arg.vl49n42tuserpagev_user/tocover_observed_deferred_immediate_49htop.t.cover_observed_deferred_immediate_49' 0 -C 'ft/t_assert_ctl_arg.vl49n44tuserpagev_user/tocover_final_deferred_immediate_stmt_49htop.t.cover_final_deferred_immediate_stmt_49' 0 -C 'ft/t_assert_ctl_arg.vl49n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_49htop.t.cover_observed_deferred_immediate_stmt_49' 0 -C 'ft/t_assert_ctl_arg.vl51n31tuserpagev_user/tocover_simple_immediate_51htop.t.cover_simple_immediate_51' 0 -C 'ft/t_assert_ctl_arg.vl51n36tuserpagev_user/tocover_simple_immediate_stmt_51htop.t.cover_simple_immediate_stmt_51' 0 -C 'ft/t_assert_ctl_arg.vl51n39tuserpagev_user/tocover_final_deferred_immediate_51htop.t.cover_final_deferred_immediate_51' 0 -C 'ft/t_assert_ctl_arg.vl51n42tuserpagev_user/tocover_observed_deferred_immediate_51htop.t.cover_observed_deferred_immediate_51' 0 -C 'ft/t_assert_ctl_arg.vl51n44tuserpagev_user/tocover_final_deferred_immediate_stmt_51htop.t.cover_final_deferred_immediate_stmt_51' 0 -C 'ft/t_assert_ctl_arg.vl51n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_51htop.t.cover_observed_deferred_immediate_stmt_51' 0 -C 'ft/t_assert_ctl_arg.vl56n31tuserpagev_user/tocover_simple_immediate_56htop.t.cover_simple_immediate_56' 0 -C 'ft/t_assert_ctl_arg.vl56n36tuserpagev_user/tocover_simple_immediate_stmt_56htop.t.cover_simple_immediate_stmt_56' 0 -C 'ft/t_assert_ctl_arg.vl56n39tuserpagev_user/tocover_final_deferred_immediate_56htop.t.cover_final_deferred_immediate_56' 0 -C 'ft/t_assert_ctl_arg.vl56n42tuserpagev_user/tocover_observed_deferred_immediate_56htop.t.cover_observed_deferred_immediate_56' 1 -C 'ft/t_assert_ctl_arg.vl56n44tuserpagev_user/tocover_final_deferred_immediate_stmt_56htop.t.cover_final_deferred_immediate_stmt_56' 0 -C 'ft/t_assert_ctl_arg.vl56n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_56htop.t.cover_observed_deferred_immediate_stmt_56' 1 -C 'ft/t_assert_ctl_arg.vl58n31tuserpagev_user/tocover_simple_immediate_58htop.t.cover_simple_immediate_58' 0 -C 'ft/t_assert_ctl_arg.vl58n36tuserpagev_user/tocover_simple_immediate_stmt_58htop.t.cover_simple_immediate_stmt_58' 0 -C 'ft/t_assert_ctl_arg.vl58n39tuserpagev_user/tocover_final_deferred_immediate_58htop.t.cover_final_deferred_immediate_58' 0 -C 'ft/t_assert_ctl_arg.vl58n42tuserpagev_user/tocover_observed_deferred_immediate_58htop.t.cover_observed_deferred_immediate_58' 0 -C 'ft/t_assert_ctl_arg.vl58n44tuserpagev_user/tocover_final_deferred_immediate_stmt_58htop.t.cover_final_deferred_immediate_stmt_58' 0 -C 'ft/t_assert_ctl_arg.vl58n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_58htop.t.cover_observed_deferred_immediate_stmt_58' 0 -C 'ft/t_assert_ctl_arg.vl63n31tuserpagev_user/tocover_simple_immediate_63htop.t.cover_simple_immediate_63' 0 -C 'ft/t_assert_ctl_arg.vl63n36tuserpagev_user/tocover_simple_immediate_stmt_63htop.t.cover_simple_immediate_stmt_63' 0 -C 'ft/t_assert_ctl_arg.vl63n39tuserpagev_user/tocover_final_deferred_immediate_63htop.t.cover_final_deferred_immediate_63' 1 -C 'ft/t_assert_ctl_arg.vl63n42tuserpagev_user/tocover_observed_deferred_immediate_63htop.t.cover_observed_deferred_immediate_63' 0 -C 'ft/t_assert_ctl_arg.vl63n44tuserpagev_user/tocover_final_deferred_immediate_stmt_63htop.t.cover_final_deferred_immediate_stmt_63' 1 -C 'ft/t_assert_ctl_arg.vl63n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_63htop.t.cover_observed_deferred_immediate_stmt_63' 0 -C 'ft/t_assert_ctl_arg.vl65n31tuserpagev_user/tocover_simple_immediate_65htop.t.cover_simple_immediate_65' 0 -C 'ft/t_assert_ctl_arg.vl65n36tuserpagev_user/tocover_simple_immediate_stmt_65htop.t.cover_simple_immediate_stmt_65' 0 -C 'ft/t_assert_ctl_arg.vl65n39tuserpagev_user/tocover_final_deferred_immediate_65htop.t.cover_final_deferred_immediate_65' 0 -C 'ft/t_assert_ctl_arg.vl65n42tuserpagev_user/tocover_observed_deferred_immediate_65htop.t.cover_observed_deferred_immediate_65' 0 -C 'ft/t_assert_ctl_arg.vl65n44tuserpagev_user/tocover_final_deferred_immediate_stmt_65htop.t.cover_final_deferred_immediate_stmt_65' 0 -C 'ft/t_assert_ctl_arg.vl65n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_65htop.t.cover_observed_deferred_immediate_stmt_65' 0 -C 'ft/t_assert_ctl_arg.vl69n31tuserpagev_user/tocover_simple_immediate_69htop.t.cover_simple_immediate_69' 0 -C 'ft/t_assert_ctl_arg.vl69n36tuserpagev_user/tocover_simple_immediate_stmt_69htop.t.cover_simple_immediate_stmt_69' 0 -C 'ft/t_assert_ctl_arg.vl69n39tuserpagev_user/tocover_final_deferred_immediate_69htop.t.cover_final_deferred_immediate_69' 0 -C 'ft/t_assert_ctl_arg.vl69n42tuserpagev_user/tocover_observed_deferred_immediate_69htop.t.cover_observed_deferred_immediate_69' 0 -C 'ft/t_assert_ctl_arg.vl69n44tuserpagev_user/tocover_final_deferred_immediate_stmt_69htop.t.cover_final_deferred_immediate_stmt_69' 0 -C 'ft/t_assert_ctl_arg.vl69n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_69htop.t.cover_observed_deferred_immediate_stmt_69' 0 -C 'ft/t_assert_ctl_arg.vl71n31tuserpagev_user/tocover_simple_immediate_71htop.t.cover_simple_immediate_71' 1 -C 'ft/t_assert_ctl_arg.vl71n36tuserpagev_user/tocover_simple_immediate_stmt_71htop.t.cover_simple_immediate_stmt_71' 1 -C 'ft/t_assert_ctl_arg.vl71n39tuserpagev_user/tocover_final_deferred_immediate_71htop.t.cover_final_deferred_immediate_71' 1 -C 'ft/t_assert_ctl_arg.vl71n42tuserpagev_user/tocover_observed_deferred_immediate_71htop.t.cover_observed_deferred_immediate_71' 1 -C 'ft/t_assert_ctl_arg.vl71n44tuserpagev_user/tocover_final_deferred_immediate_stmt_71htop.t.cover_final_deferred_immediate_stmt_71' 1 -C 'ft/t_assert_ctl_arg.vl71n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_71htop.t.cover_observed_deferred_immediate_stmt_71' 1 -C 'ft/t_assert_ctl_arg.vl73n31tuserpagev_user/tocover_simple_immediate_73htop.t.cover_simple_immediate_73' 0 -C 'ft/t_assert_ctl_arg.vl73n36tuserpagev_user/tocover_simple_immediate_stmt_73htop.t.cover_simple_immediate_stmt_73' 0 -C 'ft/t_assert_ctl_arg.vl73n39tuserpagev_user/tocover_final_deferred_immediate_73htop.t.cover_final_deferred_immediate_73' 0 -C 'ft/t_assert_ctl_arg.vl73n42tuserpagev_user/tocover_observed_deferred_immediate_73htop.t.cover_observed_deferred_immediate_73' 0 -C 'ft/t_assert_ctl_arg.vl73n44tuserpagev_user/tocover_final_deferred_immediate_stmt_73htop.t.cover_final_deferred_immediate_stmt_73' 0 -C 'ft/t_assert_ctl_arg.vl73n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_73htop.t.cover_observed_deferred_immediate_stmt_73' 0 -C 'ft/t_assert_ctl_arg.vl76n31tuserpagev_user/tocover_simple_immediate_76htop.t.cover_simple_immediate_76' 1 -C 'ft/t_assert_ctl_arg.vl76n36tuserpagev_user/tocover_simple_immediate_stmt_76htop.t.cover_simple_immediate_stmt_76' 1 -C 'ft/t_assert_ctl_arg.vl76n39tuserpagev_user/tocover_final_deferred_immediate_76htop.t.cover_final_deferred_immediate_76' 0 -C 'ft/t_assert_ctl_arg.vl76n42tuserpagev_user/tocover_observed_deferred_immediate_76htop.t.cover_observed_deferred_immediate_76' 1 -C 'ft/t_assert_ctl_arg.vl76n44tuserpagev_user/tocover_final_deferred_immediate_stmt_76htop.t.cover_final_deferred_immediate_stmt_76' 0 -C 'ft/t_assert_ctl_arg.vl76n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_76htop.t.cover_observed_deferred_immediate_stmt_76' 1 -C 'ft/t_assert_ctl_arg.vl78n31tuserpagev_user/tocover_simple_immediate_78htop.t.cover_simple_immediate_78' 1 -C 'ft/t_assert_ctl_arg.vl78n36tuserpagev_user/tocover_simple_immediate_stmt_78htop.t.cover_simple_immediate_stmt_78' 1 -C 'ft/t_assert_ctl_arg.vl78n39tuserpagev_user/tocover_final_deferred_immediate_78htop.t.cover_final_deferred_immediate_78' 1 -C 'ft/t_assert_ctl_arg.vl78n42tuserpagev_user/tocover_observed_deferred_immediate_78htop.t.cover_observed_deferred_immediate_78' 1 -C 'ft/t_assert_ctl_arg.vl78n44tuserpagev_user/tocover_final_deferred_immediate_stmt_78htop.t.cover_final_deferred_immediate_stmt_78' 1 -C 'ft/t_assert_ctl_arg.vl78n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_78htop.t.cover_observed_deferred_immediate_stmt_78' 1 -C 'ft/t_assert_ctl_arg.vl80n31tuserpagev_user/tocover_simple_immediate_80htop.t.cover_simple_immediate_80' 1 -C 'ft/t_assert_ctl_arg.vl80n36tuserpagev_user/tocover_simple_immediate_stmt_80htop.t.cover_simple_immediate_stmt_80' 1 -C 'ft/t_assert_ctl_arg.vl80n39tuserpagev_user/tocover_final_deferred_immediate_80htop.t.cover_final_deferred_immediate_80' 0 -C 'ft/t_assert_ctl_arg.vl80n42tuserpagev_user/tocover_observed_deferred_immediate_80htop.t.cover_observed_deferred_immediate_80' 0 -C 'ft/t_assert_ctl_arg.vl80n44tuserpagev_user/tocover_final_deferred_immediate_stmt_80htop.t.cover_final_deferred_immediate_stmt_80' 0 -C 'ft/t_assert_ctl_arg.vl80n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_80htop.t.cover_observed_deferred_immediate_stmt_80' 0 -C 'ft/t_assert_ctl_arg.vl82n31tuserpagev_user/tocover_simple_immediate_82htop.t.cover_simple_immediate_82' 1 -C 'ft/t_assert_ctl_arg.vl82n36tuserpagev_user/tocover_simple_immediate_stmt_82htop.t.cover_simple_immediate_stmt_82' 1 -C 'ft/t_assert_ctl_arg.vl82n39tuserpagev_user/tocover_final_deferred_immediate_82htop.t.cover_final_deferred_immediate_82' 0 -C 'ft/t_assert_ctl_arg.vl82n42tuserpagev_user/tocover_observed_deferred_immediate_82htop.t.cover_observed_deferred_immediate_82' 0 -C 'ft/t_assert_ctl_arg.vl82n44tuserpagev_user/tocover_final_deferred_immediate_stmt_82htop.t.cover_final_deferred_immediate_stmt_82' 0 -C 'ft/t_assert_ctl_arg.vl82n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_82htop.t.cover_observed_deferred_immediate_stmt_82' 0 -C 'ft/t_assert_ctl_arg.vl84n31tuserpagev_user/tocover_simple_immediate_84htop.t.cover_simple_immediate_84' 0 -C 'ft/t_assert_ctl_arg.vl84n36tuserpagev_user/tocover_simple_immediate_stmt_84htop.t.cover_simple_immediate_stmt_84' 0 -C 'ft/t_assert_ctl_arg.vl84n39tuserpagev_user/tocover_final_deferred_immediate_84htop.t.cover_final_deferred_immediate_84' 0 -C 'ft/t_assert_ctl_arg.vl84n42tuserpagev_user/tocover_observed_deferred_immediate_84htop.t.cover_observed_deferred_immediate_84' 0 -C 'ft/t_assert_ctl_arg.vl84n44tuserpagev_user/tocover_final_deferred_immediate_stmt_84htop.t.cover_final_deferred_immediate_stmt_84' 0 -C 'ft/t_assert_ctl_arg.vl84n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_84htop.t.cover_observed_deferred_immediate_stmt_84' 0 -C 'ft/t_assert_ctl_arg.vl86n31tuserpagev_user/tocover_simple_immediate_86htop.t.cover_simple_immediate_86' 1 -C 'ft/t_assert_ctl_arg.vl86n36tuserpagev_user/tocover_simple_immediate_stmt_86htop.t.cover_simple_immediate_stmt_86' 1 -C 'ft/t_assert_ctl_arg.vl86n39tuserpagev_user/tocover_final_deferred_immediate_86htop.t.cover_final_deferred_immediate_86' 0 -C 'ft/t_assert_ctl_arg.vl86n42tuserpagev_user/tocover_observed_deferred_immediate_86htop.t.cover_observed_deferred_immediate_86' 0 -C 'ft/t_assert_ctl_arg.vl86n44tuserpagev_user/tocover_final_deferred_immediate_stmt_86htop.t.cover_final_deferred_immediate_stmt_86' 0 -C 'ft/t_assert_ctl_arg.vl86n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_86htop.t.cover_observed_deferred_immediate_stmt_86' 0 -C 'ft/t_assert_ctl_arg.vl88n31tuserpagev_user/tocover_simple_immediate_88htop.t.cover_simple_immediate_88' 0 -C 'ft/t_assert_ctl_arg.vl88n36tuserpagev_user/tocover_simple_immediate_stmt_88htop.t.cover_simple_immediate_stmt_88' 0 -C 'ft/t_assert_ctl_arg.vl88n39tuserpagev_user/tocover_final_deferred_immediate_88htop.t.cover_final_deferred_immediate_88' 0 -C 'ft/t_assert_ctl_arg.vl88n42tuserpagev_user/tocover_observed_deferred_immediate_88htop.t.cover_observed_deferred_immediate_88' 0 -C 'ft/t_assert_ctl_arg.vl88n44tuserpagev_user/tocover_final_deferred_immediate_stmt_88htop.t.cover_final_deferred_immediate_stmt_88' 0 -C 'ft/t_assert_ctl_arg.vl88n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_88htop.t.cover_observed_deferred_immediate_stmt_88' 0 -C 'ft/t_assert_ctl_arg.vl90n31tuserpagev_user/tocover_simple_immediate_90htop.t.cover_simple_immediate_90' 1 -C 'ft/t_assert_ctl_arg.vl90n36tuserpagev_user/tocover_simple_immediate_stmt_90htop.t.cover_simple_immediate_stmt_90' 1 -C 'ft/t_assert_ctl_arg.vl90n39tuserpagev_user/tocover_final_deferred_immediate_90htop.t.cover_final_deferred_immediate_90' 1 -C 'ft/t_assert_ctl_arg.vl90n42tuserpagev_user/tocover_observed_deferred_immediate_90htop.t.cover_observed_deferred_immediate_90' 1 -C 'ft/t_assert_ctl_arg.vl90n44tuserpagev_user/tocover_final_deferred_immediate_stmt_90htop.t.cover_final_deferred_immediate_stmt_90' 1 -C 'ft/t_assert_ctl_arg.vl90n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_90htop.t.cover_observed_deferred_immediate_stmt_90' 1 -C 'ft/t_assert_ctl_arg.vl92n31tuserpagev_user/tocover_simple_immediate_92htop.t.cover_simple_immediate_92' 0 -C 'ft/t_assert_ctl_arg.vl92n36tuserpagev_user/tocover_simple_immediate_stmt_92htop.t.cover_simple_immediate_stmt_92' 0 -C 'ft/t_assert_ctl_arg.vl92n39tuserpagev_user/tocover_final_deferred_immediate_92htop.t.cover_final_deferred_immediate_92' 0 -C 'ft/t_assert_ctl_arg.vl92n42tuserpagev_user/tocover_observed_deferred_immediate_92htop.t.cover_observed_deferred_immediate_92' 0 -C 'ft/t_assert_ctl_arg.vl92n44tuserpagev_user/tocover_final_deferred_immediate_stmt_92htop.t.cover_final_deferred_immediate_stmt_92' 0 -C 'ft/t_assert_ctl_arg.vl92n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_92htop.t.cover_observed_deferred_immediate_stmt_92' 0 -C 'ft/t_assert_ctl_arg.vl97n31tuserpagev_user/tocover_simple_immediate_97htop.t.cover_simple_immediate_97' 0 -C 'ft/t_assert_ctl_arg.vl97n36tuserpagev_user/tocover_simple_immediate_stmt_97htop.t.cover_simple_immediate_stmt_97' 0 -C 'ft/t_assert_ctl_arg.vl97n39tuserpagev_user/tocover_final_deferred_immediate_97htop.t.cover_final_deferred_immediate_97' 0 -C 'ft/t_assert_ctl_arg.vl97n42tuserpagev_user/tocover_observed_deferred_immediate_97htop.t.cover_observed_deferred_immediate_97' 0 -C 'ft/t_assert_ctl_arg.vl97n44tuserpagev_user/tocover_final_deferred_immediate_stmt_97htop.t.cover_final_deferred_immediate_stmt_97' 0 -C 'ft/t_assert_ctl_arg.vl97n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_97htop.t.cover_observed_deferred_immediate_stmt_97' 0 +C 'ft/t_assert_ctl_arg.vl102n31tuserpagev_user/tocover_simple_immediate_102htop.t.cover_simple_immediate_102' 0 +C 'ft/t_assert_ctl_arg.vl102n36tuserpagev_user/tocover_simple_immediate_stmt_102htop.t.cover_simple_immediate_stmt_102' 0 +C 'ft/t_assert_ctl_arg.vl102n39tuserpagev_user/tocover_final_deferred_immediate_102htop.t.cover_final_deferred_immediate_102' 0 +C 'ft/t_assert_ctl_arg.vl102n42tuserpagev_user/tocover_observed_deferred_immediate_102htop.t.cover_observed_deferred_immediate_102' 0 +C 'ft/t_assert_ctl_arg.vl102n44tuserpagev_user/tocover_final_deferred_immediate_stmt_102htop.t.cover_final_deferred_immediate_stmt_102' 0 +C 'ft/t_assert_ctl_arg.vl102n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_102htop.t.cover_observed_deferred_immediate_stmt_102' 0 +C 'ft/t_assert_ctl_arg.vl105n31tuserpagev_user/tocover_simple_immediate_105htop.t.cover_simple_immediate_105' 1 +C 'ft/t_assert_ctl_arg.vl105n36tuserpagev_user/tocover_simple_immediate_stmt_105htop.t.cover_simple_immediate_stmt_105' 1 +C 'ft/t_assert_ctl_arg.vl105n39tuserpagev_user/tocover_final_deferred_immediate_105htop.t.cover_final_deferred_immediate_105' 1 +C 'ft/t_assert_ctl_arg.vl105n42tuserpagev_user/tocover_observed_deferred_immediate_105htop.t.cover_observed_deferred_immediate_105' 1 +C 'ft/t_assert_ctl_arg.vl105n44tuserpagev_user/tocover_final_deferred_immediate_stmt_105htop.t.cover_final_deferred_immediate_stmt_105' 1 +C 'ft/t_assert_ctl_arg.vl105n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_105htop.t.cover_observed_deferred_immediate_stmt_105' 1 +C 'ft/t_assert_ctl_arg.vl107n31tuserpagev_user/tocover_simple_immediate_107htop.t.cover_simple_immediate_107' 1 +C 'ft/t_assert_ctl_arg.vl107n36tuserpagev_user/tocover_simple_immediate_stmt_107htop.t.cover_simple_immediate_stmt_107' 1 +C 'ft/t_assert_ctl_arg.vl107n39tuserpagev_user/tocover_final_deferred_immediate_107htop.t.cover_final_deferred_immediate_107' 1 +C 'ft/t_assert_ctl_arg.vl107n42tuserpagev_user/tocover_observed_deferred_immediate_107htop.t.cover_observed_deferred_immediate_107' 1 +C 'ft/t_assert_ctl_arg.vl107n44tuserpagev_user/tocover_final_deferred_immediate_stmt_107htop.t.cover_final_deferred_immediate_stmt_107' 1 +C 'ft/t_assert_ctl_arg.vl107n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_107htop.t.cover_observed_deferred_immediate_stmt_107' 1 +C 'ft/t_assert_ctl_arg.vl109n31tuserpagev_user/tocover_simple_immediate_109htop.t.cover_simple_immediate_109' 0 +C 'ft/t_assert_ctl_arg.vl109n36tuserpagev_user/tocover_simple_immediate_stmt_109htop.t.cover_simple_immediate_stmt_109' 0 +C 'ft/t_assert_ctl_arg.vl109n39tuserpagev_user/tocover_final_deferred_immediate_109htop.t.cover_final_deferred_immediate_109' 0 +C 'ft/t_assert_ctl_arg.vl109n42tuserpagev_user/tocover_observed_deferred_immediate_109htop.t.cover_observed_deferred_immediate_109' 0 +C 'ft/t_assert_ctl_arg.vl109n44tuserpagev_user/tocover_final_deferred_immediate_stmt_109htop.t.cover_final_deferred_immediate_stmt_109' 0 +C 'ft/t_assert_ctl_arg.vl109n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_109htop.t.cover_observed_deferred_immediate_stmt_109' 0 +C 'ft/t_assert_ctl_arg.vl111n31tuserpagev_user/tocover_simple_immediate_111htop.t.cover_simple_immediate_111' 1 +C 'ft/t_assert_ctl_arg.vl111n36tuserpagev_user/tocover_simple_immediate_stmt_111htop.t.cover_simple_immediate_stmt_111' 1 +C 'ft/t_assert_ctl_arg.vl111n39tuserpagev_user/tocover_final_deferred_immediate_111htop.t.cover_final_deferred_immediate_111' 1 +C 'ft/t_assert_ctl_arg.vl111n42tuserpagev_user/tocover_observed_deferred_immediate_111htop.t.cover_observed_deferred_immediate_111' 0 +C 'ft/t_assert_ctl_arg.vl111n44tuserpagev_user/tocover_final_deferred_immediate_stmt_111htop.t.cover_final_deferred_immediate_stmt_111' 1 +C 'ft/t_assert_ctl_arg.vl111n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_111htop.t.cover_observed_deferred_immediate_stmt_111' 0 +C 'ft/t_assert_ctl_arg.vl191n21tuserpagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0 +C 'ft/t_assert_ctl_arg.vl192n26tuserpagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0 +C 'ft/t_assert_ctl_arg.vl48n30tuserpagev_user/tocover_simple_immediate_48htop.t.cover_simple_immediate_48' 1 +C 'ft/t_assert_ctl_arg.vl48n35tuserpagev_user/tocover_simple_immediate_stmt_48htop.t.cover_simple_immediate_stmt_48' 1 +C 'ft/t_assert_ctl_arg.vl48n38tuserpagev_user/tocover_final_deferred_immediate_48htop.t.cover_final_deferred_immediate_48' 0 +C 'ft/t_assert_ctl_arg.vl48n41tuserpagev_user/tocover_observed_deferred_immediate_48htop.t.cover_observed_deferred_immediate_48' 0 +C 'ft/t_assert_ctl_arg.vl48n43tuserpagev_user/tocover_final_deferred_immediate_stmt_48htop.t.cover_final_deferred_immediate_stmt_48' 0 +C 'ft/t_assert_ctl_arg.vl48n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_48htop.t.cover_observed_deferred_immediate_stmt_48' 0 +C 'ft/t_assert_ctl_arg.vl50n30tuserpagev_user/tocover_simple_immediate_50htop.t.cover_simple_immediate_50' 0 +C 'ft/t_assert_ctl_arg.vl50n35tuserpagev_user/tocover_simple_immediate_stmt_50htop.t.cover_simple_immediate_stmt_50' 0 +C 'ft/t_assert_ctl_arg.vl50n38tuserpagev_user/tocover_final_deferred_immediate_50htop.t.cover_final_deferred_immediate_50' 0 +C 'ft/t_assert_ctl_arg.vl50n41tuserpagev_user/tocover_observed_deferred_immediate_50htop.t.cover_observed_deferred_immediate_50' 0 +C 'ft/t_assert_ctl_arg.vl50n43tuserpagev_user/tocover_final_deferred_immediate_stmt_50htop.t.cover_final_deferred_immediate_stmt_50' 0 +C 'ft/t_assert_ctl_arg.vl50n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_50htop.t.cover_observed_deferred_immediate_stmt_50' 0 +C 'ft/t_assert_ctl_arg.vl55n30tuserpagev_user/tocover_simple_immediate_55htop.t.cover_simple_immediate_55' 0 +C 'ft/t_assert_ctl_arg.vl55n35tuserpagev_user/tocover_simple_immediate_stmt_55htop.t.cover_simple_immediate_stmt_55' 0 +C 'ft/t_assert_ctl_arg.vl55n38tuserpagev_user/tocover_final_deferred_immediate_55htop.t.cover_final_deferred_immediate_55' 0 +C 'ft/t_assert_ctl_arg.vl55n41tuserpagev_user/tocover_observed_deferred_immediate_55htop.t.cover_observed_deferred_immediate_55' 1 +C 'ft/t_assert_ctl_arg.vl55n43tuserpagev_user/tocover_final_deferred_immediate_stmt_55htop.t.cover_final_deferred_immediate_stmt_55' 0 +C 'ft/t_assert_ctl_arg.vl55n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_55htop.t.cover_observed_deferred_immediate_stmt_55' 1 +C 'ft/t_assert_ctl_arg.vl57n30tuserpagev_user/tocover_simple_immediate_57htop.t.cover_simple_immediate_57' 0 +C 'ft/t_assert_ctl_arg.vl57n35tuserpagev_user/tocover_simple_immediate_stmt_57htop.t.cover_simple_immediate_stmt_57' 0 +C 'ft/t_assert_ctl_arg.vl57n38tuserpagev_user/tocover_final_deferred_immediate_57htop.t.cover_final_deferred_immediate_57' 0 +C 'ft/t_assert_ctl_arg.vl57n41tuserpagev_user/tocover_observed_deferred_immediate_57htop.t.cover_observed_deferred_immediate_57' 0 +C 'ft/t_assert_ctl_arg.vl57n43tuserpagev_user/tocover_final_deferred_immediate_stmt_57htop.t.cover_final_deferred_immediate_stmt_57' 0 +C 'ft/t_assert_ctl_arg.vl57n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_57htop.t.cover_observed_deferred_immediate_stmt_57' 0 +C 'ft/t_assert_ctl_arg.vl62n30tuserpagev_user/tocover_simple_immediate_62htop.t.cover_simple_immediate_62' 0 +C 'ft/t_assert_ctl_arg.vl62n35tuserpagev_user/tocover_simple_immediate_stmt_62htop.t.cover_simple_immediate_stmt_62' 0 +C 'ft/t_assert_ctl_arg.vl62n38tuserpagev_user/tocover_final_deferred_immediate_62htop.t.cover_final_deferred_immediate_62' 1 +C 'ft/t_assert_ctl_arg.vl62n41tuserpagev_user/tocover_observed_deferred_immediate_62htop.t.cover_observed_deferred_immediate_62' 0 +C 'ft/t_assert_ctl_arg.vl62n43tuserpagev_user/tocover_final_deferred_immediate_stmt_62htop.t.cover_final_deferred_immediate_stmt_62' 1 +C 'ft/t_assert_ctl_arg.vl62n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_62htop.t.cover_observed_deferred_immediate_stmt_62' 0 +C 'ft/t_assert_ctl_arg.vl64n30tuserpagev_user/tocover_simple_immediate_64htop.t.cover_simple_immediate_64' 0 +C 'ft/t_assert_ctl_arg.vl64n35tuserpagev_user/tocover_simple_immediate_stmt_64htop.t.cover_simple_immediate_stmt_64' 0 +C 'ft/t_assert_ctl_arg.vl64n38tuserpagev_user/tocover_final_deferred_immediate_64htop.t.cover_final_deferred_immediate_64' 0 +C 'ft/t_assert_ctl_arg.vl64n41tuserpagev_user/tocover_observed_deferred_immediate_64htop.t.cover_observed_deferred_immediate_64' 0 +C 'ft/t_assert_ctl_arg.vl64n43tuserpagev_user/tocover_final_deferred_immediate_stmt_64htop.t.cover_final_deferred_immediate_stmt_64' 0 +C 'ft/t_assert_ctl_arg.vl64n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_64htop.t.cover_observed_deferred_immediate_stmt_64' 0 +C 'ft/t_assert_ctl_arg.vl68n30tuserpagev_user/tocover_simple_immediate_68htop.t.cover_simple_immediate_68' 0 +C 'ft/t_assert_ctl_arg.vl68n35tuserpagev_user/tocover_simple_immediate_stmt_68htop.t.cover_simple_immediate_stmt_68' 0 +C 'ft/t_assert_ctl_arg.vl68n38tuserpagev_user/tocover_final_deferred_immediate_68htop.t.cover_final_deferred_immediate_68' 0 +C 'ft/t_assert_ctl_arg.vl68n41tuserpagev_user/tocover_observed_deferred_immediate_68htop.t.cover_observed_deferred_immediate_68' 0 +C 'ft/t_assert_ctl_arg.vl68n43tuserpagev_user/tocover_final_deferred_immediate_stmt_68htop.t.cover_final_deferred_immediate_stmt_68' 0 +C 'ft/t_assert_ctl_arg.vl68n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_68htop.t.cover_observed_deferred_immediate_stmt_68' 0 +C 'ft/t_assert_ctl_arg.vl70n30tuserpagev_user/tocover_simple_immediate_70htop.t.cover_simple_immediate_70' 1 +C 'ft/t_assert_ctl_arg.vl70n35tuserpagev_user/tocover_simple_immediate_stmt_70htop.t.cover_simple_immediate_stmt_70' 1 +C 'ft/t_assert_ctl_arg.vl70n38tuserpagev_user/tocover_final_deferred_immediate_70htop.t.cover_final_deferred_immediate_70' 1 +C 'ft/t_assert_ctl_arg.vl70n41tuserpagev_user/tocover_observed_deferred_immediate_70htop.t.cover_observed_deferred_immediate_70' 1 +C 'ft/t_assert_ctl_arg.vl70n43tuserpagev_user/tocover_final_deferred_immediate_stmt_70htop.t.cover_final_deferred_immediate_stmt_70' 1 +C 'ft/t_assert_ctl_arg.vl70n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_70htop.t.cover_observed_deferred_immediate_stmt_70' 1 +C 'ft/t_assert_ctl_arg.vl72n30tuserpagev_user/tocover_simple_immediate_72htop.t.cover_simple_immediate_72' 0 +C 'ft/t_assert_ctl_arg.vl72n35tuserpagev_user/tocover_simple_immediate_stmt_72htop.t.cover_simple_immediate_stmt_72' 0 +C 'ft/t_assert_ctl_arg.vl72n38tuserpagev_user/tocover_final_deferred_immediate_72htop.t.cover_final_deferred_immediate_72' 0 +C 'ft/t_assert_ctl_arg.vl72n41tuserpagev_user/tocover_observed_deferred_immediate_72htop.t.cover_observed_deferred_immediate_72' 0 +C 'ft/t_assert_ctl_arg.vl72n43tuserpagev_user/tocover_final_deferred_immediate_stmt_72htop.t.cover_final_deferred_immediate_stmt_72' 0 +C 'ft/t_assert_ctl_arg.vl72n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_72htop.t.cover_observed_deferred_immediate_stmt_72' 0 +C 'ft/t_assert_ctl_arg.vl75n30tuserpagev_user/tocover_simple_immediate_75htop.t.cover_simple_immediate_75' 1 +C 'ft/t_assert_ctl_arg.vl75n35tuserpagev_user/tocover_simple_immediate_stmt_75htop.t.cover_simple_immediate_stmt_75' 1 +C 'ft/t_assert_ctl_arg.vl75n38tuserpagev_user/tocover_final_deferred_immediate_75htop.t.cover_final_deferred_immediate_75' 0 +C 'ft/t_assert_ctl_arg.vl75n41tuserpagev_user/tocover_observed_deferred_immediate_75htop.t.cover_observed_deferred_immediate_75' 1 +C 'ft/t_assert_ctl_arg.vl75n43tuserpagev_user/tocover_final_deferred_immediate_stmt_75htop.t.cover_final_deferred_immediate_stmt_75' 0 +C 'ft/t_assert_ctl_arg.vl75n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_75htop.t.cover_observed_deferred_immediate_stmt_75' 1 +C 'ft/t_assert_ctl_arg.vl77n30tuserpagev_user/tocover_simple_immediate_77htop.t.cover_simple_immediate_77' 1 +C 'ft/t_assert_ctl_arg.vl77n35tuserpagev_user/tocover_simple_immediate_stmt_77htop.t.cover_simple_immediate_stmt_77' 1 +C 'ft/t_assert_ctl_arg.vl77n38tuserpagev_user/tocover_final_deferred_immediate_77htop.t.cover_final_deferred_immediate_77' 1 +C 'ft/t_assert_ctl_arg.vl77n41tuserpagev_user/tocover_observed_deferred_immediate_77htop.t.cover_observed_deferred_immediate_77' 1 +C 'ft/t_assert_ctl_arg.vl77n43tuserpagev_user/tocover_final_deferred_immediate_stmt_77htop.t.cover_final_deferred_immediate_stmt_77' 1 +C 'ft/t_assert_ctl_arg.vl77n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_77htop.t.cover_observed_deferred_immediate_stmt_77' 1 +C 'ft/t_assert_ctl_arg.vl79n30tuserpagev_user/tocover_simple_immediate_79htop.t.cover_simple_immediate_79' 1 +C 'ft/t_assert_ctl_arg.vl79n35tuserpagev_user/tocover_simple_immediate_stmt_79htop.t.cover_simple_immediate_stmt_79' 1 +C 'ft/t_assert_ctl_arg.vl79n38tuserpagev_user/tocover_final_deferred_immediate_79htop.t.cover_final_deferred_immediate_79' 0 +C 'ft/t_assert_ctl_arg.vl79n41tuserpagev_user/tocover_observed_deferred_immediate_79htop.t.cover_observed_deferred_immediate_79' 0 +C 'ft/t_assert_ctl_arg.vl79n43tuserpagev_user/tocover_final_deferred_immediate_stmt_79htop.t.cover_final_deferred_immediate_stmt_79' 0 +C 'ft/t_assert_ctl_arg.vl79n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_79htop.t.cover_observed_deferred_immediate_stmt_79' 0 +C 'ft/t_assert_ctl_arg.vl81n30tuserpagev_user/tocover_simple_immediate_81htop.t.cover_simple_immediate_81' 1 +C 'ft/t_assert_ctl_arg.vl81n35tuserpagev_user/tocover_simple_immediate_stmt_81htop.t.cover_simple_immediate_stmt_81' 1 +C 'ft/t_assert_ctl_arg.vl81n38tuserpagev_user/tocover_final_deferred_immediate_81htop.t.cover_final_deferred_immediate_81' 0 +C 'ft/t_assert_ctl_arg.vl81n41tuserpagev_user/tocover_observed_deferred_immediate_81htop.t.cover_observed_deferred_immediate_81' 0 +C 'ft/t_assert_ctl_arg.vl81n43tuserpagev_user/tocover_final_deferred_immediate_stmt_81htop.t.cover_final_deferred_immediate_stmt_81' 0 +C 'ft/t_assert_ctl_arg.vl81n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_81htop.t.cover_observed_deferred_immediate_stmt_81' 0 +C 'ft/t_assert_ctl_arg.vl83n30tuserpagev_user/tocover_simple_immediate_83htop.t.cover_simple_immediate_83' 0 +C 'ft/t_assert_ctl_arg.vl83n35tuserpagev_user/tocover_simple_immediate_stmt_83htop.t.cover_simple_immediate_stmt_83' 0 +C 'ft/t_assert_ctl_arg.vl83n38tuserpagev_user/tocover_final_deferred_immediate_83htop.t.cover_final_deferred_immediate_83' 0 +C 'ft/t_assert_ctl_arg.vl83n41tuserpagev_user/tocover_observed_deferred_immediate_83htop.t.cover_observed_deferred_immediate_83' 0 +C 'ft/t_assert_ctl_arg.vl83n43tuserpagev_user/tocover_final_deferred_immediate_stmt_83htop.t.cover_final_deferred_immediate_stmt_83' 0 +C 'ft/t_assert_ctl_arg.vl83n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_83htop.t.cover_observed_deferred_immediate_stmt_83' 0 +C 'ft/t_assert_ctl_arg.vl85n30tuserpagev_user/tocover_simple_immediate_85htop.t.cover_simple_immediate_85' 1 +C 'ft/t_assert_ctl_arg.vl85n35tuserpagev_user/tocover_simple_immediate_stmt_85htop.t.cover_simple_immediate_stmt_85' 1 +C 'ft/t_assert_ctl_arg.vl85n38tuserpagev_user/tocover_final_deferred_immediate_85htop.t.cover_final_deferred_immediate_85' 0 +C 'ft/t_assert_ctl_arg.vl85n41tuserpagev_user/tocover_observed_deferred_immediate_85htop.t.cover_observed_deferred_immediate_85' 0 +C 'ft/t_assert_ctl_arg.vl85n43tuserpagev_user/tocover_final_deferred_immediate_stmt_85htop.t.cover_final_deferred_immediate_stmt_85' 0 +C 'ft/t_assert_ctl_arg.vl85n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_85htop.t.cover_observed_deferred_immediate_stmt_85' 0 +C 'ft/t_assert_ctl_arg.vl87n30tuserpagev_user/tocover_simple_immediate_87htop.t.cover_simple_immediate_87' 0 +C 'ft/t_assert_ctl_arg.vl87n35tuserpagev_user/tocover_simple_immediate_stmt_87htop.t.cover_simple_immediate_stmt_87' 0 +C 'ft/t_assert_ctl_arg.vl87n38tuserpagev_user/tocover_final_deferred_immediate_87htop.t.cover_final_deferred_immediate_87' 0 +C 'ft/t_assert_ctl_arg.vl87n41tuserpagev_user/tocover_observed_deferred_immediate_87htop.t.cover_observed_deferred_immediate_87' 0 +C 'ft/t_assert_ctl_arg.vl87n43tuserpagev_user/tocover_final_deferred_immediate_stmt_87htop.t.cover_final_deferred_immediate_stmt_87' 0 +C 'ft/t_assert_ctl_arg.vl87n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_87htop.t.cover_observed_deferred_immediate_stmt_87' 0 +C 'ft/t_assert_ctl_arg.vl89n30tuserpagev_user/tocover_simple_immediate_89htop.t.cover_simple_immediate_89' 1 +C 'ft/t_assert_ctl_arg.vl89n35tuserpagev_user/tocover_simple_immediate_stmt_89htop.t.cover_simple_immediate_stmt_89' 1 +C 'ft/t_assert_ctl_arg.vl89n38tuserpagev_user/tocover_final_deferred_immediate_89htop.t.cover_final_deferred_immediate_89' 1 +C 'ft/t_assert_ctl_arg.vl89n41tuserpagev_user/tocover_observed_deferred_immediate_89htop.t.cover_observed_deferred_immediate_89' 1 +C 'ft/t_assert_ctl_arg.vl89n43tuserpagev_user/tocover_final_deferred_immediate_stmt_89htop.t.cover_final_deferred_immediate_stmt_89' 1 +C 'ft/t_assert_ctl_arg.vl89n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_89htop.t.cover_observed_deferred_immediate_stmt_89' 1 +C 'ft/t_assert_ctl_arg.vl91n30tuserpagev_user/tocover_simple_immediate_91htop.t.cover_simple_immediate_91' 0 +C 'ft/t_assert_ctl_arg.vl91n35tuserpagev_user/tocover_simple_immediate_stmt_91htop.t.cover_simple_immediate_stmt_91' 0 +C 'ft/t_assert_ctl_arg.vl91n38tuserpagev_user/tocover_final_deferred_immediate_91htop.t.cover_final_deferred_immediate_91' 0 +C 'ft/t_assert_ctl_arg.vl91n41tuserpagev_user/tocover_observed_deferred_immediate_91htop.t.cover_observed_deferred_immediate_91' 0 +C 'ft/t_assert_ctl_arg.vl91n43tuserpagev_user/tocover_final_deferred_immediate_stmt_91htop.t.cover_final_deferred_immediate_stmt_91' 0 +C 'ft/t_assert_ctl_arg.vl91n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_91htop.t.cover_observed_deferred_immediate_stmt_91' 0 +C 'ft/t_assert_ctl_arg.vl96n30tuserpagev_user/tocover_simple_immediate_96htop.t.cover_simple_immediate_96' 0 +C 'ft/t_assert_ctl_arg.vl96n35tuserpagev_user/tocover_simple_immediate_stmt_96htop.t.cover_simple_immediate_stmt_96' 0 +C 'ft/t_assert_ctl_arg.vl96n38tuserpagev_user/tocover_final_deferred_immediate_96htop.t.cover_final_deferred_immediate_96' 0 +C 'ft/t_assert_ctl_arg.vl96n41tuserpagev_user/tocover_observed_deferred_immediate_96htop.t.cover_observed_deferred_immediate_96' 0 +C 'ft/t_assert_ctl_arg.vl96n43tuserpagev_user/tocover_final_deferred_immediate_stmt_96htop.t.cover_final_deferred_immediate_stmt_96' 0 +C 'ft/t_assert_ctl_arg.vl96n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_96htop.t.cover_observed_deferred_immediate_stmt_96' 0 +C 'ft/t_assert_ctl_arg.vl99n30tuserpagev_user/tocover_simple_immediate_99htop.t.cover_simple_immediate_99' 1 +C 'ft/t_assert_ctl_arg.vl99n35tuserpagev_user/tocover_simple_immediate_stmt_99htop.t.cover_simple_immediate_stmt_99' 1 +C 'ft/t_assert_ctl_arg.vl99n38tuserpagev_user/tocover_final_deferred_immediate_99htop.t.cover_final_deferred_immediate_99' 1 +C 'ft/t_assert_ctl_arg.vl99n41tuserpagev_user/tocover_observed_deferred_immediate_99htop.t.cover_observed_deferred_immediate_99' 1 +C 'ft/t_assert_ctl_arg.vl99n43tuserpagev_user/tocover_final_deferred_immediate_stmt_99htop.t.cover_final_deferred_immediate_stmt_99' 1 +C 'ft/t_assert_ctl_arg.vl99n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_99htop.t.cover_observed_deferred_immediate_stmt_99' 1 diff --git a/test_regress/t/t_assert_ctl_arg.out b/test_regress/t/t_assert_ctl_arg.out index 61360e55d..dcd7751d8 100644 --- a/test_regress/t/t_assert_ctl_arg.out +++ b/test_regress/t/t_assert_ctl_arg.out @@ -1,416 +1,416 @@ ========== -Running all asserts at: t/t_assert_ctl_arg.v:49 +Running all asserts at: t/t_assert_ctl_arg.v:48 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:49 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. --Info: t/t_assert_ctl_arg.v:137: Verilog $stop, ignored due to +verilator+error+limit -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:49 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:49 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:49 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:49 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:49 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:49 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:49 -Passed 'top.t.cover_simple_immediate_stmt_49' at t/t_assert_ctl_arg.v:49 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:48 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +-Info: t/t_assert_ctl_arg.v:136: Verilog $stop, ignored due to +verilator+error+limit +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:48 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:48 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:48 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:48 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:48 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:48 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:48 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:48 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:48 +Passed 'top.t.cover_simple_immediate_stmt_48' at t/t_assert_ctl_arg.v:48 ========== -Running all asserts at: t/t_assert_ctl_arg.v:51 +Running all asserts at: t/t_assert_ctl_arg.v:50 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:51 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:51 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:51 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:51 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:51 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:51 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:50 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:50 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:50 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:50 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:50 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:50 ========== -Running all asserts at: t/t_assert_ctl_arg.v:56 +Running all asserts at: t/t_assert_ctl_arg.v:55 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:56 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:56 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:56 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:56 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:56 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:56 -Passed 'top.t.cover_observed_deferred_immediate_stmt_56' at t/t_assert_ctl_arg.v:56 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:55 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:55 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:55 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:55 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:55 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:55 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:55 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:55 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:55 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:55 +Passed 'top.t.cover_observed_deferred_immediate_stmt_55' at t/t_assert_ctl_arg.v:55 ========== -Running all asserts at: t/t_assert_ctl_arg.v:58 +Running all asserts at: t/t_assert_ctl_arg.v:57 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:58 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:58 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:58 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:58 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:58 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:58 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:57 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:57 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:57 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:57 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:57 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:57 ========== -Running all asserts at: t/t_assert_ctl_arg.v:63 +Running all asserts at: t/t_assert_ctl_arg.v:62 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:63 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:63 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:63 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:63 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:63 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:63 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63 -Passed 'top.t.cover_final_deferred_immediate_stmt_63' at t/t_assert_ctl_arg.v:63 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:62 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:62 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:62 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:62 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:62 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:62 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:62 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:62 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:62 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:62 +Passed 'top.t.cover_final_deferred_immediate_stmt_62' at t/t_assert_ctl_arg.v:62 ========== -Running all asserts at: t/t_assert_ctl_arg.v:65 +Running all asserts at: t/t_assert_ctl_arg.v:64 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:65 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:65 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:65 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:65 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:65 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:65 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:64 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:64 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:64 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:64 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:64 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:64 ========== -Running all asserts at: t/t_assert_ctl_arg.v:69 +Running all asserts at: t/t_assert_ctl_arg.v:68 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:69 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:69 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:69 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:69 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:69 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:69 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:68 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:68 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:68 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:68 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:68 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:68 ========== -Running all asserts at: t/t_assert_ctl_arg.v:71 +Running all asserts at: t/t_assert_ctl_arg.v:70 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Passed 'top.t.cover_simple_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 -Passed 'top.t.cover_observed_deferred_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 -Passed 'top.t.cover_final_deferred_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Passed 'top.t.cover_simple_immediate_stmt_70' at t/t_assert_ctl_arg.v:70 +Passed 'top.t.cover_observed_deferred_immediate_stmt_70' at t/t_assert_ctl_arg.v:70 +Passed 'top.t.cover_final_deferred_immediate_stmt_70' at t/t_assert_ctl_arg.v:70 ========== -Running all asserts at: t/t_assert_ctl_arg.v:73 +Running all asserts at: t/t_assert_ctl_arg.v:72 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:73 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:73 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:73 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:73 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:73 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:73 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:72 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:72 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:72 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:72 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:72 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:72 ========== -Running all asserts at: t/t_assert_ctl_arg.v:76 +Running all asserts at: t/t_assert_ctl_arg.v:75 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:76 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:76 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:76 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:76 -Passed 'top.t.cover_simple_immediate_stmt_76' at t/t_assert_ctl_arg.v:76 -Passed 'top.t.cover_observed_deferred_immediate_stmt_76' at t/t_assert_ctl_arg.v:76 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:75 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:75 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:75 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:75 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:75 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:75 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:75 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:75 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:75 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:75 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:75 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:75 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:75 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:75 +Passed 'top.t.cover_simple_immediate_stmt_75' at t/t_assert_ctl_arg.v:75 +Passed 'top.t.cover_observed_deferred_immediate_stmt_75' at t/t_assert_ctl_arg.v:75 ========== -Running all asserts at: t/t_assert_ctl_arg.v:78 +Running all asserts at: t/t_assert_ctl_arg.v:77 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Passed 'top.t.cover_simple_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 -Passed 'top.t.cover_observed_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 -Passed 'top.t.cover_final_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Passed 'top.t.cover_simple_immediate_stmt_77' at t/t_assert_ctl_arg.v:77 +Passed 'top.t.cover_observed_deferred_immediate_stmt_77' at t/t_assert_ctl_arg.v:77 +Passed 'top.t.cover_final_deferred_immediate_stmt_77' at t/t_assert_ctl_arg.v:77 ========== -Running all asserts at: t/t_assert_ctl_arg.v:80 +Running all asserts at: t/t_assert_ctl_arg.v:79 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:80 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:80 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:80 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:80 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:80 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:80 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:80 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:80 -Passed 'top.t.cover_simple_immediate_stmt_80' at t/t_assert_ctl_arg.v:80 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:79 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:79 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:79 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:79 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:79 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:79 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:79 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:79 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:79 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:79 +Passed 'top.t.cover_simple_immediate_stmt_79' at t/t_assert_ctl_arg.v:79 ========== -Running all asserts at: t/t_assert_ctl_arg.v:82 +Running all asserts at: t/t_assert_ctl_arg.v:81 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:82 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:82 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:82 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:82 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:82 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:82 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:82 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:82 -Passed 'top.t.cover_simple_immediate_stmt_82' at t/t_assert_ctl_arg.v:82 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:81 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:81 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:81 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:81 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:81 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:81 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:81 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:81 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:81 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:81 +Passed 'top.t.cover_simple_immediate_stmt_81' at t/t_assert_ctl_arg.v:81 ========== -Running all asserts at: t/t_assert_ctl_arg.v:84 +Running all asserts at: t/t_assert_ctl_arg.v:83 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:84 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:84 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:84 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:84 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:84 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:84 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:83 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:83 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:83 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:83 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:83 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:83 ========== -Running all asserts at: t/t_assert_ctl_arg.v:86 +Running all asserts at: t/t_assert_ctl_arg.v:85 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:86 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:86 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:86 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:86 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:86 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:86 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:86 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:86 -Passed 'top.t.cover_simple_immediate_stmt_86' at t/t_assert_ctl_arg.v:86 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:85 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:85 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:85 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:85 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:85 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:85 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:85 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:85 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:85 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:85 +Passed 'top.t.cover_simple_immediate_stmt_85' at t/t_assert_ctl_arg.v:85 ========== -Running all asserts at: t/t_assert_ctl_arg.v:88 +Running all asserts at: t/t_assert_ctl_arg.v:87 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:88 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:88 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:88 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:88 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:88 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:88 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:87 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:87 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:87 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:87 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:87 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:87 ========== -Running all asserts at: t/t_assert_ctl_arg.v:90 +Running all asserts at: t/t_assert_ctl_arg.v:89 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Passed 'top.t.cover_simple_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 -Passed 'top.t.cover_observed_deferred_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 -Passed 'top.t.cover_final_deferred_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Passed 'top.t.cover_simple_immediate_stmt_89' at t/t_assert_ctl_arg.v:89 +Passed 'top.t.cover_observed_deferred_immediate_stmt_89' at t/t_assert_ctl_arg.v:89 +Passed 'top.t.cover_final_deferred_immediate_stmt_89' at t/t_assert_ctl_arg.v:89 ========== -Running all asserts at: t/t_assert_ctl_arg.v:92 +Running all asserts at: t/t_assert_ctl_arg.v:91 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:92 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:92 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:92 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:92 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:92 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:92 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:91 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:91 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:91 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:91 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:91 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:91 ========== -Running all asserts at: t/t_assert_ctl_arg.v:97 +Running all asserts at: t/t_assert_ctl_arg.v:96 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:97 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:97 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:97 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:97 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:97 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:97 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:97 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:97 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:97 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:96 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:96 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:96 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:96 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:96 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:96 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:96 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:96 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:96 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:96 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:96 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:96 ========== -Running all asserts at: t/t_assert_ctl_arg.v:100 +Running all asserts at: t/t_assert_ctl_arg.v:99 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:100 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:100 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:100 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:100 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:100 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:100 -Passed 'top.t.cover_simple_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 -Passed 'top.t.cover_observed_deferred_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 -Passed 'top.t.cover_final_deferred_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:99 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:99 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:99 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:99 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:99 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:99 +Passed 'top.t.cover_simple_immediate_stmt_99' at t/t_assert_ctl_arg.v:99 +Passed 'top.t.cover_observed_deferred_immediate_stmt_99' at t/t_assert_ctl_arg.v:99 +Passed 'top.t.cover_final_deferred_immediate_stmt_99' at t/t_assert_ctl_arg.v:99 ========== -Running all asserts at: t/t_assert_ctl_arg.v:103 +Running all asserts at: t/t_assert_ctl_arg.v:102 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:103 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:103 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:103 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:103 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:103 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:103 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:103 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:103 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:103 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:102 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:102 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:102 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:102 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:102 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:102 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:102 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:102 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:102 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:102 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:102 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:102 ========== -Running all asserts at: t/t_assert_ctl_arg.v:106 +Running all asserts at: t/t_assert_ctl_arg.v:105 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:106 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:106 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:106 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:106 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:106 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:106 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:106 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:106 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:106 -Passed 'top.t.cover_simple_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 -Passed 'top.t.cover_observed_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 -Passed 'top.t.cover_final_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:105 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:105 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:105 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:105 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:105 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:105 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:105 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:105 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:105 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:105 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:105 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:105 +Passed 'top.t.cover_simple_immediate_stmt_105' at t/t_assert_ctl_arg.v:105 +Passed 'top.t.cover_observed_deferred_immediate_stmt_105' at t/t_assert_ctl_arg.v:105 +Passed 'top.t.cover_final_deferred_immediate_stmt_105' at t/t_assert_ctl_arg.v:105 ========== -Running all asserts at: t/t_assert_ctl_arg.v:108 +Running all asserts at: t/t_assert_ctl_arg.v:107 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Passed 'top.t.cover_simple_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 -Passed 'top.t.cover_observed_deferred_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 -Passed 'top.t.cover_final_deferred_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Passed 'top.t.cover_simple_immediate_stmt_107' at t/t_assert_ctl_arg.v:107 +Passed 'top.t.cover_observed_deferred_immediate_stmt_107' at t/t_assert_ctl_arg.v:107 +Passed 'top.t.cover_final_deferred_immediate_stmt_107' at t/t_assert_ctl_arg.v:107 ========== -Running all asserts at: t/t_assert_ctl_arg.v:110 +Running all asserts at: t/t_assert_ctl_arg.v:109 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:110 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:110 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:110 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:110 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:110 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:110 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:109 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:109 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:109 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:109 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:109 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:109 ========== -Running all asserts at: t/t_assert_ctl_arg.v:112 +Running all asserts at: t/t_assert_ctl_arg.v:111 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:112 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:112 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:112 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:112 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:112 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:112 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:112 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:112 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:112 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:112 -Passed 'top.t.cover_simple_immediate_stmt_112' at t/t_assert_ctl_arg.v:112 -Passed 'top.t.cover_final_deferred_immediate_stmt_112' at t/t_assert_ctl_arg.v:112 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:111 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:111 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:111 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:111 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:111 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:111 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:111 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:111 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:111 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:111 +Passed 'top.t.cover_simple_immediate_stmt_111' at t/t_assert_ctl_arg.v:111 +Passed 'top.t.cover_final_deferred_immediate_stmt_111' at t/t_assert_ctl_arg.v:111 Disabling concurrent asserts, time: 10 Enabling concurrent asserts, time: 20 *-* All Finished *-* -[20] %Error: t_assert_ctl_arg.v:182: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed. -Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:183 -Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:185 -[20] %Error: t_assert_ctl_arg.v:187: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed. -Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:188 -Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:190 +[20] %Error: t_assert_ctl_arg.v:181: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed. +Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:182 +Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:184 +[20] %Error: t_assert_ctl_arg.v:186: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed. +Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:187 +Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:189 diff --git a/test_regress/t/t_assert_ctl_arg.v b/test_regress/t/t_assert_ctl_arg.v index 5f11b2889..db8814fd5 100644 --- a/test_regress/t/t_assert_ctl_arg.v +++ b/test_regress/t/t_assert_ctl_arg.v @@ -5,190 +5,189 @@ // SPDX-License-Identifier: CC0-1.0 `define DISPLAY_PASS(file, line) \ - $display("Passed '%m' at %s:%g", file, line) + $display("Passed '%m' at %s:%g", file, line) `define DISPLAY_FAIL(file, line) \ - $display("Failed '%m' at %s:%g", file, line) + $display("Failed '%m' at %s:%g", file, line) `define RUN_ALL_ASSERTS \ - $display("==========\nRunning all asserts at: %s:%g\n==========", `__FILE__, `__LINE__); \ - run_all_asserts(`__FILE__, `__LINE__); \ - cover_simple_immediate_`__LINE__: cover(1); \ - cover_simple_immediate_stmt_`__LINE__: cover(1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ - cover_observed_deferred_immediate_`__LINE__: cover #0 (1); \ - cover_observed_deferred_immediate_stmt_`__LINE__: cover #0 (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ - cover_final_deferred_immediate_`__LINE__: cover final (1); \ - cover_final_deferred_immediate_stmt_`__LINE__: cover final (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ + $display("==========\nRunning all asserts at: %s:%g\n==========", `__FILE__, `__LINE__); \ + run_all_asserts(`__FILE__, `__LINE__); \ + cover_simple_immediate_`__LINE__: cover(1); \ + cover_simple_immediate_stmt_`__LINE__: cover(1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ + cover_observed_deferred_immediate_`__LINE__: cover #0 (1); \ + cover_observed_deferred_immediate_stmt_`__LINE__: cover #0 (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ + cover_final_deferred_immediate_`__LINE__: cover final (1); \ + cover_final_deferred_immediate_stmt_`__LINE__: cover final (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ -module t (/*AUTOARG*/ - clk - ); - input clk; +module t ( + input clk +); - let On = 3; - let Off = 4; - let Kill = 5; + let On = 3; + let Off = 4; + let Kill = 5; - let CONCURRENT = 1; - let SIMPLE_IMMEDIATE = 2; - let OBSERVED_DEFERRED_IMMEDIATE = 4; - let FINAL_DEFERRED_IMMEDIATE = 8; + let CONCURRENT = 1; + let SIMPLE_IMMEDIATE = 2; + let OBSERVED_DEFERRED_IMMEDIATE = 4; + let FINAL_DEFERRED_IMMEDIATE = 8; - let ALL_TYPES = CONCURRENT|SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE; + let ALL_TYPES = CONCURRENT|SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE; - let ASSERT = 1; - let COVER = 2; - let ASSUME = 4; + let ASSERT = 1; + let COVER = 2; + let ASSUME = 4; - concurrent concurrent(.clk(clk)); + concurrent concurrent(.clk(clk)); - initial begin - // simple immediate - $assertcontrol(Off, ALL_TYPES); - $assertcontrol(On, SIMPLE_IMMEDIATE); - `RUN_ALL_ASSERTS - $assertcontrol(Off, SIMPLE_IMMEDIATE); - `RUN_ALL_ASSERTS + initial begin + // simple immediate + $assertcontrol(Off, ALL_TYPES); + $assertcontrol(On, SIMPLE_IMMEDIATE); + `RUN_ALL_ASSERTS + $assertcontrol(Off, SIMPLE_IMMEDIATE); + `RUN_ALL_ASSERTS - // observed deferred immediate - $assertcontrol(Off, ALL_TYPES); - $assertcontrol(On, OBSERVED_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS - $assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS + // observed deferred immediate + $assertcontrol(Off, ALL_TYPES); + $assertcontrol(On, OBSERVED_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS + $assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS - // final deferred immediate - $assertcontrol(Off, ALL_TYPES); - $assertcontrol(On, FINAL_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS - $assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS + // final deferred immediate + $assertcontrol(Off, ALL_TYPES); + $assertcontrol(On, FINAL_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS + $assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS - // on, off, kill test - $assertoff; - `RUN_ALL_ASSERTS; - $asserton; - `RUN_ALL_ASSERTS; - $assertkill; - `RUN_ALL_ASSERTS; + // on, off, kill test + $assertoff; + `RUN_ALL_ASSERTS; + $asserton; + `RUN_ALL_ASSERTS; + $assertkill; + `RUN_ALL_ASSERTS; - $assertcontrol(On, SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(On, FINAL_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, SIMPLE_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(On, SIMPLE_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, ALL_TYPES); - `RUN_ALL_ASSERTS; - $assertcontrol(On, ALL_TYPES); - `RUN_ALL_ASSERTS; - $assertcontrol(Kill, ALL_TYPES); - `RUN_ALL_ASSERTS; + $assertcontrol(On, SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(On, FINAL_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, SIMPLE_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(On, SIMPLE_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, ALL_TYPES); + `RUN_ALL_ASSERTS; + $assertcontrol(On, ALL_TYPES); + `RUN_ALL_ASSERTS; + $assertcontrol(Kill, ALL_TYPES); + `RUN_ALL_ASSERTS; - // directive_type test - $assertoff; - $assertcontrol(On, ALL_TYPES, ASSERT); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, ALL_TYPES, ASSERT); - $assertcontrol(On, ALL_TYPES, COVER); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, ALL_TYPES, COVER); - $assertcontrol(On, ALL_TYPES, ASSUME); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, ALL_TYPES, ASSUME); - $assertcontrol(On, ALL_TYPES, ASSERT|COVER); - `RUN_ALL_ASSERTS; - $assertcontrol(On, ALL_TYPES, ASSUME); - `RUN_ALL_ASSERTS; - $assertoff; - `RUN_ALL_ASSERTS; - $assertcontrol(On, SIMPLE_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE, COVER|ASSUME); - `RUN_ALL_ASSERTS; - $assertoff; + // directive_type test + $assertoff; + $assertcontrol(On, ALL_TYPES, ASSERT); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, ALL_TYPES, ASSERT); + $assertcontrol(On, ALL_TYPES, COVER); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, ALL_TYPES, COVER); + $assertcontrol(On, ALL_TYPES, ASSUME); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, ALL_TYPES, ASSUME); + $assertcontrol(On, ALL_TYPES, ASSERT|COVER); + `RUN_ALL_ASSERTS; + $assertcontrol(On, ALL_TYPES, ASSUME); + `RUN_ALL_ASSERTS; + $assertoff; + `RUN_ALL_ASSERTS; + $assertcontrol(On, SIMPLE_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE, COVER|ASSUME); + `RUN_ALL_ASSERTS; + $assertoff; - // concurrent test - #10; - $display("Disabling concurrent asserts, time: %g", $time); - $assertcontrol(On, ALL_TYPES); - $assertcontrol(Off, CONCURRENT); - #10; - $display("Enabling concurrent asserts, time: %g", $time); - $assertcontrol(On, CONCURRENT); + // concurrent test + #10; + $display("Disabling concurrent asserts, time: %g", $time); + $assertcontrol(On, ALL_TYPES); + $assertcontrol(Off, CONCURRENT); + #10; + $display("Enabling concurrent asserts, time: %g", $time); + $assertcontrol(On, CONCURRENT); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule task run_all_asserts(string file, integer line); - run_simple_immediate(file, line); - run_observed_deferred_immediate(file, line); - run_final_deferred_immediate(file, line); + run_simple_immediate(file, line); + run_observed_deferred_immediate(file, line); + run_final_deferred_immediate(file, line); endtask task run_simple_immediate(string file, integer line); - $display("Testing assert_simple_immediate at %s:%g", file, line); - assert_simple_immediate: assert(0); - assert_simple_immediate_else: assert(0) else `DISPLAY_FAIL(file, line); - assert_simple_immediate_stmt: assert(0) `DISPLAY_PASS(file, line); - assert_simple_immediate_stmt_else: assert(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assert_simple_immediate at %s:%g", file, line); + assert_simple_immediate: assert(0); + assert_simple_immediate_else: assert(0) else `DISPLAY_FAIL(file, line); + assert_simple_immediate_stmt: assert(0) `DISPLAY_PASS(file, line); + assert_simple_immediate_stmt_else: assert(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); - $display("Testing assume_simple_immediate at %s:%g", file, line); - assume_simple_immediate: assume(0); - assume_simple_immediate_else: assume(0) else `DISPLAY_FAIL(file, line); - assume_simple_immediate_stmt: assume(0) `DISPLAY_PASS(file, line); - assume_simple_immediate_stmt_else: assume(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assume_simple_immediate at %s:%g", file, line); + assume_simple_immediate: assume(0); + assume_simple_immediate_else: assume(0) else `DISPLAY_FAIL(file, line); + assume_simple_immediate_stmt: assume(0) `DISPLAY_PASS(file, line); + assume_simple_immediate_stmt_else: assume(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); endtask task run_observed_deferred_immediate(string file, integer line); - $display("Testing assert_observed_deferred_immediate at %s:%g", file, line); - assert_observed_deferred_immediate: assert #0 (0); - assert_observed_deferred_immediate_else: assert #0 (0) else `DISPLAY_FAIL(file, line); - assert_observed_deferred_immediate_stmt: assert #0 (0) `DISPLAY_PASS(file, line); - assert_observed_deferred_immediate_stmt_else: assert #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assert_observed_deferred_immediate at %s:%g", file, line); + assert_observed_deferred_immediate: assert #0 (0); + assert_observed_deferred_immediate_else: assert #0 (0) else `DISPLAY_FAIL(file, line); + assert_observed_deferred_immediate_stmt: assert #0 (0) `DISPLAY_PASS(file, line); + assert_observed_deferred_immediate_stmt_else: assert #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); - $display("Testing assume_observed_deferred_immediate at %s:%g", file, line); - assume_observed_deferred_immediate: assume #0 (0); - assume_observed_deferred_immediate_else: assume #0 (0) else `DISPLAY_FAIL(file, line); - assume_observed_deferred_immediate_stmt: assume #0 (0) `DISPLAY_PASS(file, line); - assume_observed_deferred_immediate_stmt_else: assume #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assume_observed_deferred_immediate at %s:%g", file, line); + assume_observed_deferred_immediate: assume #0 (0); + assume_observed_deferred_immediate_else: assume #0 (0) else `DISPLAY_FAIL(file, line); + assume_observed_deferred_immediate_stmt: assume #0 (0) `DISPLAY_PASS(file, line); + assume_observed_deferred_immediate_stmt_else: assume #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); endtask task run_final_deferred_immediate(string file, integer line); - $display("Testing assert_final_deferred_immediate at %s:%g", file, line); - assert_final_deferred_immediate: assert final (0); - assert_final_deferred_immediate_else: assert final (0) else `DISPLAY_FAIL(file, line); - assert_final_deferred_immediate_stmt: assert final (0) `DISPLAY_PASS(file, line); - assert_final_deferred_immediate_stmt_else: assert final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assert_final_deferred_immediate at %s:%g", file, line); + assert_final_deferred_immediate: assert final (0); + assert_final_deferred_immediate_else: assert final (0) else `DISPLAY_FAIL(file, line); + assert_final_deferred_immediate_stmt: assert final (0) `DISPLAY_PASS(file, line); + assert_final_deferred_immediate_stmt_else: assert final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); - $display("Testing assume_final_deferred_immediate at %s:%g", file, line); - assume_final_deferred_immediate: assume final (0); - assume_final_deferred_immediate_else: assume final (0) else `DISPLAY_FAIL(file, line); - assume_final_deferred_immediate_stmt: assume final (0) `DISPLAY_PASS(file, line); - assume_final_deferred_immediate_stmt_else: assume final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assume_final_deferred_immediate at %s:%g", file, line); + assume_final_deferred_immediate: assume final (0); + assume_final_deferred_immediate_else: assume final (0) else `DISPLAY_FAIL(file, line); + assume_final_deferred_immediate_stmt: assume final (0) `DISPLAY_PASS(file, line); + assume_final_deferred_immediate_stmt_else: assume final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); endtask module concurrent(input clk); - property prop(); - @(posedge clk) 0 - endproperty + property prop(); + @(posedge clk) 0 + endproperty - assert_concurrent: assert property (prop); - assert_concurrent_else: assert property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__); - assert_concurrent_stmt: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); - assert_concurrent_stmt_else: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__); + assert_concurrent: assert property (prop); + assert_concurrent_else: assert property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__); + assert_concurrent_stmt: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); + assert_concurrent_stmt_else: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__); - assume_concurrent: assume property(prop); - assume_concurrent_else: assume property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__); - assume_concurrent_stmt: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); - assume_concurrent_stmt_else: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__); + assume_concurrent: assume property(prop); + assume_concurrent_else: assume property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__); + assume_concurrent_stmt: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); + assume_concurrent_stmt_else: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__); - cover_concurrent: cover property(prop); - cover_concurrent_stmt: cover property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); + cover_concurrent: cover property(prop); + cover_concurrent_stmt: cover property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); endmodule diff --git a/test_regress/t/t_assert_ctl_arg_unsup.out b/test_regress/t/t_assert_ctl_arg_unsup.out index 863f8394b..c9bad92c3 100644 --- a/test_regress/t/t_assert_ctl_arg_unsup.out +++ b/test_regress/t/t_assert_ctl_arg_unsup.out @@ -1,18 +1,18 @@ -%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:15:7: Unsupported: assert control assertion_type +%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:15:5: Unsupported: assert control assertion_type : ... note: In instance 't' - 15 | $assertcontrol(OFF, EXPECT); - | ^~~~~~~~~~~~~~ + 15 | $assertcontrol(OFF, EXPECT); + | ^~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:16:7: Unsupported: assert control assertion_type +%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:16:5: Unsupported: assert control assertion_type : ... note: In instance 't' - 16 | $assertcontrol(OFF, UNIQUE); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:17:7: Unsupported: assert control assertion_type + 16 | $assertcontrol(OFF, UNIQUE); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:17:5: Unsupported: assert control assertion_type : ... note: In instance 't' - 17 | $assertcontrol(OFF, UNIQUE0); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:18:7: Unsupported: assert control assertion_type + 17 | $assertcontrol(OFF, UNIQUE0); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:18:5: Unsupported: assert control assertion_type : ... note: In instance 't' - 18 | $assertcontrol(OFF, PRIORITY); - | ^~~~~~~~~~~~~~ + 18 | $assertcontrol(OFF, PRIORITY); + | ^~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_ctl_arg_unsup.v b/test_regress/t/t_assert_ctl_arg_unsup.v index e998de28e..b041652f2 100644 --- a/test_regress/t/t_assert_ctl_arg_unsup.v +++ b/test_regress/t/t_assert_ctl_arg_unsup.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module t; - let OFF = 4; - let EXPECT = 16; - let UNIQUE = 32; - let UNIQUE0 = 64; - let PRIORITY = 128; + let OFF = 4; + let EXPECT = 16; + let UNIQUE = 32; + let UNIQUE0 = 64; + let PRIORITY = 128; - initial begin - $assertcontrol(OFF, EXPECT); - $assertcontrol(OFF, UNIQUE); - $assertcontrol(OFF, UNIQUE0); - $assertcontrol(OFF, PRIORITY); - end + initial begin + $assertcontrol(OFF, EXPECT); + $assertcontrol(OFF, UNIQUE); + $assertcontrol(OFF, UNIQUE0); + $assertcontrol(OFF, PRIORITY); + end endmodule diff --git a/test_regress/t/t_assert_ctl_concurrent.v b/test_regress/t/t_assert_ctl_concurrent.v index 3cc919d92..3cdda2bc1 100644 --- a/test_regress/t/t_assert_ctl_concurrent.v +++ b/test_regress/t/t_assert_ctl_concurrent.v @@ -6,39 +6,33 @@ module t; - bit clock = 1'b0; - bit reset = 1'b0; + bit clock = 1'b0; + bit reset = 1'b0; - initial begin - $assertkill; + initial begin + $assertkill; - #10 + #10 reset = 1'b1; + $display("%t: deassert reset %d", $time, reset); - reset = 1'b1; - $display("%t: deassert reset %d", $time, reset); + #40 $asserton; - #40 + reset = 1'b0; + $display("%t: deassert reset %d", $time, reset); - $asserton; + #200 $display("%t: finish", $time); + $write("*-* All Finished *-*\n"); + $finish; - reset = 1'b0; - $display("%t: deassert reset %d", $time, reset); + end - #200 + always #10 clock = ~clock; + reg r = 1'b0; - $display("%t: finish", $time); - $write("*-* All Finished *-*\n"); - $finish; + always @(posedge clock) if (reset) r <= 1'b1; - end - - always #10 clock = ~clock; - reg r = 1'b0; - - always @(posedge clock) if (reset) r <= 1'b1; - - assert_test: - assert property (@(posedge clock) (reset | r)) - else $error("%t: assertion triggered", $time); + assert_test : + assert property (@(posedge clock) (reset | r)) + else $error("%t: assertion triggered", $time); endmodule diff --git a/test_regress/t/t_assert_ctl_immediate.out b/test_regress/t/t_assert_ctl_immediate.out index bd71f8bb5..a10fd21c4 100644 --- a/test_regress/t/t_assert_ctl_immediate.out +++ b/test_regress/t/t_assert_ctl_immediate.out @@ -1,6 +1,6 @@ -[0] %Error: t_assert_ctl_immediate.v:47: Assertion failed in top.t.module_with_assertctl: 'assert' failed. --Info: t/t_assert_ctl_immediate.v:47: Verilog $stop, ignored due to +verilator+error+limit -[0] %Error: t_assert_ctl_immediate.v:53: Assertion failed in top.t.module_with_assertctl: 'assert' failed. -[0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. -[0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. +[0] %Error: t_assert_ctl_immediate.v:51: Assertion failed in top.t.module_with_assertctl: 'assert' failed. +-Info: t/t_assert_ctl_immediate.v:51: Verilog $stop, ignored due to +verilator+error+limit +[0] %Error: t_assert_ctl_immediate.v:57: Assertion failed in top.t.module_with_assertctl: 'assert' failed. +[0] %Error: t_assert_ctl_immediate.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. +[0] %Error: t_assert_ctl_immediate.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. *-* All Finished *-* diff --git a/test_regress/t/t_assert_ctl_immediate.v b/test_regress/t/t_assert_ctl_immediate.v index 26d5a1e92..6c5848aaf 100644 --- a/test_regress/t/t_assert_ctl_immediate.v +++ b/test_regress/t/t_assert_ctl_immediate.v @@ -4,58 +4,62 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + module_with_assert module_with_assert (clk); + module_with_assertctl module_with_assertctl (clk); - module_with_assert module_with_assert(clk); - module_with_assertctl module_with_assertctl(clk); + always @(posedge clk) begin + assert (0); + end - always @ (posedge clk) begin - assert(0); - end - - always @ (negedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(negedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module module_with_assert(input clk); - always @(posedge clk) assert(0); +module module_with_assert ( + input clk +); + always @(posedge clk) assert (0); endmodule -module module_with_assertctl(input clk); - function void assert_off; begin +module module_with_assertctl ( + input clk +); + function void assert_off; + begin $assertoff; - end - endfunction - function void assert_on; begin + end + endfunction + function void assert_on; + begin $asserton; - end - endfunction - function void f_assert; begin - assert(0); - end - endfunction + end + endfunction + function void f_assert; + begin + assert (0); + end + endfunction - initial begin - assert_on(); - assert(0); - assert_off(); - assert_off(); - assert(0); - assert_on(); - assert_on(); - assert(0); + initial begin + assert_on(); + assert (0); + assert_off(); + assert_off(); + assert (0); + assert_on(); + assert_on(); + assert (0); - f_assert(); - f_assert(); - assert_off(); - f_assert(); - f_assert(); - end + f_assert(); + f_assert(); + assert_off(); + f_assert(); + f_assert(); + end endmodule diff --git a/test_regress/t/t_assert_ctl_unsup.out b/test_regress/t/t_assert_ctl_unsup.out index 4aae777cb..26e32ff0d 100644 --- a/test_regress/t/t_assert_ctl_unsup.out +++ b/test_regress/t/t_assert_ctl_unsup.out @@ -1,123 +1,123 @@ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:7: Unsupported: non-constant assert assertion-type expression +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:5: Unsupported: non-constant assert assertion-type expression : ... note: In instance 't.unsupported_ctl_type' - 25 | $assertcontrol(Lock, a); - | ^~~~~~~~~~~~~~ + 25 | $assertcontrol(Lock, a); + | ^~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:27:7: Unsupported: $assertcontrol control_type '2' - 27 | $assertcontrol(Unlock); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:29:7: Unsupported: $assertcontrol control_type '6' - 29 | $assertcontrol(PassOn); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:30:7: Unsupported: assert control assertion_type +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:27:5: Unsupported: $assertcontrol control_type '2' + 27 | $assertcontrol(Unlock); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:29:5: Unsupported: $assertcontrol control_type '6' + 29 | $assertcontrol(PassOn); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:30:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 30 | $assertpasson; - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:31:7: Unsupported: assert control assertion_type + 30 | $assertpasson; + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:31:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 31 | $assertpasson(a); - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:7: Unsupported: assert control assertion_type + 31 | $assertpasson(a); + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 32 | $assertpasson(a, t); - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:34:7: Unsupported: $assertcontrol control_type '7' - 34 | $assertcontrol(PassOff); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:35:7: Unsupported: assert control assertion_type + 32 | $assertpasson(a, t); + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:34:5: Unsupported: $assertcontrol control_type '7' + 34 | $assertcontrol(PassOff); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:35:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 35 | $assertpassoff; - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:36:7: Unsupported: assert control assertion_type + 35 | $assertpassoff; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:36:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 36 | $assertpassoff(a); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:37:7: Unsupported: assert control assertion_type + 36 | $assertpassoff(a); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:37:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 37 | $assertpassoff(a, t); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:39:7: Unsupported: $assertcontrol control_type '8' - 39 | $assertcontrol(FailOn); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:40:7: Unsupported: assert control assertion_type + 37 | $assertpassoff(a, t); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:39:5: Unsupported: $assertcontrol control_type '8' + 39 | $assertcontrol(FailOn); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:40:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 40 | $assertfailon; - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:41:7: Unsupported: assert control assertion_type + 40 | $assertfailon; + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:41:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 41 | $assertfailon(a); - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:42:7: Unsupported: assert control assertion_type + 41 | $assertfailon(a); + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:42:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 42 | $assertfailon(a, t); - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:44:7: Unsupported: $assertcontrol control_type '9' - 44 | $assertcontrol(FailOff); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:45:7: Unsupported: assert control assertion_type + 42 | $assertfailon(a, t); + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:44:5: Unsupported: $assertcontrol control_type '9' + 44 | $assertcontrol(FailOff); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:45:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 45 | $assertfailoff; - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:46:7: Unsupported: assert control assertion_type + 45 | $assertfailoff; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:46:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 46 | $assertfailoff(a); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:47:7: Unsupported: assert control assertion_type + 46 | $assertfailoff(a); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:47:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 47 | $assertfailoff(a, t); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:49:7: Unsupported: $assertcontrol control_type '10' - 49 | $assertcontrol(NonvacuousOn); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:50:7: Unsupported: assert control assertion_type + 47 | $assertfailoff(a, t); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:49:5: Unsupported: $assertcontrol control_type '10' + 49 | $assertcontrol(NonvacuousOn); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:50:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 50 | $assertnonvacuouson; - | ^~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:51:7: Unsupported: assert control assertion_type + 50 | $assertnonvacuouson; + | ^~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:51:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 51 | $assertnonvacuouson(a); - | ^~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:52:7: Unsupported: assert control assertion_type + 51 | $assertnonvacuouson(a); + | ^~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:52:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 52 | $assertnonvacuouson(a, t); - | ^~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:54:7: Unsupported: $assertcontrol control_type '11' - 54 | $assertcontrol(VacuousOff); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:55:7: Unsupported: assert control assertion_type + 52 | $assertnonvacuouson(a, t); + | ^~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:54:5: Unsupported: $assertcontrol control_type '11' + 54 | $assertcontrol(VacuousOff); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:55:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 55 | $assertvacuousoff; - | ^~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:56:7: Unsupported: assert control assertion_type + 55 | $assertvacuousoff; + | ^~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:56:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 56 | $assertvacuousoff(a); - | ^~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:57:7: Unsupported: assert control assertion_type + 56 | $assertvacuousoff(a); + | ^~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:57:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 57 | $assertvacuousoff(a, t); - | ^~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:64:7: Unsupported: non-const assert control type expression + 57 | $assertvacuousoff(a, t); + | ^~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:64:5: Unsupported: non-const assert control type expression : ... note: In instance 't.unsupported_ctl_type_expr' - 64 | $assertcontrol(ctl_type); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:93:10: Unsupported: assertcontrols in classes or interfaces - : ... note: In instance 't.assert_class' - 93 | $asserton; - | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:99:10: Unsupported: assertcontrols in classes or interfaces - : ... note: In instance 't.assert_class' - 99 | $assertoff; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:172:7: Unsupported: assertcontrols in classes or interfaces - : ... note: In instance 't.assert_iface' - 172 | $assertoff; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:138:7: Unsupported: assertcontrols in classes or interfaces - : ... note: In instance 't.assert_iface_class' - 138 | $assertoff; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:145:7: Unsupported: assertcontrols in classes or interfaces - : ... note: In instance 't.assert_iface_class' - 145 | $asserton; + 64 | $assertcontrol(ctl_type); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:93:7: Unsupported: assertcontrols in classes or interfaces + : ... note: In instance 't.assert_class' + 93 | $asserton; | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:99:7: Unsupported: assertcontrols in classes or interfaces + : ... note: In instance 't.assert_class' + 99 | $assertoff; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:172:5: Unsupported: assertcontrols in classes or interfaces + : ... note: In instance 't.assert_iface' + 172 | $assertoff; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:138:5: Unsupported: assertcontrols in classes or interfaces + : ... note: In instance 't.assert_iface_class' + 138 | $assertoff; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:145:5: Unsupported: assertcontrols in classes or interfaces + : ... note: In instance 't.assert_iface_class' + 145 | $asserton; + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_ctl_unsup.v b/test_regress/t/t_assert_ctl_unsup.v index 7ff4eb013..98afcad10 100644 --- a/test_regress/t/t_assert_ctl_unsup.v +++ b/test_regress/t/t_assert_ctl_unsup.v @@ -5,181 +5,181 @@ // SPDX-License-Identifier: CC0-1.0 module t(input logic clk); - unsupported_ctl_type unsupported_ctl_type(clk ? 1 : 2); - unsupported_ctl_type_expr unsupported_ctl_type_expr(); - assert_class assert_class(); - assert_iface assert_iface(); - assert_iface_class assert_iface_class(); + unsupported_ctl_type unsupported_ctl_type(clk ? 1 : 2); + unsupported_ctl_type_expr unsupported_ctl_type_expr(); + assert_class assert_class(); + assert_iface assert_iface(); + assert_iface_class assert_iface_class(); endmodule module unsupported_ctl_type(input int a); - initial begin - let Lock = 1; - let Unlock = 2; - let PassOn = 6; - let PassOff = 7; - let FailOn = 8; - let FailOff = 9; - let NonvacuousOn = 10; - let VacuousOff = 11; - $assertcontrol(Lock, a); + initial begin + let Lock = 1; + let Unlock = 2; + let PassOn = 6; + let PassOff = 7; + let FailOn = 8; + let FailOff = 9; + let NonvacuousOn = 10; + let VacuousOff = 11; + $assertcontrol(Lock, a); - $assertcontrol(Unlock); + $assertcontrol(Unlock); - $assertcontrol(PassOn); - $assertpasson; - $assertpasson(a); - $assertpasson(a, t); + $assertcontrol(PassOn); + $assertpasson; + $assertpasson(a); + $assertpasson(a, t); - $assertcontrol(PassOff); - $assertpassoff; - $assertpassoff(a); - $assertpassoff(a, t); + $assertcontrol(PassOff); + $assertpassoff; + $assertpassoff(a); + $assertpassoff(a, t); - $assertcontrol(FailOn); - $assertfailon; - $assertfailon(a); - $assertfailon(a, t); + $assertcontrol(FailOn); + $assertfailon; + $assertfailon(a); + $assertfailon(a, t); - $assertcontrol(FailOff); - $assertfailoff; - $assertfailoff(a); - $assertfailoff(a, t); + $assertcontrol(FailOff); + $assertfailoff; + $assertfailoff(a); + $assertfailoff(a, t); - $assertcontrol(NonvacuousOn); - $assertnonvacuouson; - $assertnonvacuouson(a); - $assertnonvacuouson(a, t); + $assertcontrol(NonvacuousOn); + $assertnonvacuouson; + $assertnonvacuouson(a); + $assertnonvacuouson(a, t); - $assertcontrol(VacuousOff); - $assertvacuousoff; - $assertvacuousoff(a); - $assertvacuousoff(a, t); - end + $assertcontrol(VacuousOff); + $assertvacuousoff; + $assertvacuousoff(a); + $assertvacuousoff(a, t); + end endmodule module unsupported_ctl_type_expr; - int ctl_type = 1; - initial begin - $assertcontrol(ctl_type); - end + int ctl_type = 1; + initial begin + $assertcontrol(ctl_type); + end endmodule module assert_class; - virtual class AssertCtl; - pure virtual function void virtual_assert_ctl(); - endclass + virtual class AssertCtl; + pure virtual function void virtual_assert_ctl(); + endclass - class AssertCls; - static function void static_function(); - assert(0); - endfunction - static task static_task(); - assert(0); - endtask - function void assert_function(); - assert(0); - endfunction - task assert_task(); - assert(0); - endtask - virtual function void virtual_assert(); - assert(0); - endfunction - endclass + class AssertCls; + static function void static_function(); + assert(0); + endfunction + static task static_task(); + assert(0); + endtask + function void assert_function(); + assert(0); + endfunction + task assert_task(); + assert(0); + endtask + virtual function void virtual_assert(); + assert(0); + endfunction + endclass - class AssertOn extends AssertCtl; - virtual function void virtual_assert_ctl(); - $asserton; - endfunction - endclass - - class AssertOff extends AssertCtl; - virtual function void virtual_assert_ctl(); - $assertoff; - endfunction - endclass - - AssertCls assertCls; - AssertOn assertOn; - AssertOff assertOff; - initial begin - $assertoff; - AssertCls::static_function(); - AssertCls::static_task(); + class AssertOn extends AssertCtl; + virtual function void virtual_assert_ctl(); $asserton; - AssertCls::static_function(); - AssertCls::static_task(); + endfunction + endclass - assertCls = new; - assertOn = new; - assertOff = new; + class AssertOff extends AssertCtl; + virtual function void virtual_assert_ctl(); + $assertoff; + endfunction + endclass - assertOff.virtual_assert_ctl(); - assertCls.assert_function(); - assertCls.assert_task(); - assertCls.virtual_assert(); + AssertCls assertCls; + AssertOn assertOn; + AssertOff assertOff; + initial begin + $assertoff; + AssertCls::static_function(); + AssertCls::static_task(); + $asserton; + AssertCls::static_function(); + AssertCls::static_task(); - assertOn.virtual_assert_ctl(); - assertCls.assert_function(); - assertCls.assert_task(); - assertCls.virtual_assert(); - assertOff.virtual_assert_ctl(); - assertCls.assert_function(); - end + assertCls = new; + assertOn = new; + assertOff = new; + + assertOff.virtual_assert_ctl(); + assertCls.assert_function(); + assertCls.assert_task(); + assertCls.virtual_assert(); + + assertOn.virtual_assert_ctl(); + assertCls.assert_function(); + assertCls.assert_task(); + assertCls.virtual_assert(); + assertOff.virtual_assert_ctl(); + assertCls.assert_function(); + end endmodule interface Iface; - function void assert_func(); - assert(0); - endfunction + function void assert_func(); + assert(0); + endfunction - function void assertoff_func(); - $assertoff; - endfunction + function void assertoff_func(); + $assertoff; + endfunction - initial begin - assertoff_func(); - assert(0); - assert_func(); - $asserton; - assert(0); - assert_func(); - end + initial begin + assertoff_func(); + assert(0); + assert_func(); + $asserton; + assert(0); + assert_func(); + end endinterface module assert_iface; - Iface iface(); - virtual Iface vIface = iface; - initial begin - vIface.assert_func(); - vIface.assertoff_func(); - vIface.assert_func(); + Iface iface(); + virtual Iface vIface = iface; + initial begin + vIface.assert_func(); + vIface.assertoff_func(); + vIface.assert_func(); - iface.assert_func(); - iface.assertoff_func(); - iface.assert_func(); - end + iface.assert_func(); + iface.assertoff_func(); + iface.assert_func(); + end endmodule interface class IfaceClass; - pure virtual function void assertoff_func(); - pure virtual function void assert_func(); + pure virtual function void assertoff_func(); + pure virtual function void assert_func(); endclass class IfaceClassImpl implements IfaceClass; - virtual function void assertoff_func(); - $assertoff; - endfunction - virtual function void assert_func(); - assert(0); - endfunction + virtual function void assertoff_func(); + $assertoff; + endfunction + virtual function void assert_func(); + assert(0); + endfunction endclass module assert_iface_class; - IfaceClassImpl ifaceClassImpl = new; - initial begin - ifaceClassImpl.assertoff_func(); - ifaceClassImpl.assert_func(); - end + IfaceClassImpl ifaceClassImpl = new; + initial begin + ifaceClassImpl.assertoff_func(); + ifaceClassImpl.assert_func(); + end endmodule diff --git a/test_regress/t/t_assert_disable_bad.out b/test_regress/t/t_assert_disable_bad.out index 66a373165..ae85a663f 100644 --- a/test_regress/t/t_assert_disable_bad.out +++ b/test_regress/t/t_assert_disable_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_assert_disable_bad.v:27:38: disable iff expression before property call and in its body is not legal +%Error: t/t_assert_disable_bad.v:25:37: disable iff expression before property call and in its body is not legal : ... note: In instance 't' - 27 | assert property (disable iff (val == 0) check(1, 1)); - | ^~ + 25 | assert property (disable iff (val == 0) check(1, 1)); + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_assert_disable_bad.v b/test_regress/t/t_assert_disable_bad.v index 4103e7b54..775ec72b8 100644 --- a/test_regress/t/t_assert_disable_bad.v +++ b/test_regress/t/t_assert_disable_bad.v @@ -4,25 +4,23 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic val = 0; + int cyc = 0; + logic val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - property check(int cyc_mod_2, logic expected); - @(posedge clk) disable iff (cyc == 0) cyc % 2 == cyc_mod_2 |=> val == expected; - endproperty + property check(int cyc_mod_2, logic expected); + @(posedge clk) disable iff (cyc == 0) cyc % 2 == cyc_mod_2 |=> val == expected; + endproperty - // Test should fail due to duplicated disable iff statements - // (IEEE 1800-2012 16.12.1). - assert property (disable iff (val == 0) check(1, 1)); + // Test should fail due to duplicated disable iff statements + // (IEEE 1800-2012 16.12.1). + assert property (disable iff (val == 0) check(1, 1)); endmodule diff --git a/test_regress/t/t_assert_disable_count.v b/test_regress/t/t_assert_disable_count.v index 54451f211..9411177d5 100644 --- a/test_regress/t/t_assert_disable_count.v +++ b/test_regress/t/t_assert_disable_count.v @@ -4,66 +4,69 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc; - int cyc; + Sub sub (); - Sub sub (); + default disable iff (cyc[0]); - default disable iff (cyc[0]); + int a_false; + always @(posedge clk iff !cyc[0]) begin + if (cyc < 4 || cyc > 9); + else a_false = a_false + 1; + end - int a_false; - always @(posedge clk iff !cyc[0]) begin - if (cyc < 4 || cyc > 9) ; - else a_false = a_false + 1; - end + int a0_false; + a0 : + assert property (@(posedge clk) disable iff (cyc[0]) (cyc < 4 || cyc > 9)) + else a0_false = a0_false + 1; - int a0_false; - a0: assert property (@(posedge clk) disable iff (cyc[0]) (cyc < 4 || cyc > 9)) - else a0_false = a0_false + 1; + int a1_false; + // Note that Verilator supports $inferred_disable in general expression locations + // This is a superset of what IEEE specifies + a1 : + assert property (@(posedge clk) disable iff ($inferred_disable) (cyc < 4 || cyc > 9)) + else a1_false = a1_false + 1; - int a1_false; - // Note that Verilator supports $inferred_disable in general expression locations - // This is a superset of what IEEE specifies - a1: assert property (@(posedge clk) disable iff ($inferred_disable) (cyc < 4 || cyc > 9)) - else a1_false = a1_false + 1; + int a2_false; + // Implicitly uses $inferred_disable + a2 : + assert property (@(posedge clk) (cyc < 4 || cyc > 9)) + else a2_false = a2_false + 1; - int a2_false; - // Implicitly uses $inferred_disable - a2: assert property (@(posedge clk) (cyc < 4 || cyc > 9)) - else a2_false = a2_false + 1; + int a3_false; + // A different disable iff expression + a3 : + assert property (@(posedge clk) disable iff (cyc == 5) (cyc < 4 || cyc > 9)) + else a3_false = a3_false + 1; - int a3_false; - // A different disable iff expression - a3: assert property (@(posedge clk) disable iff (cyc == 5) (cyc < 4 || cyc > 9)) - else a3_false = a3_false + 1; - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 20) begin - `checkd(a_false, 3); - `checkd(a0_false, a_false); - `checkd(a1_false, a_false); - `checkd(a2_false, a_false); - `checkd(a3_false, 5); - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + `checkd(a_false, 3); + `checkd(a0_false, a_false); + `checkd(a1_false, a_false); + `checkd(a2_false, a_false); + `checkd(a3_false, 5); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Sub; - initial begin - if ($inferred_disable !== 0) $stop; - end + initial begin + if ($inferred_disable !== 0) $stop; + end endmodule diff --git a/test_regress/t/t_assert_dup_bad.out b/test_regress/t/t_assert_dup_bad.out index 3bce26f7b..336c91ace 100644 --- a/test_regress/t/t_assert_dup_bad.out +++ b/test_regress/t/t_assert_dup_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_assert_dup_bad.v:17:4: Duplicate declaration of block: 'covlabel' - 17 | covlabel: - | ^~~~~~~~ - t/t_assert_dup_bad.v:15:4: ... Location of original declaration - 15 | covlabel: - | ^~~~~~~~ +%Error: t/t_assert_dup_bad.v:15:3: Duplicate declaration of block: 'covlabel' + 15 | covlabel : + | ^~~~~~~~ + t/t_assert_dup_bad.v:13:3: ... Location of original declaration + 13 | covlabel : + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_assert_dup_bad.v b/test_regress/t/t_assert_dup_bad.v index 250f7da9e..7be4d73ff 100644 --- a/test_regress/t/t_assert_dup_bad.v +++ b/test_regress/t/t_assert_dup_bad.v @@ -4,17 +4,15 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc = 0; + int cyc; - covlabel: - cover property (@(posedge clk) cyc==5); - covlabel: // Error: Duplicate block_identifier - cover property (@(posedge clk) cyc==5); + covlabel : + cover property (@(posedge clk) cyc == 5); + covlabel : // Error: Duplicate block_identifier + cover property (@(posedge clk) cyc == 5); endmodule diff --git a/test_regress/t/t_assert_elab.v b/test_regress/t/t_assert_elab.v index 516cbd220..5492abbbb 100644 --- a/test_regress/t/t_assert_elab.v +++ b/test_regress/t/t_assert_elab.v @@ -5,26 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 module t; - localparam STR = "string"; - function logic checkParameter(input logic [8:0] N); - $info("For %m, x is %d.", N); - if (N == 1) - return 0; - $fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work"); - endfunction + localparam STR = "string"; + function logic checkParameter(input logic [8:0] N); + $info("For %m, x is %d.", N); + if (N == 1) return 0; + $fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work"); + endfunction `ifdef FAILING_ASSERTIONS - localparam X = checkParameter(5); + localparam X = checkParameter(5); `else - localparam X = checkParameter(1); + localparam X = checkParameter(1); `endif - generate - $info("%m: In generate"); // Issue 6445 - endgenerate + generate + $info("%m: In generate"); // Issue 6445 + endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_iff.v b/test_regress/t/t_assert_iff.v index b56e72993..7a435fca8 100644 --- a/test_regress/t/t_assert_iff.v +++ b/test_regress/t/t_assert_iff.v @@ -4,54 +4,46 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - logic[3:0] enable; - int cyc = 0; +module t ( + input clk +); - Test test(.*); + logic [3:0] enable; + int cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - `ifdef FAIL1 enable[0] <= 1; `endif - enable[1] <= 1; - `ifdef FAIL2 enable[2] <= 1; `endif - enable[3] <= 1; - if (cyc != 0) begin - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + Test test (.*); + + always @(posedge clk) begin + cyc <= cyc + 1; +`ifdef FAIL1 + enable[0] <= 1; +`endif + enable[1] <= 1; +`ifdef FAIL2 + enable[2] <= 1; +`endif + enable[3] <= 1; + if (cyc != 0) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule -module Test( - input clk, - input[3:0] enable - ); +module Test ( + input clk, + input [3:0] enable +); - assert property ( - @(posedge clk iff enable[0]) - 0 - ) else $stop; + assert property (@(posedge clk iff enable[0]) 0) + else $stop; - assert property ( - @(posedge clk iff enable[1]) - 1 - ); + assert property (@(posedge clk iff enable[1]) 1); - cover property ( - @(posedge clk iff enable[2]) - 1 - ) $stop; + cover property (@(posedge clk iff enable[2]) 1) $stop; - cover property ( - @(posedge clk iff enable[3]) - 0 - ) $stop; + cover property (@(posedge clk iff enable[3]) 0) $stop; endmodule diff --git a/test_regress/t/t_assert_iff_clk_unsup.out b/test_regress/t/t_assert_iff_clk_unsup.out index 2a75cd94e..3ff98273e 100644 --- a/test_regress/t/t_assert_iff_clk_unsup.out +++ b/test_regress/t/t_assert_iff_clk_unsup.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_assert_iff_clk_unsup.v:20:21: Unsupported: property '(disable iff (...) @ (...)' +%Error-UNSUPPORTED: t/t_assert_iff_clk_unsup.v:20:20: Unsupported: property '(disable iff (...) @ (...)' : ... Suggest use property '(@(...) disable iff (...))' - 20 | assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); - | ^~~~~~~ + 20 | assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assert_iff_clk_unsup.v b/test_regress/t/t_assert_iff_clk_unsup.v index 8890d5878..efe917a04 100644 --- a/test_regress/t/t_assert_iff_clk_unsup.v +++ b/test_regress/t/t_assert_iff_clk_unsup.v @@ -4,19 +4,19 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic val = 0; + input clk; + int cyc = 0; + logic val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); + assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); endmodule diff --git a/test_regress/t/t_assert_imm_nz_bad.out b/test_regress/t/t_assert_imm_nz_bad.out index 8bf198256..33769d42d 100644 --- a/test_regress/t/t_assert_imm_nz_bad.out +++ b/test_regress/t/t_assert_imm_nz_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_assert_imm_nz_bad.v:13:26: Deferred assertions must use '#0' (IEEE 1800-2023 16.4) - 13 | labeled_imas: assert #1 (clk); - | ^ +%Error: t/t_assert_imm_nz_bad.v:14:11: Deferred assertions must use '#0' (IEEE 1800-2023 16.4) + 14 | assert #1 (clk); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_assert_imm_nz_bad.v b/test_regress/t/t_assert_imm_nz_bad.v index eaee647fe..49bbc1b7b 100644 --- a/test_regress/t/t_assert_imm_nz_bad.v +++ b/test_regress/t/t_assert_imm_nz_bad.v @@ -4,12 +4,13 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; + input clk; - labeled_imas: assert #1 (clk); // BAD: #1 + labeled_imas : + assert #1 (clk); // BAD: #1 endmodule diff --git a/test_regress/t/t_assert_implication.v b/test_regress/t/t_assert_implication.v index 4eb169f87..669b03671 100644 --- a/test_regress/t/t_assert_implication.v +++ b/test_regress/t/t_assert_implication.v @@ -4,127 +4,84 @@ // SPDX-FileCopyrightText: 2019 Peter Monsson // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - Test test (/*AUTOINST*/ - // Inputs - .clk(clk), - .cyc(cyc)); + Test test ( /*AUTOINST*/ + // Inputs + .clk(clk), + .cyc(cyc) + ); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $display("cyc=%0d", cyc); + $display("cyc=%0d", cyc); `endif - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule -module Test - ( - input clk, - input integer cyc - ); +module Test ( + input clk, + input integer cyc +); `ifdef FAIL_ASSERT_1 - assert property ( - @(posedge clk) - 1 |-> 0 - ) else $display("[%0t] wrong implication", $time); + assert property (@(posedge clk) 1 |-> 0) + else $display("[%0t] wrong implication", $time); - assert property ( - @(posedge clk) - 1 |=> 0 - ) else $display("[%0t] wrong implication", $time); + assert property (@(posedge clk) 1 |=> 0) + else $display("[%0t] wrong implication", $time); - assert property ( - @(posedge clk) - cyc%3==1 |=> cyc%3==1 - ) else $display("[%0t] wrong implication (step)", $time); + assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 1) + else $display("[%0t] wrong implication (step)", $time); - assert property ( - @(posedge clk) - cyc%3==1 |=> cyc%3==0 - ) else $display("[%0t] wrong implication (step)", $time); + assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 0) + else $display("[%0t] wrong implication (step)", $time); - assert property ( - @(posedge clk) disable iff (cyc == 3) - (cyc == 4) |=> 0 - ) else $display("[%0t] wrong implication (disable)", $time); + assert property (@(posedge clk) disable iff (cyc == 3) (cyc == 4) |=> 0) + else $display("[%0t] wrong implication (disable)", $time); - assert property ( - @(posedge clk) disable iff (cyc == 6) - (cyc == 4) |=> 0 - ) else $display("[%0t] wrong implication (disable)", $time); + assert property (@(posedge clk) disable iff (cyc == 6) (cyc == 4) |=> 0) + else $display("[%0t] wrong implication (disable)", $time); `endif - // Test |-> - assert property ( - @(posedge clk) - 1 |-> 1 - ); + // Test |-> + assert property (@(posedge clk) 1 |-> 1); - assert property ( - @(posedge clk) - 0 |-> 0 - ); + assert property (@(posedge clk) 0 |-> 0); - assert property ( - @(posedge clk) - 0 |-> 1 - ); + assert property (@(posedge clk) 0 |-> 1); - // Test |=> - assert property ( - @(posedge clk) - 1 |=> 1 - ); + // Test |=> + assert property (@(posedge clk) 1 |=> 1); - assert property ( - @(posedge clk) - 0 |=> 0 - ); + assert property (@(posedge clk) 0 |=> 0); - assert property ( - @(posedge clk) - 0 |=> 1 - ); + assert property (@(posedge clk) 0 |=> 1); - // Test correct handling of time step in |=> - assert property ( - @(posedge clk) - cyc%3==1 |=> cyc%3==2 - ); + // Test correct handling of time step in |=> + assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 2); - // Test correct handling of disable iff - assert property ( - @(posedge clk) disable iff ($sampled(cyc) < 3) - 1 |=> cyc > 3 - ); + // Test correct handling of disable iff + assert property (@(posedge clk) disable iff ($sampled(cyc) < 3) 1 |=> cyc > 3); - // Test correct handling of disable iff in current cycle - assert property ( - @(posedge clk) disable iff ($sampled(cyc) == 4) - (cyc == 4) |=> 0 - ); + // Test correct handling of disable iff in current cycle + assert property (@(posedge clk) disable iff ($sampled(cyc) == 4) (cyc == 4) |=> 0); - // Test correct handling of disable iff in previous cycle - assert property ( - @(posedge clk) disable iff (cyc == 5) - (cyc == 4) |=> 0 - ); + // Test correct handling of disable iff in previous cycle + assert property (@(posedge clk) disable iff (cyc == 5) (cyc == 4) |=> 0); endmodule diff --git a/test_regress/t/t_assert_inside_cond.v b/test_regress/t/t_assert_inside_cond.v index 1a70b7a14..d7058bed5 100644 --- a/test_regress/t/t_assert_inside_cond.v +++ b/test_regress/t/t_assert_inside_cond.v @@ -11,36 +11,36 @@ module t (/*AUTOARG*/ clk ); - input clk; - output logic hit; + input clk; + output logic hit; - logic [31:0] addr; - int cyc; + logic [31:0] addr; + int cyc; - initial addr = 32'h380; + initial addr = 32'h380; - always @ (posedge clk) begin - cyc <= cyc + 1; + always @ (posedge clk) begin + cyc <= cyc + 1; `ifdef T_ASSERT_INSIDE_COND - addr <= 32'h380; + addr <= 32'h380; `elsif T_ASSERT_INSIDE_COND_BAD - addr <= 32'h389; + addr <= 32'h389; `else `error "Bad test define" `endif - if (cyc == 9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always_comb begin - hit = 0; - unique case (addr[11:0]) inside - [12'h380 : 12'h388]: begin - hit = 1; - end - endcase - end + always_comb begin + hit = 0; + unique case (addr[11:0]) inside + [12'h380 : 12'h388]: begin + hit = 1; + end + endcase + end endmodule diff --git a/test_regress/t/t_assert_on.v b/test_regress/t/t_assert_on.v index 5ee299316..3639d06b0 100644 --- a/test_regress/t/t_assert_on.v +++ b/test_regress/t/t_assert_on.v @@ -4,17 +4,14 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - - always @ (posedge clk) begin - assert (0); - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + assert (0); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_past.v b/test_regress/t/t_assert_past.v index 40708babf..976623021 100644 --- a/test_regress/t/t_assert_past.v +++ b/test_regress/t/t_assert_past.v @@ -4,25 +4,24 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); - input clk; - int cyc = 0; - logic val = 0; - // Example: - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - $display("t=%0t cyc=%0d val=%b", $time, cyc, val); - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - assert property(@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0) - else $display("$past assert 1 failed"); - assert property(@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1) - else $display("$past assert 2 failed"); - // Example end +module t ( + input clk +); + int cyc = 0; + logic val = 0; + // Example: + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + $display("t=%0t cyc=%0d val=%b", $time, cyc, val); + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + assert property (@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0) + else $display("$past assert 1 failed"); + assert property (@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1) + else $display("$past assert 2 failed"); + // Example end endmodule diff --git a/test_regress/t/t_assert_procedural_clk_bad.out b/test_regress/t/t_assert_procedural_clk_bad.out index 9214de450..1da4cc66e 100644 --- a/test_regress/t/t_assert_procedural_clk_bad.out +++ b/test_regress/t/t_assert_procedural_clk_bad.out @@ -1,10 +1,10 @@ -%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:21:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) - : ... note: In instance 't' - 21 | assume property (@(posedge clk) cyc == 9); - | ^~~~~~ +%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:19:9: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) + : ... note: In instance 't' + 19 | assume property (@(posedge clk) cyc == 9); + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) - : ... note: In instance 't' - 22 | assume property (@(negedge clk) cyc == 9); - | ^~~~~~ +%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:20:9: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) + : ... note: In instance 't' + 20 | assume property (@(negedge clk) cyc == 9); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_procedural_clk_bad.v b/test_regress/t/t_assert_procedural_clk_bad.v index e0615046f..7e458231f 100644 --- a/test_regress/t/t_assert_procedural_clk_bad.v +++ b/test_regress/t/t_assert_procedural_clk_bad.v @@ -4,28 +4,26 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 1; + wire [7:0] cyc_copy = cyc[7:0]; - integer cyc; initial cyc=1; - wire [7:0] cyc_copy = cyc[7:0]; - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==9) begin - assume property (@(posedge clk) cyc == 9); - assume property (@(negedge clk) cyc == 9); - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 9) begin + assume property (@(posedge clk) cyc == 9); + assume property (@(negedge clk) cyc == 9); end - end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_assert_question.v b/test_regress/t/t_assert_question.v index 8d756a8e3..518d90d43 100644 --- a/test_regress/t/t_assert_question.v +++ b/test_regress/t/t_assert_question.v @@ -11,24 +11,24 @@ module t (/*AUTOARG*/ clk, sel, a, c ); - input clk; - input bit [3:0] sel; - input bit [3:0] a; - input bit c; - output bit dout; + input clk; + input bit [3:0] sel; + input bit [3:0] a; + input bit c; + output bit dout; - localparam logic DC = 1'b?; + localparam logic DC = 1'b?; - always_ff @(posedge clk) begin - unique casez(sel) - 4'b0000: dout <= a[0]; - 4'b001?: dout <= a[1]; - {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2]; - {1'b1, 1'b?, 1'b?, DC}: dout <= a[3]; - default: dout <= '0; - endcase - $write("*-* All Finished *-*\n"); - $finish; - end + always_ff @(posedge clk) begin + unique casez(sel) + 4'b0000: dout <= a[0]; + 4'b001?: dout <= a[1]; + {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2]; + {1'b1, 1'b?, 1'b?, DC}: dout <= a[3]; + default: dout <= '0; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_sampled.v b/test_regress/t/t_assert_sampled.v index 5344592d6..0522ad690 100644 --- a/test_regress/t/t_assert_sampled.v +++ b/test_regress/t/t_assert_sampled.v @@ -4,87 +4,109 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [3:0] a, b; + reg [3:0] a, b; - Test1 t1(clk, a, b); - Test2 t2(clk, a, b); - Test3 t3(clk, a, b); + Test1 t1 ( + clk, + a, + b + ); + Test2 t2 ( + clk, + a, + b + ); + Test3 t3 ( + clk, + a, + b + ); - initial begin - a = 0; - b = 0; - end + initial begin + a = 0; + b = 0; + end - always @(posedge clk) begin - a <= a + 1; - b = b + 1; + always @(posedge clk) begin + a <= a + 1; + b = b + 1; - $display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b)); + $display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b)); - if (b >= 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (b >= 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test1( - clk, a, b - ); +module Test1 ( + clk, + a, + b +); - input clk; - input [3:0] a, b; + input clk; + input [3:0] a, b; - assert property (@(posedge clk) $sampled(a) == $sampled(b)); + assert property (@(posedge clk) $sampled(a) == $sampled(b)); endmodule -module Test2( - clk, a, b - ); +module Test2 ( + clk, + a, + b +); - input clk; - input [3:0] a, b; + input clk; + input [3:0] a, b; - assert property (@(posedge clk) a == b); + assert property (@(posedge clk) a == b); endmodule -module Test3( - clk, a, b - ); +module Test3 ( + clk, + a, + b +); - input clk; - input [3:0] a, b; + input clk; + input [3:0] a, b; - int hits[10]; + int hits[10]; - assert property (@(posedge clk) a == b) hits[1]=1; - assert property (@(posedge clk) a == b) else hits[2]=1; - assert property (@(posedge clk) a == b) hits[3]=1; else hits[4]=1; + assert property (@(posedge clk) a == b) hits[1] = 1; + assert property (@(posedge clk) a == b) + else hits[2] = 1; + assert property (@(posedge clk) a == b) hits[3] = 1; + else hits[4] = 1; - assert property (@(posedge clk) a != b) hits[5]=1; - assert property (@(posedge clk) a != b) else hits[6]=1; - assert property (@(posedge clk) a != b) hits[7]=1; else hits[8]=1; + assert property (@(posedge clk) a != b) hits[5] = 1; + assert property (@(posedge clk) a != b) + else hits[6] = 1; + assert property (@(posedge clk) a != b) hits[7] = 1; + else hits[8] = 1; - final begin - `checkd(hits[1], 1); - `checkd(hits[2], 0); - `checkd(hits[3], 1); - `checkd(hits[4], 0); - `checkd(hits[5], 0); - `checkd(hits[6], 1); - `checkd(hits[7], 0); - `checkd(hits[8], 1); - end + final begin + `checkd(hits[1], 1); + `checkd(hits[2], 0); + `checkd(hits[3], 1); + `checkd(hits[4], 0); + `checkd(hits[5], 0); + `checkd(hits[6], 1); + `checkd(hits[7], 0); + `checkd(hits[8], 1); + end endmodule diff --git a/test_regress/t/t_assert_synth.v b/test_regress/t/t_assert_synth.v index fa9cff4f6..cf6f7aa7d 100644 --- a/test_regress/t/t_assert_synth.v +++ b/test_regress/t/t_assert_synth.v @@ -4,112 +4,109 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg a; initial a = 1'b1; + reg b_fc; initial b_fc = 1'b0; + reg b_pc; initial b_pc = 1'b0; + reg b_oh; initial b_oh = 1'b0; + reg b_oc; initial b_oc = 1'b0; + wire a_l = ~a; + wire b_oc_l = ~b_oc; - reg a; initial a = 1'b1; - reg b_fc; initial b_fc = 1'b0; - reg b_pc; initial b_pc = 1'b0; - reg b_oh; initial b_oh = 1'b0; - reg b_oc; initial b_oc = 1'b0; - wire a_l = ~a; - wire b_oc_l = ~b_oc; + // Note we must ensure that full, parallel, etc, only fire during + // edges (not mid-cycle), and must provide a way to turn them off. + // SystemVerilog provides: $asserton and $assertoff. - // Note we must ensure that full, parallel, etc, only fire during - // edges (not mid-cycle), and must provide a way to turn them off. - // SystemVerilog provides: $asserton and $assertoff. + // verilator lint_off CASEINCOMPLETE - // verilator lint_off CASEINCOMPLETE - - always @* begin - // Note not all tools support directives on casez's + always @* begin + // Note not all tools support directives on casez's `ifdef ATTRIBUTES - case ({a,b_fc}) // synopsys full_case + case ({a,b_fc}) // synopsys full_case `else - case ({a,b_fc}) + case ({a,b_fc}) `endif - 2'b0_0: ; - 2'b0_1: ; - 2'b1_0: ; - // Note no default - endcase - priority case ({a,b_fc}) - 2'b0_0: ; - 2'b0_1: ; - 2'b1_0: ; - // Note no default - endcase - end + 2'b0_0: ; + 2'b0_1: ; + 2'b1_0: ; + // Note no default + endcase + priority case ({a,b_fc}) + 2'b0_0: ; + 2'b0_1: ; + 2'b1_0: ; + // Note no default + endcase + end - always @* begin + always @* begin `ifdef ATTRIBUTES - case (1'b1) // synopsys full_case parallel_case + case (1'b1) // synopsys full_case parallel_case `else `ifdef FAILING_FULL - case (1'b1) // synopsys parallel_case + case (1'b1) // synopsys parallel_case `else - case (1'b1) // synopsys parallel_full + case (1'b1) // synopsys parallel_full `endif `endif - a: ; - b_pc: ; - endcase - end + a: ; + b_pc: ; + endcase + end `ifdef NOT_YET_VERILATOR // Unsupported - // ambit synthesis one_hot "a, b_oh" - // cadence one_cold "a_l, b_oc_l" + // ambit synthesis one_hot "a, b_oh" + // cadence one_cold "a_l, b_oc_l" `endif - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= 1'b1; - b_fc <= 1'b0; - b_pc <= 1'b0; - b_oh <= 1'b0; - b_oc <= 1'b0; - end - if (cyc==2) begin - a <= 1'b0; - b_fc <= 1'b1; - b_pc <= 1'b1; - b_oh <= 1'b1; - b_oc <= 1'b1; - end - if (cyc==3) begin - a <= 1'b1; - b_fc <= 1'b0; - b_pc <= 1'b0; - b_oh <= 1'b0; - b_oc <= 1'b0; - end - if (cyc==4) begin + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 1'b1; + b_fc <= 1'b0; + b_pc <= 1'b0; + b_oh <= 1'b0; + b_oc <= 1'b0; + end + if (cyc==2) begin + a <= 1'b0; + b_fc <= 1'b1; + b_pc <= 1'b1; + b_oh <= 1'b1; + b_oc <= 1'b1; + end + if (cyc==3) begin + a <= 1'b1; + b_fc <= 1'b0; + b_pc <= 1'b0; + b_oh <= 1'b0; + b_oc <= 1'b0; + end + if (cyc==4) begin `ifdef FAILING_FULL - b_fc <= 1'b1; + b_fc <= 1'b1; `endif `ifdef FAILING_PARALLEL - b_pc <= 1'b1; + b_pc <= 1'b1; `endif `ifdef FAILING_OH - b_oh <= 1'b1; + b_oh <= 1'b1; `endif `ifdef FAILING_OC - b_oc <= 1'b1; + b_oc <= 1'b1; `endif - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end end - end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end initial begin : test_info $info ("Start of $info test"); diff --git a/test_regress/t/t_assert_synth_full.out b/test_regress/t/t_assert_synth_full.out index 2134d5a40..662534e16 100644 --- a/test_regress/t/t_assert_synth_full.out +++ b/test_regress/t/t_assert_synth_full.out @@ -1,6 +1,6 @@ -[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test -[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test -[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test -[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3' -%Error: t/t_assert_synth.v:31: Verilog $stop +[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test +[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test +[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test +[40] %Error: t_assert_synth.v:28: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3' +%Error: t/t_assert_synth.v:28: Verilog $stop Aborting... diff --git a/test_regress/t/t_assert_synth_full_vlt.out b/test_regress/t/t_assert_synth_full_vlt.out index a14c33995..4e1202d4b 100644 --- a/test_regress/t/t_assert_synth_full_vlt.out +++ b/test_regress/t/t_assert_synth_full_vlt.out @@ -1,6 +1,6 @@ -[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test -[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test -[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test -[40] %Error: t_assert_synth.v:40: Assertion failed in top.t: priority case, but non-match found for '2'h3' -%Error: t/t_assert_synth.v:40: Verilog $stop +[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test +[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test +[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test +[40] %Error: t_assert_synth.v:37: Assertion failed in top.t: priority case, but non-match found for '2'h3' +%Error: t/t_assert_synth.v:37: Verilog $stop Aborting... diff --git a/test_regress/t/t_assert_synth_parallel.out b/test_regress/t/t_assert_synth_parallel.out index 2958bbba9..bbe98a077 100644 --- a/test_regress/t/t_assert_synth_parallel.out +++ b/test_regress/t/t_assert_synth_parallel.out @@ -1,6 +1,6 @@ -[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test -[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test -[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test -[40] %Error: t_assert_synth.v:50: Assertion failed in top.t: synthesis full_case parallel_case, but multiple matches found for '1'h1' -%Error: t/t_assert_synth.v:50: Verilog $stop +[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test +[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test +[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test +[40] %Error: t_assert_synth.v:47: Assertion failed in top.t: synthesis full_case parallel_case, but multiple matches found for '1'h1' +%Error: t/t_assert_synth.v:47: Verilog $stop Aborting... diff --git a/test_regress/t/t_assert_synth_parallel.vlt b/test_regress/t/t_assert_synth_parallel.vlt index 566a0b9f7..c5824bdc5 100644 --- a/test_regress/t/t_assert_synth_parallel.vlt +++ b/test_regress/t/t_assert_synth_parallel.vlt @@ -6,4 +6,4 @@ `verilator_config -parallel_case -file "t/t_assert_synth.v" -lines 55 +parallel_case -file "t/t_assert_synth.v" -lines 52 diff --git a/test_regress/t/t_assert_synth_parallel_vlt.out b/test_regress/t/t_assert_synth_parallel_vlt.out index 41a1a77c4..14f9cc094 100644 --- a/test_regress/t/t_assert_synth_parallel_vlt.out +++ b/test_regress/t/t_assert_synth_parallel_vlt.out @@ -1,6 +1,6 @@ -[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test -[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test -[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test -[40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found for '1'h1' -%Error: t/t_assert_synth.v:55: Verilog $stop +[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test +[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test +[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test +[40] %Error: t_assert_synth.v:52: Assertion failed in top.t: synthesis parallel_case, but multiple matches found for '1'h1' +%Error: t/t_assert_synth.v:52: Verilog $stop Aborting... diff --git a/test_regress/t/t_assert_unique_case_bad.v b/test_regress/t/t_assert_unique_case_bad.v index 949ccd9c5..8f5cd8e8c 100644 --- a/test_regress/t/t_assert_unique_case_bad.v +++ b/test_regress/t/t_assert_unique_case_bad.v @@ -4,61 +4,61 @@ // SPDX-FileCopyrightText: 2024 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - hit, - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Outputs + hit, + // Inputs + clk +); - input clk; - output logic hit; + input clk; + output logic hit; - logic [31:0] addr; - logic [11:0] match_item0, match_item1; - int cyc; - string s; + logic [31:0] addr; + logic [11:0] match_item0, match_item1; + int cyc; + string s; - initial addr = 32'h380; + initial addr = 32'h380; - always @ (posedge clk) begin - cyc <= cyc + 1; - addr <= 32'h380 + cyc; - match_item0 = 12'h 380 + cyc[11:0]; - match_item1 = 12'h 390 - cyc[11:0]; - $sformat(s, "%1d", cyc); - if (cyc == 9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + addr <= 32'h380 + cyc; + match_item0 = 12'h380 + cyc[11:0]; + match_item1 = 12'h390 - cyc[11:0]; + $sformat(s, "%1d", cyc); + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always_comb begin - hit = 1; - unique case (addr[11:0]) - match_item0: $display("match_item0"); - match_item1: $display("match_item1"); - default: hit = 0; - endcase - end + always_comb begin + hit = 1; + unique case (addr[11:0]) + match_item0: $display("match_item0"); + match_item1: $display("match_item1"); + default: hit = 0; + endcase + end `ifdef NO_STOP_FAIL - always_comb begin - unique case (s) - "": ; - "0": ; - "2": ; - "4": ; - "6": ; - endcase - end - always_comb begin - priority case (s) - $sformatf("%1d", cyc - 1): ; - "0": ; - "6": ; - endcase - end + always_comb begin + unique case (s) + "": ; + "0": ; + "2": ; + "4": ; + "6": ; + endcase + end + always_comb begin + priority case (s) + $sformatf("%1d", cyc - 1): ; + "0": ; + "6": ; + endcase + end `endif endmodule diff --git a/test_regress/t/t_assign_expr.v b/test_regress/t/t_assign_expr.v index ff551bc81..98ecc2759 100644 --- a/test_regress/t/t_assign_expr.v +++ b/test_regress/t/t_assign_expr.v @@ -4,76 +4,94 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - int a; - int b; - int i; + int a; + int b; + int i; - // verilator lint_off ASSIGNEQEXPR - initial begin - a = 10; - i = (a = 2); - `checkd(a, 2); `checkd(i, 2); + // verilator lint_off ASSIGNEQEXPR + initial begin + a = 10; + i = (a = 2); + `checkd(a, 2); + `checkd(i, 2); - a = 10; - i = (a += 2); - `checkd(a, 12); `checkd(i, 12); + a = 10; + i = (a += 2); + `checkd(a, 12); + `checkd(i, 12); - a = 10; - i = (a -= 2); - `checkd(a, 8); `checkd(i, 8); + a = 10; + i = (a -= 2); + `checkd(a, 8); + `checkd(i, 8); - a = 10; - i = (a *= 2); - `checkd(a, 20); `checkd(i, 20); + a = 10; + i = (a *= 2); + `checkd(a, 20); + `checkd(i, 20); - a = 10; - i = (a /= 2); - `checkd(a, 5); `checkd(i, 5); + a = 10; + i = (a /= 2); + `checkd(a, 5); + `checkd(i, 5); - a = 11; - i = (a %= 2); - `checkd(a, 1); `checkd(i, 1); + a = 11; + i = (a %= 2); + `checkd(a, 1); + `checkd(i, 1); - a = 10; - i = (a &= 2); - `checkd(a, 2); `checkd(i, 2); + a = 10; + i = (a &= 2); + `checkd(a, 2); + `checkd(i, 2); - a = 8; - i = (a |= 2); - `checkd(a, 10); `checkd(i, 10); + a = 8; + i = (a |= 2); + `checkd(a, 10); + `checkd(i, 10); - a = 10; - i = (a ^= 2); - `checkd(a, 8); `checkd(i, 8); + a = 10; + i = (a ^= 2); + `checkd(a, 8); + `checkd(i, 8); - a = 10; - i = (a <<= 2); - `checkd(a, 40); `checkd(i, 40); + a = 10; + i = (a <<= 2); + `checkd(a, 40); + `checkd(i, 40); - a = 10; - i = (a >>= 2); - `checkd(a, 2); `checkd(i, 2); + a = 10; + i = (a >>= 2); + `checkd(a, 2); + `checkd(i, 2); - a = 10; - i = (a >>>= 2); - `checkd(a, 2); `checkd(i, 2); + a = 10; + i = (a >>>= 2); + `checkd(a, 2); + `checkd(i, 2); - a = 10; - i = (a = (b = 5)); - `checkd(a, 5); `checkd(i, 5); `checkd(b, 5); + a = 10; + i = (a = (b = 5)); + `checkd(a, 5); + `checkd(i, 5); + `checkd(b, 5); - a = 10; - b = 6; - i = ((a += (b += 1) + 1)); - `checkd(a, 18); `checkd(i, 18); `checkd(b, 7); + a = 10; + b = 6; + i = ((a += (b += 1) + 1)); + `checkd(a, 18); + `checkd(i, 18); + `checkd(b, 7); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assign_inline.v b/test_regress/t/t_assign_inline.v index f378db28e..ad22baf4a 100644 --- a/test_regress/t/t_assign_inline.v +++ b/test_regress/t/t_assign_inline.v @@ -4,50 +4,48 @@ // SPDX-FileCopyrightText: 2015 Mike Thyer // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - int cycle=0; + int cycle = 0; - // verilator lint_off UNOPTFLAT - reg [7:0] a_r; - wire [7:0] a_w; - reg [7:0] b_r; - reg [7:0] c_d_r, c_q_r; + // verilator lint_off UNOPTFLAT + reg [7:0] a_r; + wire [7:0] a_w; + reg [7:0] b_r; + reg [7:0] c_d_r, c_q_r; - assign a_w = a_r; + assign a_w = a_r; - always @(*) begin - a_r = 0; - b_r = a_w; // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete" - a_r = c_q_r; - c_d_r = c_q_r; - end + always @(*) begin + a_r = 0; + b_r = a_w; // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete" + a_r = c_q_r; + c_d_r = c_q_r; + end - // stimulus + checks - always @(posedge clk) begin - cycle <= cycle+1; - if (cycle==0) begin - c_q_r <= 8'b0; - end - else begin - c_q_r <= c_d_r+1; + // stimulus + checks + always @(posedge clk) begin + cycle <= cycle + 1; + if (cycle == 0) begin + c_q_r <= 8'b0; + end + else begin + c_q_r <= c_d_r + 1; `ifdef TEST_VERBOSE - $display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same + $display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same `endif - end - if (cycle >= 10) begin - if (b_r==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $stop; - end - end - end + end + if (cycle >= 10) begin + if (b_r == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end + end endmodule diff --git a/test_regress/t/t_assign_slice_overflow.v b/test_regress/t/t_assign_slice_overflow.v index 64b6fca2c..ed1af2f4d 100644 --- a/test_regress/t/t_assign_slice_overflow.v +++ b/test_regress/t/t_assign_slice_overflow.v @@ -23,157 +23,158 @@ // SPDX-FileCopyrightText: 2021 David Turner // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - // Non-constant offsets - reg varoffset1; - reg [6:0] varoffset2; - reg [6:0] varoffset3; + integer cyc = 0; + // Non-constant offsets + reg varoffset1; + reg [6:0] varoffset2; + reg [6:0] varoffset3; - // Destinations for variable-offset assignments - reg [69:0] dstwide1; - reg [69:0] dstwide2; - reg [1:0] dstnarrow; + // Destinations for variable-offset assignments + reg [69:0] dstwide1; + reg [69:0] dstwide2; + reg [1:0] dstnarrow; - // Constant offsets - reg [6:0] constoffset; + // Constant offsets + reg [6:0] constoffset; - // Destinations for constant-offset assignments - reg [2:0] dst_cdata; - reg [11:0] dst_sdata; - reg [29:0] dst_idata; - reg [59:0] dst_qdata; - reg [69:0] dst_wdata1; // assign idata within word - reg [69:0] dst_wdata2; // assign idata crossing word boundary - reg [69:0] dst_wdata3; // assign idata corresponding to whole word - reg [69:0] dst_wdata4; // assign qdata - reg [69:0] dst_wdata5; // assign wdata corresponding to several whole words - reg [69:0] dst_wdata6; // assign wdata starting at word-offset - reg [69:0] dst_wdata7; // assign wdata unaligned + // Destinations for constant-offset assignments + reg [2:0] dst_cdata; + reg [11:0] dst_sdata; + reg [29:0] dst_idata; + reg [59:0] dst_qdata; + reg [69:0] dst_wdata1; // assign idata within word + reg [69:0] dst_wdata2; // assign idata crossing word boundary + reg [69:0] dst_wdata3; // assign idata corresponding to whole word + reg [69:0] dst_wdata4; // assign qdata + reg [69:0] dst_wdata5; // assign wdata corresponding to several whole words + reg [69:0] dst_wdata6; // assign wdata starting at word-offset + reg [69:0] dst_wdata7; // assign wdata unaligned - always @(*) begin - // Non-constant select offset, destination narrow - dstnarrow = 2'd0; - dstnarrow[varoffset1 +: 2'd2] = 2'd2; + always @(*) begin + // Non-constant select offset, destination narrow + dstnarrow = 2'd0; + dstnarrow[varoffset1+:2'd2] = 2'd2; - // Non-constant select offset, destination wide, width == 1 - dstwide1 = 70'd0; - dstwide1[varoffset2 +: 1'd1] = 1'd1; + // Non-constant select offset, destination wide, width == 1 + dstwide1 = 70'd0; + dstwide1[varoffset2+:1'd1] = 1'd1; - // Non-constant select offset, destination wide, width != 1 - dstwide2 = 70'd0; - dstwide2[varoffset3 +: 2'd2] = 2'd2; + // Non-constant select offset, destination wide, width != 1 + dstwide2 = 70'd0; + dstwide2[varoffset3+:2'd2] = 2'd2; - // Constant offset, IData into CData - constoffset = 7'd2; - dst_cdata = 3'd0; - dst_cdata[constoffset[0 +: 2] +: 3'd3] = 3'd6; + // Constant offset, IData into CData + constoffset = 7'd2; + dst_cdata = 3'd0; + dst_cdata[constoffset[0+:2]+:3'd3] = 3'd6; - // Constant offset, IData into SData - constoffset = 7'd11; - dst_sdata = 12'd0; - dst_sdata[constoffset[0 +: 4] +: 2'd2] = 2'd2; + // Constant offset, IData into SData + constoffset = 7'd11; + dst_sdata = 12'd0; + dst_sdata[constoffset[0+:4]+:2'd2] = 2'd2; - // Constant offset, IData into IData - constoffset = 7'd29; - dst_idata = 30'd0; - dst_idata[constoffset[0 +: 5] +: 2'd2] = 2'd2; + // Constant offset, IData into IData + constoffset = 7'd29; + dst_idata = 30'd0; + dst_idata[constoffset[0+:5]+:2'd2] = 2'd2; - // Constant offset, QData into QData - constoffset = 7'd59; - dst_qdata = 60'd0; - dst_qdata[constoffset[0 +: 6] +: 2'd2] = 2'd2; + // Constant offset, QData into QData + constoffset = 7'd59; + dst_qdata = 60'd0; + dst_qdata[constoffset[0+:6]+:2'd2] = 2'd2; - // Constant offset, IData into WData within word - constoffset = 7'd69; - dst_wdata1 = 70'd0; - dst_wdata1[constoffset +: 2'd2] = 2'd2; + // Constant offset, IData into WData within word + constoffset = 7'd69; + dst_wdata1 = 70'd0; + dst_wdata1[constoffset+:2'd2] = 2'd2; - // Constant offset, IData into WData crossing word boundary - constoffset = 7'd61; - dst_wdata2 = 70'd0; - dst_wdata2[constoffset +: 4'd10] = 10'd1 << 4'd9; + // Constant offset, IData into WData crossing word boundary + constoffset = 7'd61; + dst_wdata2 = 70'd0; + dst_wdata2[constoffset+:4'd10] = 10'd1 << 4'd9; - // Constant offset, IData into WData replacing a whole word - constoffset = 7'd64; - dst_wdata3 = 70'd0; - dst_wdata3[constoffset +: 6'd32] = 32'd1 << 3'd6; + // Constant offset, IData into WData replacing a whole word + constoffset = 7'd64; + dst_wdata3 = 70'd0; + dst_wdata3[constoffset+:6'd32] = 32'd1 << 3'd6; - // Constant offset, QData into WData - constoffset = 7'd31; - dst_wdata4 = 70'd0; - dst_wdata4[constoffset +: 7'd40] = 40'd1 << 7'd39; + // Constant offset, QData into WData + constoffset = 7'd31; + dst_wdata4 = 70'd0; + dst_wdata4[constoffset+:7'd40] = 40'd1 << 7'd39; - // Constant offset, WData into WData replacing whole words - constoffset = 7'd32; - dst_wdata5 = 70'd0; - dst_wdata5[constoffset +: 7'd64] = 64'd1 << 7'd38; + // Constant offset, WData into WData replacing whole words + constoffset = 7'd32; + dst_wdata5 = 70'd0; + dst_wdata5[constoffset+:7'd64] = 64'd1 << 7'd38; - // Constant offset, WData into WData offset word aligned - constoffset = 7'd32; - dst_wdata6 = 70'd0; - dst_wdata6[constoffset +: 7'd40] = 40'd1 << 7'd38; + // Constant offset, WData into WData offset word aligned + constoffset = 7'd32; + dst_wdata6 = 70'd0; + dst_wdata6[constoffset+:7'd40] = 40'd1 << 7'd38; - // Constant offset, WData into WData unaligned - constoffset = 7'd1; - dst_wdata7 = 70'd0; - dst_wdata7[constoffset +: 7'd70] = 70'd1 << 7'd69; - end + // Constant offset, WData into WData unaligned + constoffset = 7'd1; + dst_wdata7 = 70'd0; + dst_wdata7[constoffset+:7'd70] = 70'd1 << 7'd69; + end - // Test loop - always @ (posedge clk) begin - // State machine to avoid verilator constant-folding offset - if (cyc == 0) begin - // Initialisation - varoffset1 <= 1'd0; - varoffset2 <= 7'd0; - varoffset3 <= 7'd0; - end else if (cyc == 1) begin - // Variable offsets set here to avoid verilator constant folding - varoffset1 <= 1'd1; - varoffset2 <= 7'd70; - varoffset3 <= 7'd69; - end else if (cyc == 2) begin - // Check all destinations are 0 - $write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1); - $write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1); - $write("dstnarrow = %23d, downshifted = %23d\n", dstnarrow, dstnarrow >> 1); - $write("dst_cdata = %23d, downshifted = %23d\n", dst_cdata, dst_cdata >> 1); - $write("dst_sdata = %23d, downshifted = %23d\n", dst_sdata, dst_sdata >> 1); - $write("dst_idata = %23d, downshifted = %23d\n", dst_idata, dst_idata >> 1); - $write("dst_qdata = %23d, downshifted = %23d\n", dst_qdata, dst_qdata >> 1); - $write("dst_wdata1 = %23d, downshifted = %23d\n", dst_wdata1, dst_wdata1 >> 1); - $write("dst_wdata2 = %23d, downshifted = %23d\n", dst_wdata2, dst_wdata2 >> 1); - $write("dst_wdata3 = %23d, downshifted = %23d\n", dst_wdata3, dst_wdata3 >> 1); - $write("dst_wdata4 = %23d, downshifted = %23d\n", dst_wdata4, dst_wdata4 >> 1); - $write("dst_wdata5 = %23d, downshifted = %23d\n", dst_wdata5, dst_wdata5 >> 1); - $write("dst_wdata6 = %23d, downshifted = %23d\n", dst_wdata6, dst_wdata6 >> 1); - $write("dst_wdata7 = %23d, downshifted = %23d\n", dst_wdata7, dst_wdata7 >> 1); + // Test loop + always @(posedge clk) begin + // State machine to avoid verilator constant-folding offset + if (cyc == 0) begin + // Initialisation + varoffset1 <= 1'd0; + varoffset2 <= 7'd0; + varoffset3 <= 7'd0; + end + else if (cyc == 1) begin + // Variable offsets set here to avoid verilator constant folding + varoffset1 <= 1'd1; + varoffset2 <= 7'd70; + varoffset3 <= 7'd69; + end + else if (cyc == 2) begin + // Check all destinations are 0 + $write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1); + $write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1); + $write("dstnarrow = %23d, downshifted = %23d\n", dstnarrow, dstnarrow >> 1); + $write("dst_cdata = %23d, downshifted = %23d\n", dst_cdata, dst_cdata >> 1); + $write("dst_sdata = %23d, downshifted = %23d\n", dst_sdata, dst_sdata >> 1); + $write("dst_idata = %23d, downshifted = %23d\n", dst_idata, dst_idata >> 1); + $write("dst_qdata = %23d, downshifted = %23d\n", dst_qdata, dst_qdata >> 1); + $write("dst_wdata1 = %23d, downshifted = %23d\n", dst_wdata1, dst_wdata1 >> 1); + $write("dst_wdata2 = %23d, downshifted = %23d\n", dst_wdata2, dst_wdata2 >> 1); + $write("dst_wdata3 = %23d, downshifted = %23d\n", dst_wdata3, dst_wdata3 >> 1); + $write("dst_wdata4 = %23d, downshifted = %23d\n", dst_wdata4, dst_wdata4 >> 1); + $write("dst_wdata5 = %23d, downshifted = %23d\n", dst_wdata5, dst_wdata5 >> 1); + $write("dst_wdata6 = %23d, downshifted = %23d\n", dst_wdata6, dst_wdata6 >> 1); + $write("dst_wdata7 = %23d, downshifted = %23d\n", dst_wdata7, dst_wdata7 >> 1); - if (dstwide1 !== 70'd0 || (dstwide1 >> 1) !== 70'd0) $stop; - if (dstwide2 !== 70'd0 || (dstwide2 >> 1) !== 70'd0) $stop; - if (dstnarrow !== 2'd0 || (dstnarrow >> 1) !== 2'd0) $stop; - if (dst_cdata !== 3'd0 || (dst_cdata >> 1) !== 3'd0) $stop; - if (dst_sdata !== 12'd0 || (dst_sdata >> 1) !== 12'd0) $stop; - if (dst_idata !== 30'd0 || (dst_idata >> 1) !== 30'd0) $stop; - if (dst_qdata !== 60'd0 || (dst_qdata >> 1) !== 60'd0) $stop; - if (dst_wdata1 !== 70'd0 || (dst_wdata1 >> 1) !== 70'd0) $stop; - if (dst_wdata2 !== 70'd0 || (dst_wdata2 >> 1) !== 70'd0) $stop; - if (dst_wdata3 !== 70'd0 || (dst_wdata3 >> 1) !== 70'd0) $stop; - if (dst_wdata4 !== 70'd0 || (dst_wdata4 >> 1) !== 70'd0) $stop; - if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop; - if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop; - if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop; - end else begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (dstwide1 !== 70'd0 || (dstwide1 >> 1) !== 70'd0) $stop; + if (dstwide2 !== 70'd0 || (dstwide2 >> 1) !== 70'd0) $stop; + if (dstnarrow !== 2'd0 || (dstnarrow >> 1) !== 2'd0) $stop; + if (dst_cdata !== 3'd0 || (dst_cdata >> 1) !== 3'd0) $stop; + if (dst_sdata !== 12'd0 || (dst_sdata >> 1) !== 12'd0) $stop; + if (dst_idata !== 30'd0 || (dst_idata >> 1) !== 30'd0) $stop; + if (dst_qdata !== 60'd0 || (dst_qdata >> 1) !== 60'd0) $stop; + if (dst_wdata1 !== 70'd0 || (dst_wdata1 >> 1) !== 70'd0) $stop; + if (dst_wdata2 !== 70'd0 || (dst_wdata2 >> 1) !== 70'd0) $stop; + if (dst_wdata3 !== 70'd0 || (dst_wdata3 >> 1) !== 70'd0) $stop; + if (dst_wdata4 !== 70'd0 || (dst_wdata4 >> 1) !== 70'd0) $stop; + if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop; + if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop; + if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end - cyc <= cyc + 1; - end + cyc <= cyc + 1; + end endmodule diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.out b/test_regress/t/t_assigndly_dynamic_notiming_bad.out index 687d05541..9712a069f 100644 --- a/test_regress/t/t_assigndly_dynamic_notiming_bad.out +++ b/test_regress/t/t_assigndly_dynamic_notiming_bad.out @@ -1,6 +1,6 @@ -%Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:11: Delayed assignment in a non-inlined function/task requires --timing - : ... note: In instance '$unit::Cls' - 10 | qux <= '1; - | ^~ +%Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:9: Delayed assignment in a non-inlined function/task requires --timing + : ... note: In instance '$unit::Cls' + 10 | qux <= '1; + | ^~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.v b/test_regress/t/t_assigndly_dynamic_notiming_bad.v index 818f9378f..a089f302b 100644 --- a/test_regress/t/t_assigndly_dynamic_notiming_bad.v +++ b/test_regress/t/t_assigndly_dynamic_notiming_bad.v @@ -5,19 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - task bar; - static int qux; - qux <= '1; - // Use qux to prevent V3Dead optimizations - $display("qux = %d\n", qux); - endtask + task bar; + static int qux; + qux <= '1; + // Use qux to prevent V3Dead optimizations + $display("qux = %d\n", qux); + endtask endclass module t; - initial begin - Cls c; - c.bar(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + c.bar(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assigndly_task.v b/test_regress/t/t_assigndly_task.v index 6a7f4f63b..c8570b0ab 100644 --- a/test_regress/t/t_assigndly_task.v +++ b/test_regress/t/t_assigndly_task.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - input clk, - input [7:0] d, - input [2:0] a, - output [7:0] q + input clk, + input [7:0] d, + input [2:0] a, + output [7:0] q ); always_ff @(posedge clk) tick(a); diff --git a/test_regress/t/t_assoc.v b/test_regress/t/t_assoc.v index 1f9d9b5a9..dd47f92a1 100644 --- a/test_regress/t/t_assoc.v +++ b/test_regress/t/t_assoc.v @@ -4,149 +4,196 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - integer i; + integer i; - always @ (posedge clk) begin - cyc <= cyc + 1; - begin - // Type - typedef bit [3:0] nibble_t; - typedef string dict_t [nibble_t]; - dict_t a; - string b [nibble_t]; - nibble_t k; - string v; + always @(posedge clk) begin + cyc <= cyc + 1; + begin + // Type + typedef bit [3:0] nibble_t; + typedef string dict_t[nibble_t]; + dict_t a; + string b[nibble_t]; + nibble_t k; + string v; - a[4'd3] = "fooed"; - a[4'd2] = "bared"; - i = a.num(); `checkh(i, 2); - i = a.size; `checkh(i, 2); // Also checks no parens - v = a[4'd3]; `checks(v, "fooed"); - v = a[4'd2]; `checks(v, "bared"); - i = a.exists(4'd0); `checkh(i, 0); - if (a.exists(4'd0)) $stop; // Check no width warning - i = a.exists(4'd2); `checkh(i, 1); - if (!a.exists(4'd2)) $stop; // Check no width warning - i = a.first(k); `checkh(i, 1); `checks(k, 4'd2); - i = a.next(k); `checkh(i, 1); `checks(k, 4'd3); - i = a.next(k); `checkh(i, 0); - i = a.last(k); `checkh(i, 1); `checks(k, 4'd3); - i = a.prev(k); `checkh(i, 1); `checks(k, 4'd2); - i = a.prev(k); `checkh(i, 0); - `checkp(a, "'{'h2:\"bared\", 'h3:\"fooed\"}"); + a[4'd3] = "fooed"; + a[4'd2] = "bared"; + i = a.num(); + `checkh(i, 2); + i = a.size; + `checkh(i, 2); // Also checks no parens + v = a[4'd3]; + `checks(v, "fooed"); + v = a[4'd2]; + `checks(v, "bared"); + i = a.exists(4'd0); + `checkh(i, 0); + if (a.exists(4'd0)) $stop; // Check no width warning + i = a.exists(4'd2); + `checkh(i, 1); + if (!a.exists(4'd2)) $stop; // Check no width warning + i = a.first(k); + `checkh(i, 1); + `checks(k, 4'd2); + i = a.next(k); + `checkh(i, 1); + `checks(k, 4'd3); + i = a.next(k); + `checkh(i, 0); + i = a.last(k); + `checkh(i, 1); + `checks(k, 4'd3); + i = a.prev(k); + `checkh(i, 1); + `checks(k, 4'd2); + i = a.prev(k); + `checkh(i, 0); + `checkp(a, "'{'h2:\"bared\", 'h3:\"fooed\"}"); - a.first(k); `checks(k, 4'd2); - a.next(k); `checks(k, 4'd3); - a.next(k); - a.last(k); `checks(k, 4'd3); - a.prev(k); `checks(k, 4'd2); + a.first(k); + `checks(k, 4'd2); + a.next(k); + `checks(k, 4'd3); + a.next(k); + a.last(k); + `checks(k, 4'd3); + a.prev(k); + `checks(k, 4'd2); - a.delete(4'd2); - i = a.size(); `checkh(i, 1); + a.delete(4'd2); + i = a.size(); + `checkh(i, 1); - b = a; // Copy assignment - i = b.size(); `checkh(i, 1); - end + b = a; // Copy assignment + i = b.size(); + `checkh(i, 1); + end - begin - // Strings - string a [string]; - string k; - string v; + begin + // Strings + string a[string]; + string k; + string v; - a["foo"] = "fooed"; - a["bar"] = "bared"; - i = a.num(); `checkh(i, 2); - i = a.size(); `checkh(i, 2); - v = a["foo"]; `checks(v, "fooed"); - v = a["bar"]; `checks(v, "bared"); - i = a.exists("baz"); `checkh(i, 0); - i = a.exists("bar"); `checkh(i, 1); - i = a.first(k); `checkh(i, 1); `checks(k, "bar"); - i = a.next(k); `checkh(i, 1); `checks(k, "foo"); - i = a.next(k); `checkh(i, 0); - i = a.last(k); `checkh(i, 1); `checks(k, "foo"); - i = a.prev(k); `checkh(i, 1); `checks(k, "bar"); - i = a.prev(k); `checkh(i, 0); - `checkp(a["foo"], "\"fooed\""); - `checkp(a, "'{\"bar\":\"bared\", \"foo\":\"fooed\"}"); + a["foo"] = "fooed"; + a["bar"] = "bared"; + i = a.num(); + `checkh(i, 2); + i = a.size(); + `checkh(i, 2); + v = a["foo"]; + `checks(v, "fooed"); + v = a["bar"]; + `checks(v, "bared"); + i = a.exists("baz"); + `checkh(i, 0); + i = a.exists("bar"); + `checkh(i, 1); + i = a.first(k); + `checkh(i, 1); + `checks(k, "bar"); + i = a.next(k); + `checkh(i, 1); + `checks(k, "foo"); + i = a.next(k); + `checkh(i, 0); + i = a.last(k); + `checkh(i, 1); + `checks(k, "foo"); + i = a.prev(k); + `checkh(i, 1); + `checks(k, "bar"); + i = a.prev(k); + `checkh(i, 0); + `checkp(a["foo"], "\"fooed\""); + `checkp(a, "'{\"bar\":\"bared\", \"foo\":\"fooed\"}"); - a.delete("bar"); - i = a.size(); `checkh(i, 1); - a.delete(); - i = a.size(); `checkh(i, 0); - i = a.first(k); `checkh(i, 0); - i = a.last(k); `checkh(i, 0); + a.delete("bar"); + i = a.size(); + `checkh(i, 1); + a.delete(); + i = a.size(); + `checkh(i, 0); + i = a.first(k); + `checkh(i, 0); + i = a.last(k); + `checkh(i, 0); - // Patterns & default - a = '{ "f": "fooed", "b": "bared", default: "defaulted" }; - i = a.size(); `checkh(i, 2); // Default doesn't count - v = a["f"]; `checks(v, "fooed"); - v = a["b"]; `checks(v, "bared"); - v = a["NEXISTS"]; `checks(v, "defaulted"); + // Patterns & default + a = '{"f": "fooed", "b": "bared", default: "defaulted"}; + i = a.size(); + `checkh(i, 2); // Default doesn't count + v = a["f"]; + `checks(v, "fooed"); + v = a["b"]; + `checks(v, "bared"); + v = a["NEXISTS"]; + `checks(v, "defaulted"); - a = '{}; - i = a.size(); `checkh(i, 0); - end + a = '{}; + i = a.size(); + `checkh(i, 0); + end - begin - // Wide-wides - need special array container classes, ick. - logic [91:2] a [ logic [65:1] ]; - int b [ bit [99:0] ]; - a[~65'hfe] = ~ 90'hfee; - `checkh(a[~65'hfe], ~ 90'hfee); - b[100'b1] = 1; - `checkh(b[100'b1], 1); - end + begin + // Wide-wides - need special array container classes, ick. + logic [91:2] a[logic [65:1]]; + int b[bit [99:0]]; + a[~65'hfe] = ~90'hfee; + `checkh(a[~65'hfe], ~90'hfee); + b[100'b1] = 1; + `checkh(b[100'b1], 1); + end - begin - int a [string]; - int sum; - sum = 0; - a["one"] = 1; - a["two"] = 2; - foreach (a[i]) sum += a[i]; - `checkh(sum, 1 + 2); - end + begin + int a[string]; + int sum; + sum = 0; + a["one"] = 1; + a["two"] = 2; + foreach (a[i]) sum += a[i]; + `checkh(sum, 1 + 2); + end - begin // Issue #5435 - int a; - int ok; - int dict [int]; + begin // Issue #5435 + int a; + int ok; + int dict[int]; - dict[3] = 'h13; - dict[4] = 'h14; - dict[5] = 'h15; + dict[3] = 'h13; + dict[4] = 'h14; + dict[5] = 'h15; - a = 4; - ok = dict.first(a); - if (a != 3) $stop; - if (ok != 1) $stop; - a = 4; - ok = dict.next(a); - if (a != 5) $stop; - if (ok != 1) $stop; - a = 4; - ok = dict.last(a); - if (a != 5) $stop; - if (ok != 1) $stop; - end + a = 4; + ok = dict.first(a); + if (a != 3) $stop; + if (ok != 1) $stop; + a = 4; + ok = dict.next(a); + if (a != 5) $stop; + if (ok != 1) $stop; + a = 4; + ok = dict.last(a); + if (a != 5) $stop; + if (ok != 1) $stop; + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assoc2.v b/test_regress/t/t_assoc2.v index 42deb93c1..5601e54df 100644 --- a/test_regress/t/t_assoc2.v +++ b/test_regress/t/t_assoc2.v @@ -4,45 +4,45 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - int imap[int]; + int imap[int]; - // associative array of an associative array - logic [31:0] a [logic [31:0]][logic [63:0]]; + // associative array of an associative array + logic [31:0] a[logic [31:0]][logic [63:0]]; - task static disp(); - int i = 60; - imap[i++] = 600; - imap[i++] = 601; - foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]); - endtask + task static disp(); + int i = 60; + imap[i++] = 600; + imap[i++] = 601; + foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]); + endtask - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - a[5][8] = 8; - a[5][9] = 9; - imap[10] = 100; - imap[11] = 101; - end - else if (cyc == 2) begin - `checkh(a[5][8], 8); - `checkh(a[5][9], 9); - disp(); - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + a[5][8] = 8; + a[5][9] = 9; + imap[10] = 100; + imap[11] = 101; + end + else if (cyc == 2) begin + `checkh(a[5][8], 8); + `checkh(a[5][9], 9); + disp(); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_assoc_compare.v b/test_regress/t/t_assoc_compare.v index ce4923359..d25036970 100644 --- a/test_regress/t/t_assoc_compare.v +++ b/test_regress/t/t_assoc_compare.v @@ -4,64 +4,66 @@ // SPDX-FileCopyrightText: 2023 Ilya Barkov // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end +`define check_comp(lhs, rhs, op, expv) if ((expv) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (expv)); `stop; end // Two checks because == and != may not be derived from each other `define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0) `define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1) +// verilog_format: on class Cls; - int i; + int i; endclass module t; - initial begin - begin // simple case - int assoc1[int]; - int assoc2[int]; - // Empty are equal - `check_eq(assoc1, assoc2) - // Make different - assoc1[10] = 15; - assoc2[-1] = 365; - `check_ne(assoc1, assoc2) - // Make same - assoc1[-1] = 365; - assoc2[10] = 15; - `check_eq(assoc1, assoc2) - // Don't actually change - assoc1[-1] = 365; - `check_eq(assoc1, assoc2) - // Compare different sizes - assoc1[3] = 0; - `check_ne(assoc1, assoc2) - end - begin // check that a class as key is fine - int assoc1[Cls]; - int assoc2[Cls]; - automatic Cls a = new; - automatic Cls b = new; - int t; - assoc1[a] = 0; - `check_ne(assoc1, assoc2) - assoc2[a] = 0; - `check_eq(assoc1, assoc2) - assoc2.delete(a); - assoc2[b] = 0; - `check_ne(assoc1, assoc2) - end - begin // check that a class as value is fine - Cls assoc1[int]; - Cls assoc2[int]; - automatic Cls a = new; - automatic Cls b = new; - assoc1[1] = a; - assoc2[1] = b; - `check_ne(assoc1, assoc2) - assoc2[1] = a; - `check_eq(assoc1, assoc2) - end - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + begin // simple case + int assoc1[int]; + int assoc2[int]; + // Empty are equal + `check_eq(assoc1, assoc2) + // Make different + assoc1[10] = 15; + assoc2[-1] = 365; + `check_ne(assoc1, assoc2) + // Make same + assoc1[-1] = 365; + assoc2[10] = 15; + `check_eq(assoc1, assoc2) + // Don't actually change + assoc1[-1] = 365; + `check_eq(assoc1, assoc2) + // Compare different sizes + assoc1[3] = 0; + `check_ne(assoc1, assoc2) + end + begin // check that a class as key is fine + int assoc1[Cls]; + int assoc2[Cls]; + automatic Cls a = new; + automatic Cls b = new; + int t; + assoc1[a] = 0; + `check_ne(assoc1, assoc2) + assoc2[a] = 0; + `check_eq(assoc1, assoc2) + assoc2.delete(a); + assoc2[b] = 0; + `check_ne(assoc1, assoc2) + end + begin // check that a class as value is fine + Cls assoc1[int]; + Cls assoc2[int]; + automatic Cls a = new; + automatic Cls b = new; + assoc1[1] = a; + assoc2[1] = b; + `check_ne(assoc1, assoc2) + assoc2[1] = a; + `check_eq(assoc1, assoc2) + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assoc_enum.v b/test_regress/t/t_assoc_enum.v index 79de64a4d..3ae1af9f8 100644 --- a/test_regress/t/t_assoc_enum.v +++ b/test_regress/t/t_assoc_enum.v @@ -11,25 +11,31 @@ // verilog_format: on class X; - typedef enum int { - INITIAL, RUNNING, SUSPENDED, COMPLETING, DONE - } state_t; + typedef enum int { + INITIAL, + RUNNING, + SUSPENDED, + COMPLETING, + DONE + } state_t; - static string state_names[state_t] = '{ - INITIAL: "INITIAL", - RUNNING: "RUNNING", - SUSPENDED: "SUSPENDED", - COMPLETING: "COMPLETING", - DONE: "DONE" - }; - protected state_t state; + static + string + state_names[state_t] = '{ + INITIAL: "INITIAL", + RUNNING: "RUNNING", + SUSPENDED: "SUSPENDED", + COMPLETING: "COMPLETING", + DONE: "DONE" + }; + protected state_t state; - function new(); - this.state = INITIAL; - `checks(state_names[this.state], "INITIAL"); - this.state = RUNNING; - `checks(state_names[this.state], "RUNNING"); - endfunction + function new(); + this.state = INITIAL; + `checks(state_names[this.state], "INITIAL"); + this.state = RUNNING; + `checks(state_names[this.state], "RUNNING"); + endfunction endclass diff --git a/test_regress/t/t_assoc_method.v b/test_regress/t/t_assoc_method.v index cadc9809b..82e4970a6 100644 --- a/test_regress/t/t_assoc_method.v +++ b/test_regress/t/t_assoc_method.v @@ -4,10 +4,11 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); - +// verilog_format: on module t; typedef struct {int x, y;} point; @@ -51,7 +52,7 @@ module t; points_q[1] = point'{2, 4}; points_q[5] = point'{1, 4}; - points_qv = points_q.unique(p) with (p.x); + points_qv = points_q.unique(p) with (p.x); `checkh(points_qv.size, 2); qi = points_q.unique_index (p) with (p.x + p.y); qi.sort; @@ -189,7 +190,7 @@ module t; i = qe.xor(); `checkh(i, 32'b0); - q = '{10: 1, 11: 2}; + q = '{10: 1, 11: 2}; qe = '{10: 1, 11: 2}; `checkh(q == qe, 1'b1); `checkh(q != qe, 1'b0); diff --git a/test_regress/t/t_assoc_method_bad.out b/test_regress/t/t_assoc_method_bad.out index 101bd8f61..6d4dc09c5 100644 --- a/test_regress/t/t_assoc_method_bad.out +++ b/test_regress/t/t_assoc_method_bad.out @@ -1,67 +1,67 @@ -%Error: t/t_assoc_method_bad.v:14:13: The 1 arguments passed to .num method does not match its requiring 0 arguments +%Error: t/t_assoc_method_bad.v:14:11: The 1 arguments passed to .num method does not match its requiring 0 arguments : ... note: In instance 't' - 14 | v = a.num("badarg"); - | ^~~ + 14 | v = a.num("badarg"); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_assoc_method_bad.v:15:13: The 1 arguments passed to .size method does not match its requiring 0 arguments +%Error: t/t_assoc_method_bad.v:15:11: The 1 arguments passed to .size method does not match its requiring 0 arguments : ... note: In instance 't' - 15 | v = a.size("badarg"); - | ^~~~ -%Error: t/t_assoc_method_bad.v:16:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments + 15 | v = a.size("badarg"); + | ^~~~ +%Error: t/t_assoc_method_bad.v:16:11: The 0 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' - 16 | v = a.exists(); - | ^~~~~~ -%Error: t/t_assoc_method_bad.v:17:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments + 16 | v = a.exists(); + | ^~~~~~ +%Error: t/t_assoc_method_bad.v:17:11: The 2 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' - 17 | v = a.exists(k, "bad2"); - | ^~~~~~ -%Error: t/t_assoc_method_bad.v:18:13: The 0 arguments passed to .first method does not match its requiring 1 arguments + 17 | v = a.exists(k, "bad2"); + | ^~~~~~ +%Error: t/t_assoc_method_bad.v:18:11: The 0 arguments passed to .first method does not match its requiring 1 arguments : ... note: In instance 't' - 18 | v = a.first(); - | ^~~~~ -%Error-UNSUPPORTED: t/t_assoc_method_bad.v:18:13: Unsupported: Non-variable on LHS of built-in method 'first' + 18 | v = a.first(); + | ^~~~~ +%Error-UNSUPPORTED: t/t_assoc_method_bad.v:18:11: Unsupported: Non-variable on LHS of built-in method 'first' : ... note: In instance 't' - 18 | v = a.first(); - | ^~~~~ + 18 | v = a.first(); + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_assoc_method_bad.v:19:13: The 2 arguments passed to .next method does not match its requiring 1 arguments +%Error: t/t_assoc_method_bad.v:19:11: The 2 arguments passed to .next method does not match its requiring 1 arguments : ... note: In instance 't' - 19 | v = a.next(k, "bad2"); - | ^~~~ -%Error: t/t_assoc_method_bad.v:20:13: The 0 arguments passed to .last method does not match its requiring 1 arguments + 19 | v = a.next(k, "bad2"); + | ^~~~ +%Error: t/t_assoc_method_bad.v:20:11: The 0 arguments passed to .last method does not match its requiring 1 arguments : ... note: In instance 't' - 20 | v = a.last(); - | ^~~~ -%Error-UNSUPPORTED: t/t_assoc_method_bad.v:20:13: Unsupported: Non-variable on LHS of built-in method 'last' + 20 | v = a.last(); + | ^~~~ +%Error-UNSUPPORTED: t/t_assoc_method_bad.v:20:11: Unsupported: Non-variable on LHS of built-in method 'last' : ... note: In instance 't' - 20 | v = a.last(); - | ^~~~ -%Error: t/t_assoc_method_bad.v:21:13: The 2 arguments passed to .prev method does not match its requiring 1 arguments + 20 | v = a.last(); + | ^~~~ +%Error: t/t_assoc_method_bad.v:21:11: The 2 arguments passed to .prev method does not match its requiring 1 arguments : ... note: In instance 't' - 21 | v = a.prev(k, "bad2"); - | ^~~~ -%Error: t/t_assoc_method_bad.v:22:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments + 21 | v = a.prev(k, "bad2"); + | ^~~~ +%Error: t/t_assoc_method_bad.v:22:7: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments : ... note: In instance 't' - 22 | a.delete(k, "bad2"); - | ^~~~~~ -%Error: t/t_assoc_method_bad.v:24:9: Array method 'sort' not legal on associative arrays + 22 | a.delete(k, "bad2"); + | ^~~~~~ +%Error: t/t_assoc_method_bad.v:24:7: Array method 'sort' not legal on associative arrays : ... note: In instance 't' - 24 | a.sort; - | ^~~~ -%Error: t/t_assoc_method_bad.v:25:9: Array method 'rsort' not legal on associative arrays + 24 | a.sort; + | ^~~~ +%Error: t/t_assoc_method_bad.v:25:7: Array method 'rsort' not legal on associative arrays : ... note: In instance 't' - 25 | a.rsort; - | ^~~~~ -%Error: t/t_assoc_method_bad.v:26:9: Array method 'reverse' not legal on associative arrays + 25 | a.rsort; + | ^~~~~ +%Error: t/t_assoc_method_bad.v:26:7: Array method 'reverse' not legal on associative arrays : ... note: In instance 't' - 26 | a.reverse; - | ^~~~~~~ -%Error: t/t_assoc_method_bad.v:27:9: Array method 'shuffle' not legal on associative arrays + 26 | a.reverse; + | ^~~~~~~ +%Error: t/t_assoc_method_bad.v:27:7: Array method 'shuffle' not legal on associative arrays : ... note: In instance 't' - 27 | a.shuffle; - | ^~~~~~~ -%Error: t/t_assoc_method_bad.v:29:9: Unknown built-in associative array method 'bad_not_defined' + 27 | a.shuffle; + | ^~~~~~~ +%Error: t/t_assoc_method_bad.v:29:7: Unknown built-in associative array method 'bad_not_defined' : ... note: In instance 't' - 29 | a.bad_not_defined(); - | ^~~~~~~~~~~~~~~ + 29 | a.bad_not_defined(); + | ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assoc_method_bad.v b/test_regress/t/t_assoc_method_bad.v index a2dabc4ea..c118ec531 100644 --- a/test_regress/t/t_assoc_method_bad.v +++ b/test_regress/t/t_assoc_method_bad.v @@ -6,26 +6,26 @@ module t; - initial begin - string a [string]; - string k; - string v; + initial begin + string a[string]; + string k; + string v; - v = a.num("badarg"); - v = a.size("badarg"); - v = a.exists(); // Bad - v = a.exists(k, "bad2"); - v = a.first(); // Bad - v = a.next(k, "bad2"); // Bad - v = a.last(); // Bad - v = a.prev(k, "bad2"); // Bad - a.delete(k, "bad2"); + v = a.num("badarg"); + v = a.size("badarg"); + v = a.exists(); // Bad + v = a.exists(k, "bad2"); + v = a.first(); // Bad + v = a.next(k, "bad2"); // Bad + v = a.last(); // Bad + v = a.prev(k, "bad2"); // Bad + a.delete(k, "bad2"); - a.sort; // Not legal on assoc - a.rsort; // Not legal on assoc - a.reverse; // Not legal on assoc - a.shuffle; // Not legal on assoc + a.sort; // Not legal on assoc + a.rsort; // Not legal on assoc + a.reverse; // Not legal on assoc + a.shuffle; // Not legal on assoc - a.bad_not_defined(); - end + a.bad_not_defined(); + end endmodule diff --git a/test_regress/t/t_assoc_method_map.out b/test_regress/t/t_assoc_method_map.out index 61d553d8b..62dd71bbc 100644 --- a/test_regress/t/t_assoc_method_map.out +++ b/test_regress/t/t_assoc_method_map.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_assoc_method_map.v:17:15: Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5) +%Error-UNSUPPORTED: t/t_assoc_method_map.v:19:13: Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' - 17 | res = a.map(el) with (el == 2); - | ^~~ + 19 | res = a.map(el) with (el == 2); + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assoc_method_map.v b/test_regress/t/t_assoc_method_map.v index c01a19a30..829b0baaf 100644 --- a/test_regress/t/t_assoc_method_map.v +++ b/test_regress/t/t_assoc_method_map.v @@ -4,20 +4,22 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - initial begin - automatic int res[]; - automatic int a[int] = '{1: 100, 2: 200, 3: 300}; + initial begin + automatic int res[]; + automatic int a[int] = '{1: 100, 2: 200, 3: 300}; - // TODO results not known to be correct - res = a.map(el) with (el == 2); - `checkh(res.size, 3); - `checkh(res[0], 0); - `checkh(res[1], 1); - `checkh(res[2], 0); - end + // TODO results not known to be correct + res = a.map(el) with (el == 2); + `checkh(res.size, 3); + `checkh(res[0], 0); + `checkh(res[1], 1); + `checkh(res[2], 0); + end endmodule diff --git a/test_regress/t/t_assoc_ref_type.v b/test_regress/t/t_assoc_ref_type.v index 276f98893..3b2f83dce 100644 --- a/test_regress/t/t_assoc_ref_type.v +++ b/test_regress/t/t_assoc_ref_type.v @@ -5,87 +5,91 @@ // SPDX-License-Identifier: CC0-1.0 class Foo1; - int x = 1; - function int get_x; - return x; - endfunction + int x = 1; + function int get_x; + return x; + endfunction endclass class Foo2; - int x = 2; - function int get_x; - return x; - endfunction + int x = 2; + function int get_x; + return x; + endfunction endclass class Bar; - typedef Foo1 foo_t; - protected foo_t m_dict[int]; + typedef Foo1 foo_t; + protected foo_t m_dict[int]; - function void set(int key); - foo_t default_value = new; - m_dict[key] = default_value; - endfunction - function foo_t get(int key); - return m_dict[key]; - endfunction + function void set(int key); + foo_t default_value = new; + m_dict[key] = default_value; + endfunction + function foo_t get(int key); + return m_dict[key]; + endfunction endclass -class Baz #(type T=Foo1); +class Baz #( + type T = Foo1 +); protected T m_dict[int]; function void set(int key); - T default_value = new; - m_dict[key] = default_value; - endfunction - function T get(int key); - return m_dict[key]; - endfunction + T default_value = new; + m_dict[key] = default_value; + endfunction + function T get(int key); + return m_dict[key]; + endfunction endclass class WBase; endclass -class Wrapper#(type VAL_T=int); - VAL_T value; +class Wrapper #( + type VAL_T = int +); + VAL_T value; endclass class Bum; - typedef int map_t[string]; - map_t m_value; - function new(map_t value); - m_value = value; - endfunction + typedef int map_t[string]; + map_t m_value; + function new(map_t value); + m_value = value; + endfunction endclass module t; - typedef WBase wrap_map_t[string]; - typedef WBase wrap_queue_t[$]; + typedef WBase wrap_map_t[string]; + typedef WBase wrap_queue_t[$]; - localparam string str_key = "the_key"; + localparam string str_key = "the_key"; - initial begin - automatic Bar bar_i = new; - automatic Baz baz_1_i = new; - automatic Baz #(Foo2) baz_2_i = new; - automatic Bum bum_i; + initial begin + automatic Bar bar_i = new; + automatic Baz baz_1_i = new; + automatic Baz #(Foo2) baz_2_i = new; + automatic Bum bum_i; - automatic Wrapper#(wrap_map_t) wrap_map = new(); - automatic Wrapper#(wrap_queue_t) wrap_queue = new(); + automatic Wrapper #(wrap_map_t) wrap_map = new(); + automatic Wrapper #(wrap_queue_t) wrap_queue = new(); - bar_i.set(1); - baz_1_i.set(2); - baz_2_i.set(3); + bar_i.set(1); + baz_1_i.set(2); + baz_2_i.set(3); - if (bar_i.get(1).get_x() != 1) $stop; - if (baz_1_i.get(2).get_x() != 1) $stop; - if (baz_2_i.get(3).get_x() != 2) $stop; + if (bar_i.get(1).get_x() != 1) $stop; + if (baz_1_i.get(2).get_x() != 1) $stop; + if (baz_2_i.get(3).get_x() != 2) $stop; - bum_i = new('{str_key: 42}); - if (bum_i.m_value["the_key"] != 42) $stop; + bum_i = new('{str_key: 42}); + if (bum_i.m_value["the_key"] != 42) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assoc_wildcard.v b/test_regress/t/t_assoc_wildcard.v index 002ae3549..257b579da 100644 --- a/test_regress/t/t_assoc_wildcard.v +++ b/test_regress/t/t_assoc_wildcard.v @@ -4,51 +4,63 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - integer i; + integer i; - always @ (posedge clk) begin - cyc <= cyc + 1; - begin - // Wildcard - typedef string dict_t [*]; - static string a [*] = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; - static dict_t b = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; - int k; - string v; + always @(posedge clk) begin + cyc <= cyc + 1; + begin + // Wildcard + typedef string dict_t [*]; + static string a [*] = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; + static dict_t b = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; + int k; + string v; - v = b["CCC"]; `checks(v, "baring"); - v = b["BBBBB"]; `checks(v, "fooing"); + v = b["CCC"]; + `checks(v, "baring"); + v = b["BBBBB"]; + `checks(v, "fooing"); - v = a["CCC"]; `checks(v, "baring"); - v = a["BBBBB"]; `checks(v, "fooing"); + v = a["CCC"]; + `checks(v, "baring"); + v = a["BBBBB"]; + `checks(v, "fooing"); - a[32'd1234] = "fooed"; - a[4'd3] = "bared"; - a[79'h4141] = "bazed"; - i = a.num(); `checkh(i, 5); - i = a.size(); `checkh(i, 5); - v = a[39'd1234]; `checks(v, "fooed"); - v = a["AA"]; `checks(v, "bazed"); - v = a[4'd3]; `checks(v, "bared"); - i = a.exists("baz"); `checkh(i, 0); - i = a.exists(4'd3); `checkh(i, 1); - a.delete(4'd3); - i = a.size(); `checkh(i, 4); - end + a[32'd1234] = "fooed"; + a[4'd3] = "bared"; + a[79'h4141] = "bazed"; + i = a.num(); + `checkh(i, 5); + i = a.size(); + `checkh(i, 5); + v = a[39'd1234]; + `checks(v, "fooed"); + v = a["AA"]; + `checks(v, "bazed"); + v = a[4'd3]; + `checks(v, "bared"); + i = a.exists("baz"); + `checkh(i, 0); + i = a.exists(4'd3); + `checkh(i, 1); + a.delete(4'd3); + i = a.size(); + `checkh(i, 4); + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assoc_wildcard_bad.out b/test_regress/t/t_assoc_wildcard_bad.out index a76182730..58322f10b 100644 --- a/test_regress/t/t_assoc_wildcard_bad.out +++ b/test_regress/t/t_assoc_wildcard_bad.out @@ -1,78 +1,78 @@ -%Error: t/t_assoc_wildcard_bad.v:23:13: The 1 arguments passed to .num method does not match its requiring 0 arguments +%Error: t/t_assoc_wildcard_bad.v:23:11: The 1 arguments passed to .num method does not match its requiring 0 arguments : ... note: In instance 't' - 23 | v = a.num("badarg"); - | ^~~ + 23 | v = a.num("badarg"); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_assoc_wildcard_bad.v:24:13: The 1 arguments passed to .size method does not match its requiring 0 arguments +%Error: t/t_assoc_wildcard_bad.v:24:11: The 1 arguments passed to .size method does not match its requiring 0 arguments : ... note: In instance 't' - 24 | v = a.size("badarg"); - | ^~~~ -%Error: t/t_assoc_wildcard_bad.v:25:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments + 24 | v = a.size("badarg"); + | ^~~~ +%Error: t/t_assoc_wildcard_bad.v:25:11: The 0 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' - 25 | v = a.exists(); - | ^~~~~~ -%Error: t/t_assoc_wildcard_bad.v:26:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments + 25 | v = a.exists(); + | ^~~~~~ +%Error: t/t_assoc_wildcard_bad.v:26:11: The 2 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' - 26 | v = a.exists(k, "bad2"); - | ^~~~~~ -%Error: t/t_assoc_wildcard_bad.v:27:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments + 26 | v = a.exists(k, "bad2"); + | ^~~~~~ +%Error: t/t_assoc_wildcard_bad.v:27:7: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments : ... note: In instance 't' - 27 | a.delete(k, "bad2"); - | ^~~~~~ -%Error: t/t_assoc_wildcard_bad.v:29:9: Array method 'sort' not legal on associative arrays + 27 | a.delete(k, "bad2"); + | ^~~~~~ +%Error: t/t_assoc_wildcard_bad.v:29:7: Array method 'sort' not legal on associative arrays : ... note: In instance 't' - 29 | a.sort; - | ^~~~ -%Error: t/t_assoc_wildcard_bad.v:30:9: Array method 'rsort' not legal on associative arrays + 29 | a.sort; + | ^~~~ +%Error: t/t_assoc_wildcard_bad.v:30:7: Array method 'rsort' not legal on associative arrays : ... note: In instance 't' - 30 | a.rsort; - | ^~~~~ -%Error: t/t_assoc_wildcard_bad.v:31:9: Array method 'reverse' not legal on associative arrays + 30 | a.rsort; + | ^~~~~ +%Error: t/t_assoc_wildcard_bad.v:31:7: Array method 'reverse' not legal on associative arrays : ... note: In instance 't' - 31 | a.reverse; - | ^~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:32:9: Array method 'shuffle' not legal on associative arrays + 31 | a.reverse; + | ^~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:32:7: Array method 'shuffle' not legal on associative arrays : ... note: In instance 't' - 32 | a.shuffle; - | ^~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:34:9: Array method 'first' not legal on wildcard associative arrays + 32 | a.shuffle; + | ^~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:34:7: Array method 'first' not legal on wildcard associative arrays : ... note: In instance 't' - 34 | a.first; - | ^~~~~ -%Error: t/t_assoc_wildcard_bad.v:35:9: Array method 'last' not legal on wildcard associative arrays + 34 | a.first; + | ^~~~~ +%Error: t/t_assoc_wildcard_bad.v:35:7: Array method 'last' not legal on wildcard associative arrays : ... note: In instance 't' - 35 | a.last; - | ^~~~ -%Error: t/t_assoc_wildcard_bad.v:36:9: Array method 'next' not legal on wildcard associative arrays + 35 | a.last; + | ^~~~ +%Error: t/t_assoc_wildcard_bad.v:36:7: Array method 'next' not legal on wildcard associative arrays : ... note: In instance 't' - 36 | a.next; - | ^~~~ -%Error: t/t_assoc_wildcard_bad.v:37:9: Array method 'prev' not legal on wildcard associative arrays + 36 | a.next; + | ^~~~ +%Error: t/t_assoc_wildcard_bad.v:37:7: Array method 'prev' not legal on wildcard associative arrays : ... note: In instance 't' - 37 | a.prev; - | ^~~~ -%Error: t/t_assoc_wildcard_bad.v:38:9: Array method 'unique_index' not legal on wildcard associative arrays + 37 | a.prev; + | ^~~~ +%Error: t/t_assoc_wildcard_bad.v:38:7: Array method 'unique_index' not legal on wildcard associative arrays : ... note: In instance 't' - 38 | a.unique_index; - | ^~~~~~~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:39:9: Array method 'find_index' not legal on wildcard associative arrays + 38 | a.unique_index; + | ^~~~~~~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:39:7: Array method 'find_index' not legal on wildcard associative arrays : ... note: In instance 't' - 39 | a.find_index; - | ^~~~~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:40:9: Array method 'find_first_index' not legal on wildcard associative arrays + 39 | a.find_index; + | ^~~~~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:40:7: Array method 'find_first_index' not legal on wildcard associative arrays : ... note: In instance 't' - 40 | a.find_first_index; - | ^~~~~~~~~~~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:41:9: Array method 'find_last_index' not legal on wildcard associative arrays + 40 | a.find_first_index; + | ^~~~~~~~~~~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:41:7: Array method 'find_last_index' not legal on wildcard associative arrays : ... note: In instance 't' - 41 | a.find_last_index; - | ^~~~~~~~~~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:43:8: Wildcard index must be integral (IEEE 1800-2023 7.8.1) + 41 | a.find_last_index; + | ^~~~~~~~~~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:43:6: Wildcard index must be integral (IEEE 1800-2023 7.8.1) : ... note: In instance 't' - 43 | a[x] = "bad"; - | ^ -%Error: t/t_assoc_wildcard_bad.v:45:9: Unknown wildcard associative array method 'bad_not_defined' + 43 | a[x] = "bad"; + | ^ +%Error: t/t_assoc_wildcard_bad.v:45:7: Unknown wildcard associative array method 'bad_not_defined' : ... note: In instance 't' - 45 | a.bad_not_defined(); - | ^~~~~~~~~~~~~~~ + 45 | a.bad_not_defined(); + | ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assoc_wildcard_bad.v b/test_regress/t/t_assoc_wildcard_bad.v index f8e7c6f01..4ce772a39 100644 --- a/test_regress/t/t_assoc_wildcard_bad.v +++ b/test_regress/t/t_assoc_wildcard_bad.v @@ -7,41 +7,41 @@ typedef class Cls; class Cls; - integer imembera; - integer imemberb; + integer imembera; + integer imemberb; endclass : Cls module t; - initial begin - string a [*]; - string k; - string v; + initial begin + string a [*]; + string k; + string v; - Cls x; + Cls x; - v = a.num("badarg"); - v = a.size("badarg"); - v = a.exists(); // Bad - v = a.exists(k, "bad2"); - a.delete(k, "bad2"); + v = a.num("badarg"); + v = a.size("badarg"); + v = a.exists(); // Bad + v = a.exists(k, "bad2"); + a.delete(k, "bad2"); - a.sort; // Not legal on assoc - a.rsort; // Not legal on assoc - a.reverse; // Not legal on assoc - a.shuffle; // Not legal on assoc + a.sort; // Not legal on assoc + a.rsort; // Not legal on assoc + a.reverse; // Not legal on assoc + a.shuffle; // Not legal on assoc - a.first; // Not legal on wildcard - a.last; // Not legal on wildcard - a.next; // Not legal on wildcard - a.prev; // Not legal on wildcard - a.unique_index; // Not legal on wildcard - a.find_index; // Not legal on wildcard - a.find_first_index; // Not legal on wildcard - a.find_last_index; // Not legal on wildcard + a.first; // Not legal on wildcard + a.last; // Not legal on wildcard + a.next; // Not legal on wildcard + a.prev; // Not legal on wildcard + a.unique_index; // Not legal on wildcard + a.find_index; // Not legal on wildcard + a.find_first_index; // Not legal on wildcard + a.find_last_index; // Not legal on wildcard - a[x] = "bad"; + a[x] = "bad"; - a.bad_not_defined(); - end + a.bad_not_defined(); + end endmodule diff --git a/test_regress/t/t_assoc_wildcard_map.out b/test_regress/t/t_assoc_wildcard_map.out index 91dae9ed5..fadf53e84 100644 --- a/test_regress/t/t_assoc_wildcard_map.out +++ b/test_regress/t/t_assoc_wildcard_map.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5) +%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:13: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' - 19 | res = a.map(el) with (el == 2); - | ^~~ + 19 | res = a.map(el) with (el == 2); + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assoc_wildcard_map.v b/test_regress/t/t_assoc_wildcard_map.v index befe2d958..482e8a890 100644 --- a/test_regress/t/t_assoc_wildcard_map.v +++ b/test_regress/t/t_assoc_wildcard_map.v @@ -11,15 +11,15 @@ module t; - initial begin - automatic int res[]; - automatic int a [*] = '{1: 100, 2: 200, 3: 300}; + initial begin + automatic int res[]; + automatic int a [*] = '{1: 100, 2: 200, 3: 300}; - // TODO results not known to be correct - res = a.map(el) with (el == 2); - `checkh(res.size, 3); - `checkh(res[0], 0); - `checkh(res[1], 1); - `checkh(res[2], 0); - end + // TODO results not known to be correct + res = a.map(el) with (el == 2); + `checkh(res.size, 3); + `checkh(res[0], 0); + `checkh(res[1], 1); + `checkh(res[2], 0); + end endmodule diff --git a/test_regress/t/t_assoc_wildcard_method.v b/test_regress/t/t_assoc_wildcard_method.v index d9b784d2d..5c1e8ca6f 100644 --- a/test_regress/t/t_assoc_wildcard_method.v +++ b/test_regress/t/t_assoc_wildcard_method.v @@ -4,151 +4,153 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on module t; - typedef struct { int x, y; } point; + typedef struct { int x, y; } point; - function automatic int vec_len_squared(point p); - return p.x * p.x + p.y * p.y; - endfunction + function automatic int vec_len_squared(point p); + return p.x * p.x + p.y * p.y; + endfunction - initial begin - int q[*]; - int qe [ * ]; // Empty - Note spaces around [*] for parsing coverage - automatic point points_q[*] = '{"a": point'{1, 2}, "b": point'{2, 4}, "c": point'{1, 4}}; - int qv[$]; // Value returns - int qi[$]; // Index returns - int i; - bit b; - string v; + initial begin + int q[*]; + int qe [ * ]; // Empty - Note spaces around [*] for parsing coverage + automatic point points_q[*] = '{"a": point'{1, 2}, "b": point'{2, 4}, "c": point'{1, 4}}; + int qv[$]; // Value returns + int qi[$]; // Index returns + int i; + bit b; + string v; - q = '{"a":1, "b":2, "c":2, "d":4, "e":3}; - `checkp(q, "'{\"a\":'h1, \"b\":'h2, \"c\":'h2, \"d\":'h4, \"e\":'h3}"); + q = '{"a":1, "b":2, "c":2, "d":4, "e":3}; + `checkp(q, "'{\"a\":'h1, \"b\":'h2, \"c\":'h2, \"d\":'h4, \"e\":'h3}"); - // NOT tested: with ... selectors + // NOT tested: with ... selectors - //q.sort; // Not legal on assoc - see t_assoc_meth_bad - //q.rsort; // Not legal on assoc - see t_assoc_meth_bad - //q.reverse; // Not legal on assoc - see t_assoc_meth_bad - //q.shuffle; // Not legal on assoc - see t_assoc_meth_bad + //q.sort; // Not legal on assoc - see t_assoc_meth_bad + //q.rsort; // Not legal on assoc - see t_assoc_meth_bad + //q.reverse; // Not legal on assoc - see t_assoc_meth_bad + //q.shuffle; // Not legal on assoc - see t_assoc_meth_bad - `checkp(qe, "'{}"); - qv = q.unique; - `checkp(qv, "'{'h1, 'h2, 'h4, 'h3}"); - qv = qe.unique; - `checkp(qv, "'{}"); + `checkp(qe, "'{}"); + qv = q.unique; + `checkp(qv, "'{'h1, 'h2, 'h4, 'h3}"); + qv = qe.unique; + `checkp(qv, "'{}"); - //q.unique_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad + //q.unique_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad - // These require an with clause or are illegal - qv = q.find with (item == 2); - `checkp(qv, "'{'h2, 'h2}"); - qv = q.find_first with (item == 2); - `checkp(qv, "'{'h2}"); - qv = q.find_last with (item == 2); - `checkp(qv, "'{'h2}"); + // These require an with clause or are illegal + qv = q.find with (item == 2); + `checkp(qv, "'{'h2, 'h2}"); + qv = q.find_first with (item == 2); + `checkp(qv, "'{'h2}"); + qv = q.find_last with (item == 2); + `checkp(qv, "'{'h2}"); - qv = q.find with (item == 20); - `checkp(qv, "'{}"); - qv = q.find_first with (item == 20); - `checkp(qv, "'{}"); - qv = q.find_last with (item == 20); - `checkp(qv, "'{}"); + qv = q.find with (item == 20); + `checkp(qv, "'{}"); + qv = q.find_first with (item == 20); + `checkp(qv, "'{}"); + qv = q.find_last with (item == 20); + `checkp(qv, "'{}"); - //q.find_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad - //q.find_first_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad - //q.find_last_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad + //q.find_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad + //q.find_first_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad + //q.find_last_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad - qv = q.min; - `checkp(qv, "'{'h1}"); - qv = q.max; - `checkp(qv, "'{'h4}"); + qv = q.min; + `checkp(qv, "'{'h1}"); + qv = q.max; + `checkp(qv, "'{'h4}"); - qv = qe.min; - `checkp(qv, "'{}"); - qv = qe.max; - `checkp(qv, "'{}"); + qv = qe.min; + `checkp(qv, "'{}"); + qv = qe.max; + `checkp(qv, "'{}"); - // Reduction methods + // Reduction methods - i = q.sum; - `checkh(i, 32'hc); - i = q.sum with (item + 1); - `checkh(i, 32'h11); - i = q.product; - `checkh(i, 32'h30); - i = q.product with (item + 1); - `checkh(i, 32'h168); + i = q.sum; + `checkh(i, 32'hc); + i = q.sum with (item + 1); + `checkh(i, 32'h11); + i = q.product; + `checkh(i, 32'h30); + i = q.product with (item + 1); + `checkh(i, 32'h168); - i = qe.sum; - `checkh(i, 32'h0); - i = qe.product; - `checkh(i, 32'h0); + i = qe.sum; + `checkh(i, 32'h0); + i = qe.product; + `checkh(i, 32'h0); - q = '{10:32'b1100, 11:32'b1010}; - i = q.and; - `checkh(i, 32'b1000); - i = q.and with (item + 1); - `checkh(i, 32'b1001); - i = q.or; - `checkh(i, 32'b1110); - i = q.or with (item + 1); - `checkh(i, 32'b1111); - i = q.xor; - `checkh(i, 32'b0110); - i = q.xor with (item + 1); - `checkh(i, 32'b0110); + q = '{10:32'b1100, 11:32'b1010}; + i = q.and; + `checkh(i, 32'b1000); + i = q.and with (item + 1); + `checkh(i, 32'b1001); + i = q.or; + `checkh(i, 32'b1110); + i = q.or with (item + 1); + `checkh(i, 32'b1111); + i = q.xor; + `checkh(i, 32'b0110); + i = q.xor with (item + 1); + `checkh(i, 32'b0110); - i = qe.and; - `checkh(i, 32'h0); - i = qe.and with (item + 1); - `checkh(i, 32'h0); - i = qe.or; - `checkh(i, 32'b0); - i = qe.or with (item + 1); - `checkh(i, 32'b0); - i = qe.xor; - `checkh(i, 32'b0); - i = qe.xor with (item + 1); - `checkh(i, 32'b0); + i = qe.and; + `checkh(i, 32'h0); + i = qe.and with (item + 1); + `checkh(i, 32'h0); + i = qe.or; + `checkh(i, 32'b0); + i = qe.or with (item + 1); + `checkh(i, 32'b0); + i = qe.xor; + `checkh(i, 32'b0); + i = qe.xor with (item + 1); + `checkh(i, 32'b0); - i = q.and(); - `checkh(i, 32'b1000); - i = q.and() with (item + 1); - `checkh(i, 32'b1001); - i = q.or(); - `checkh(i, 32'b1110); - i = q.or() with (item + 1); - `checkh(i, 32'b1111); - i = q.xor(); - `checkh(i, 32'b0110); - i = q.xor() with (item + 1); - `checkh(i, 32'b0110); + i = q.and(); + `checkh(i, 32'b1000); + i = q.and() with (item + 1); + `checkh(i, 32'b1001); + i = q.or(); + `checkh(i, 32'b1110); + i = q.or() with (item + 1); + `checkh(i, 32'b1111); + i = q.xor(); + `checkh(i, 32'b0110); + i = q.xor() with (item + 1); + `checkh(i, 32'b0110); - i = qe.and(); - `checkh(i, 32'b0); - i = qe.or(); - `checkh(i, 32'b0); - i = qe.xor(); - `checkh(i, 32'b0); + i = qe.and(); + `checkh(i, 32'b0); + i = qe.or(); + `checkh(i, 32'b0); + i = qe.xor(); + `checkh(i, 32'b0); - i = points_q.sum with (vec_len_squared(item)); - `checkh(i, 32'h2a); - i = points_q.product with (vec_len_squared(item)); - `checkh(i, 32'h6a4); - b = points_q.sum with (vec_len_squared(item) == 5); - `checkh(b, 1'b1); - b = points_q.sum with (vec_len_squared(item) == 0); - `checkh(b, 1'b0); - b = points_q.product with (vec_len_squared(item) inside {5, 17}); - `checkh(b, 1'b0); - b = points_q.sum with (vec_len_squared(item) inside {5, 17, 20}); - `checkh(b, 1'b1); + i = points_q.sum with (vec_len_squared(item)); + `checkh(i, 32'h2a); + i = points_q.product with (vec_len_squared(item)); + `checkh(i, 32'h6a4); + b = points_q.sum with (vec_len_squared(item) == 5); + `checkh(b, 1'b1); + b = points_q.sum with (vec_len_squared(item) == 0); + `checkh(b, 1'b0); + b = points_q.product with (vec_len_squared(item) inside {5, 17}); + `checkh(b, 1'b0); + b = points_q.sum with (vec_len_squared(item) inside {5, 17, 20}); + `checkh(b, 1'b1); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_attr_parenstar.v b/test_regress/t/t_attr_parenstar.v index 580a42da7..accecc67d 100644 --- a/test_regress/t/t_attr_parenstar.v +++ b/test_regress/t/t_attr_parenstar.v @@ -4,39 +4,38 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // verilog_format: off + always @(*) begin + if (clk) begin end + end - always @(*) begin - if (clk) begin end - end + always @(* ) begin + if (clk) begin end + end - always @(* ) begin - if (clk) begin end - end + // Not legal in some simulators, legal in others +// always @(* /*cmt*/ ) begin +// if (clk) begin end +// end - // Not legal in some simulators, legal in others -// always @(* /*cmt*/ ) begin -// if (clk) begin end -// end + // Not legal in some simulators, legal in others +// always @(* // cmt +// ) begin +// if (clk) begin end +// end - // Not legal in some simulators, legal in others -// always @(* // cmt -// ) begin -// if (clk) begin end -// end + always @ (* + ) begin + if (clk) begin end + end + // verilog_format: on - always @ (* - ) begin - if (clk) begin end - end - - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_benchmark_mux4k.v b/test_regress/t/t_benchmark_mux4k.v index 0e0fe4ee9..74ca1423f 100644 --- a/test_regress/t/t_benchmark_mux4k.v +++ b/test_regress/t/t_benchmark_mux4k.v @@ -18,163 +18,171 @@ // Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v + // End of automatics - reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai; - reg [`ADDR_WIDTH-1:0] addr; + reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai; + reg [`ADDR_WIDTH-1:0] addr; - // Mux: takes in addr and datai and outputs datao - mux4096 mux4096 (/*AUTOINST*/ - // Outputs - .datao (datao[`DATA_WIDTH-1:0]), - // Inputs - .datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]), - .addr (addr[`ADDR_WIDTH-1:0])); + // Mux: takes in addr and datai and outputs datao + mux4096 mux4096 ( /*AUTOINST*/ + // Outputs + .datao(datao[`DATA_WIDTH-1:0]), + // Inputs + .datai(datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]), + .addr(addr[`ADDR_WIDTH-1:0]) + ); - // calculate what the answer should be from datai. This is bit - // tricky given the way datai gets sliced. datai is in bit - // planes where all the LSBs are contiguous and then the next bit. - reg [`DATA_WIDTH-1:0] datao_check; - integer j; - always @(datai or addr) begin - for(j=0;j<`DATA_WIDTH;j=j+1) begin - /* verilator lint_off WIDTH */ - datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr); - /* verilator lint_on WIDTH */ + // calculate what the answer should be from datai. This is bit + // tricky given the way datai gets sliced. datai is in bit + // planes where all the LSBs are contiguous and then the next bit. + reg [`DATA_WIDTH-1:0] datao_check; + integer j; + always @(datai or addr) begin + for (j = 0; j < `DATA_WIDTH; j = j + 1) begin + /* verilator lint_off WIDTH */ + datao_check[j] = datai >> ((`MUX1_SIZE * `MUX2_SIZE * j) + addr); + /* verilator lint_on WIDTH */ + end + end + + // Run the test loop. This just increments the address + integer i, result; + always @(posedge clk) begin + // initial the input data with random values + if (addr == 0) begin + result = 1; + datai = 0; + for (i = 0; i < `MUX1_SIZE * `MUX2_SIZE; i = i + 1) begin + /* verilator lint_off WIDTH */ + datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}}); + /* verilator lint_on WIDTH */ end - end + end - // Run the test loop. This just increments the address - integer i, result; - always @ (posedge clk) begin - // initial the input data with random values - if (addr == 0) begin - result = 1; - datai = 0; - for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin - /* verilator lint_off WIDTH */ - datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}}); - /* verilator lint_on WIDTH */ - end - end - - addr <= addr + 1; - if (datao_check != datao) begin - result = 0; - $stop; - end + addr <= addr + 1; + if (datao_check != datao) begin + result = 0; + $stop; + end `ifdef TEST_VERBOSE - $write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao); + $write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao); `endif - // only run the first 10 addresses for now - if (addr > 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // only run the first 10 addresses for now + if (addr > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module mux4096 - (input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai, - input [`ADDR_WIDTH-1:0] addr, - output [`DATA_WIDTH-1:0] datao - ); +module mux4096 ( + input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai, + input [`ADDR_WIDTH-1:0] addr, + output [`DATA_WIDTH-1:0] datao +); - // DATA_WIDTH instantiations of mux4096_1bit - mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0] - (.addr(addr), + // DATA_WIDTH instantiations of mux4096_1bit + mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0] ( + .addr(addr), .datai(datai), .datao(datao) - ); + ); endmodule -module mux4096_1bit - (input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai, - input [`ADDR_WIDTH-1:0] addr, - output datao - ); +module mux4096_1bit ( + input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai, + input [`ADDR_WIDTH-1:0] addr, + output datao +); - // address decoding - wire [3:0] A = (4'b1) << addr[1:0]; - wire [3:0] B = (4'b1) << addr[3:2]; - wire [3:0] C = (4'b1) << addr[5:4]; - wire [3:0] D = (4'b1) << addr[7:6]; - wire [3:0] E = (4'b1) << addr[9:8]; - wire [3:0] F = (4'b1) << addr[11:10]; + // address decoding + wire [3:0] A = (4'b1) << addr[1:0]; + wire [3:0] B = (4'b1) << addr[3:2]; + wire [3:0] C = (4'b1) << addr[5:4]; + wire [3:0] D = (4'b1) << addr[7:6]; + wire [3:0] E = (4'b1) << addr[9:8]; + wire [3:0] F = (4'b1) << addr[11:10]; - wire [`MUX2_SIZE-1:0] data0; + wire [`MUX2_SIZE-1:0] data0; - // DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64 - // first stage of 64:1 muxing - mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0] - (.A(A), + // DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64 + // first stage of 64:1 muxing + mux64 #( + .MUX_SIZE(`MUX1_SIZE) + ) mux1[`MUX2_SIZE-1:0] ( + .A(A), .B(B), .C(C), .datai(datai), - .datao(data0)); + .datao(data0) + ); - // DATA_WIDTH*MUX2_SIZE instantiations of mux64 - // second stage of 64:1 muxing - mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2 - (.A(D), + // DATA_WIDTH*MUX2_SIZE instantiations of mux64 + // second stage of 64:1 muxing + mux64 #( + .MUX_SIZE(`MUX2_SIZE) + ) mux2 ( + .A(D), .B(E), .C(F), .datai(data0), - .datao(datao)); + .datao(datao) + ); endmodule -module mux64 - #(parameter MUX_SIZE=64) - (input [3:0] A, - input [3:0] B, - input [3:0] C, - input [MUX_SIZE-1:0] datai, - output datao - ); +module mux64 #( + parameter MUX_SIZE = 64 +) ( + input [3:0] A, + input [3:0] B, + input [3:0] C, + input [MUX_SIZE-1:0] datai, + output datao +); - wire [63:0] colSelA = { 16{ A[3:0] }}; - wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}}; - wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}}; + wire [63:0] colSelA = {16{A[3:0]}}; + wire [63:0] colSelB = {4{{4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}}; + wire [63:0] colSelC = {{16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}}; - wire [MUX_SIZE-1:0] data_bus; + wire [MUX_SIZE-1:0] data_bus; - // Note each of these becomes a separate wire. - //.colSelA(colSelA[MUX_SIZE-1:0]), - //.colSelB(colSelB[MUX_SIZE-1:0]), - //.colSelC(colSelC[MUX_SIZE-1:0]), + // Note each of these becomes a separate wire. + //.colSelA(colSelA[MUX_SIZE-1:0]), + //.colSelB(colSelB[MUX_SIZE-1:0]), + //.colSelC(colSelC[MUX_SIZE-1:0]), - drv drv[MUX_SIZE-1:0] - (.colSelA(colSelA[MUX_SIZE-1:0]), + drv drv[MUX_SIZE-1:0] ( + .colSelA(colSelA[MUX_SIZE-1:0]), .colSelB(colSelB[MUX_SIZE-1:0]), .colSelC(colSelC[MUX_SIZE-1:0]), .datai(datai), .datao(data_bus) - ); + ); - assign datao = |data_bus; + assign datao = |data_bus; endmodule -module drv - (input colSelA, - input colSelB, - input colSelC, - input datai, - output datao - ); - assign datao = colSelC & colSelB & colSelA & datai; +module drv ( + input colSelA, + input colSelB, + input colSelC, + input datai, + output datao +); + assign datao = colSelC & colSelB & colSelA & datai; endmodule diff --git a/test_regress/t/t_bind.v b/test_regress/t/t_bind.v index a8ec4fe9e..8601775db 100644 --- a/test_regress/t/t_bind.v +++ b/test_regress/t/t_bind.v @@ -7,72 +7,77 @@ bit a_finished; bit b_finished; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - wire [31:0] o; - wire si = 1'b0; +module t ( /*AUTOARG*/ + // Inputs + clk + ); + input clk; + wire [31:0] o; + wire si = 1'b0; - ExampInst i - (// Outputs - .o (o[31:0]), + ExampInst i ( // Outputs + .o(o[31:0]), // Inputs - .i (1'b0) - /*AUTOINST*/); + .i(1'b0) + /*AUTOINST*/); - Prog p (/*AUTOINST*/ - // Inputs - .si (si)); + Prog p ( /*AUTOINST*/ + // Inputs + .si (si)); - always @ (posedge clk) begin - if (!a_finished) $stop; - if (!b_finished) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (!a_finished) $stop; + if (!b_finished) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module InstModule ( - output logic [31:0] so, - input si - ); - assign so = {32{si}}; + output logic [31:0] so, + input si +); + assign so = {32{si}}; endmodule -program Prog (input si); - initial a_finished = 1'b1; +program Prog ( + input si +); + initial a_finished = 1'b1; endprogram -module ExampInst (o,i); - output logic [31:0] o; - input i; +module ExampInst ( + o, + i +); + output logic [31:0] o; + input i; - InstModule instName - (// Outputs - .so (o[31:0]), + InstModule instName ( // Outputs + .so(o[31:0]), // Inputs - .si (i) - /*AUTOINST*/); + .si(i) + /*AUTOINST*/); - //bind InstModule Prog instProg - // (.si(si)); + //bind InstModule Prog instProg + // (.si(si)); - // Note is based on context of caller - bind InstModule Prog instProg - (/*AUTOBIND*/ - .si (si)); + // Note is based on context of caller + bind InstModule Prog instProg ( /*AUTOBIND*/ + .si(si) + ); endmodule // Check bind at top level -bind InstModule Prog2 instProg2 - (/*AUTOBIND*/ - .si (si)); +bind InstModule Prog2 instProg2 ( /*AUTOBIND*/ + .si(si) +); // Check program declared after bind -program Prog2 (input si); - initial b_finished = 1'b1; +program Prog2 ( + input si +); + initial b_finished = 1'b1; endprogram diff --git a/test_regress/t/t_bind2.v b/test_regress/t/t_bind2.v index ebf19478c..7b400704f 100644 --- a/test_regress/t/t_bind2.v +++ b/test_regress/t/t_bind2.v @@ -6,14 +6,15 @@ // verilator lint_off WIDTH +// verilog_format: off `define stop $stop -`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t ( + input clk +); -module t ( /*AUTOARG*/ - // Inputs - clk - ); - input clk; reg [7:0] p1; reg [7:0] p2; reg [7:0] p3; diff --git a/test_regress/t/t_bind_nfound.v b/test_regress/t/t_bind_nfound.v index ba0e49bb5..46cb381de 100644 --- a/test_regress/t/t_bind_nfound.v +++ b/test_regress/t/t_bind_nfound.v @@ -9,19 +9,19 @@ endinterface module t; - sub sub(); + sub sub (); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub_ext; - bind sub_inst bound_if i_bound(); + bind sub_inst bound_if i_bound (); endmodule module sub; - sub_ext sub_ext(); + sub_ext sub_ext (); endmodule diff --git a/test_regress/t/t_bitsel_2d_slice.v b/test_regress/t/t_bitsel_2d_slice.v index 25ffbf47e..6387c9d31 100644 --- a/test_regress/t/t_bitsel_2d_slice.v +++ b/test_regress/t/t_bitsel_2d_slice.v @@ -4,26 +4,24 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - localparam int WIDTH = 8; - typedef logic [WIDTH-1:0] [15:0] two_dee_t; - typedef logic[$clog2(WIDTH)-1:0] index_t; + localparam int WIDTH = 8; + typedef logic [WIDTH-1:0][15:0] two_dee_t; + typedef logic [$clog2(WIDTH)-1:0] index_t; - two_dee_t the_two_dee; + two_dee_t the_two_dee; - initial begin - the_two_dee[index_t'(5)][7:0] = 8'hab; - the_two_dee[index_t'(5)][15:8] = 8'h12; - end + initial begin + the_two_dee[index_t'(5)][7:0] = 8'hab; + the_two_dee[index_t'(5)][15:8] = 8'h12; + end - always @ (posedge clk) begin - if (the_two_dee[5] != 16'h12ab) $stop(); - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (the_two_dee[5] != 16'h12ab) $stop(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_concat.v b/test_regress/t/t_bitsel_concat.v index daff0b45e..a6c364b87 100644 --- a/test_regress/t/t_bitsel_concat.v +++ b/test_regress/t/t_bitsel_concat.v @@ -17,88 +17,88 @@ // Test IEEE 1800-2023 concat bit selects, function bit selects, method bit selects class Cls; - static function logic [15:0] valf1ed(); - return 16'hf1ed; - endfunction + static function logic [15:0] valf1ed(); + return 16'hf1ed; + endfunction endclass module t; - Cls c; + Cls c; - int q[$]; + int q[$]; - logic [7:0] aa; - logic [7:0] bb; - logic [7:0] s8; - logic s1; + logic [7:0] aa; + logic [7:0] bb; + logic [7:0] s8; + logic s1; - function logic [15:0] valf0ed(); - return 16'hf0ed; - endfunction + function logic [15:0] valf0ed(); + return 16'hf0ed; + endfunction - int i; - typedef int arr_t[1:0][3:0]; + int i; + typedef int arr_t[1:0][3:0]; - function arr_t valarr(); - return '{'{1,2,3,4}, '{5,6,7,8}}; - endfunction + function arr_t valarr(); + return '{'{1,2,3,4}, '{5,6,7,8}}; + endfunction - initial begin - aa = 8'haa; - bb = 8'hbb; + initial begin + aa = 8'haa; + bb = 8'hbb; - s1 = {aa,bb}[8]; - `checkh(s1, 1'b0); - s1 = {aa,bb}[9]; - `checkh(s1, 1'b1); - s8 = {aa,bb}[11:4]; - `checkh(s8, 8'hab); - s8 = {aa,bb}[4+:8]; - `checkh(s8, 8'hab); - s8 = {aa,bb}[11-:8]; - `checkh(s8, 8'hab); + s1 = {aa,bb}[8]; + `checkh(s1, 1'b0); + s1 = {aa,bb}[9]; + `checkh(s1, 1'b1); + s8 = {aa,bb}[11:4]; + `checkh(s8, 8'hab); + s8 = {aa,bb}[4+:8]; + `checkh(s8, 8'hab); + s8 = {aa,bb}[11-:8]; + `checkh(s8, 8'hab); - s1 = valf0ed()[4]; - `checkh(s1, 1'b0); - s1 = valf0ed()[5]; - `checkh(s1, 1'b1); - s8 = valf0ed()[11:4]; - `checkh(s8, 8'h0e); - s8 = valf0ed()[4+:8]; - `checkh(s8, 8'h0e); - s8 = valf0ed()[11-:8]; - `checkh(s8, 8'h0e); + s1 = valf0ed()[4]; + `checkh(s1, 1'b0); + s1 = valf0ed()[5]; + `checkh(s1, 1'b1); + s8 = valf0ed()[11:4]; + `checkh(s8, 8'h0e); + s8 = valf0ed()[4+:8]; + `checkh(s8, 8'h0e); + s8 = valf0ed()[11-:8]; + `checkh(s8, 8'h0e); - c = new; - s1 = c.valf1ed()[4]; - `checkh(s1, 1'b0); - s1 = c.valf1ed()[5]; - `checkh(s1, 1'b1); - s8 = c.valf1ed()[11:4]; - `checkh(s8, 8'h1e); - s8 = c.valf1ed()[4+:8]; - `checkh(s8, 8'h1e); - s8 = c.valf1ed()[11-:8]; - `checkh(s8, 8'h1e); + c = new; + s1 = c.valf1ed()[4]; + `checkh(s1, 1'b0); + s1 = c.valf1ed()[5]; + `checkh(s1, 1'b1); + s8 = c.valf1ed()[11:4]; + `checkh(s8, 8'h1e); + s8 = c.valf1ed()[4+:8]; + `checkh(s8, 8'h1e); + s8 = c.valf1ed()[11-:8]; + `checkh(s8, 8'h1e); - q.push_front(32'h10ef); - s1 = q.sum()[4]; - `checkh(s1, 1'b0); - s1 = q.sum()[5]; - `checkh(s1, 1'b1); - s8 = q.sum()[11:4]; - `checkh(s8, 8'h0e); - s8 = q.sum()[4+:8]; - `checkh(s8, 8'h0e); - s8 = q.sum()[11-:8]; - `checkh(s8, 8'h0e); + q.push_front(32'h10ef); + s1 = q.sum()[4]; + `checkh(s1, 1'b0); + s1 = q.sum()[5]; + `checkh(s1, 1'b1); + s8 = q.sum()[11:4]; + `checkh(s8, 8'h0e); + s8 = q.sum()[4+:8]; + `checkh(s8, 8'h0e); + s8 = q.sum()[11-:8]; + `checkh(s8, 8'h0e); - i = valarr()[1][2]; - $display(i); + i = valarr()[1][2]; + $display(i); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_const_bad.out b/test_regress/t/t_bitsel_const_bad.out index f4060503d..3e4b87786 100644 --- a/test_regress/t/t_bitsel_const_bad.out +++ b/test_regress/t/t_bitsel_const_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_bitsel_const_bad.v:16:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' +%Error: t/t_bitsel_const_bad.v:16:15: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' - 16 | assign a = b[0]; - | ^ + 16 | assign a = b[0]; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_bitsel_const_bad.v b/test_regress/t/t_bitsel_const_bad.v index 27316736f..368fd9c0a 100644 --- a/test_regress/t/t_bitsel_const_bad.v +++ b/test_regress/t/t_bitsel_const_bad.v @@ -8,11 +8,11 @@ module t; - // Note that if we declare "wire [0:0] b", this works just fine. - wire a; - wire b; + // Note that if we declare "wire [0:0] b", this works just fine. + wire a; + wire b; - assign b = 1'b0; - assign a = b[0]; // IEEE illegal can't extract scalar + assign b = 1'b0; + assign a = b[0]; // IEEE illegal can't extract scalar endmodule diff --git a/test_regress/t/t_bitsel_enum.v b/test_regress/t/t_bitsel_enum.v index edb81040e..58176bdb9 100644 --- a/test_regress/t/t_bitsel_enum.v +++ b/test_regress/t/t_bitsel_enum.v @@ -4,25 +4,22 @@ // SPDX-FileCopyrightText: 2015 Jonathon Donaldson // SPDX-License-Identifier: CC0-1.0 -module t_bitsel_enum - ( - output out0, - output out1 - ); +module t_bitsel_enum ( + output out0, + output out1 +); - localparam [6:0] CNST_VAL = 7'h22; + localparam [6:0] CNST_VAL = 7'h22; - enum logic [6:0] { - ENUM_VAL = 7'h33 - } MyEnum; + enum logic [6:0] {ENUM_VAL = 7'h33} MyEnum; - assign out0 = CNST_VAL[0]; - // Not supported by NC-verilog nor VCS, but other simulators do - assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works + assign out0 = CNST_VAL[0]; + // Not supported by NC-verilog nor VCS, but other simulators do + assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_over32.v b/test_regress/t/t_bitsel_over32.v index c4311ca0b..44b16ad73 100644 --- a/test_regress/t/t_bitsel_over32.v +++ b/test_regress/t/t_bitsel_over32.v @@ -4,35 +4,38 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(aw_addr, orig_aw_size); +module t ( + aw_addr, + orig_aw_size +); - typedef logic [63:0] addr_t; - typedef logic [7:0][7:0] mst_data_t; + typedef logic [63:0] addr_t; + typedef logic [7:0][7:0] mst_data_t; - logic [127:0] slv_req_i_w_data; - input addr_t aw_addr; - mst_data_t w_data; - input logic [2:0] orig_aw_size; + logic [127:0] slv_req_i_w_data; + input addr_t aw_addr; + mst_data_t w_data; + input logic [2:0] orig_aw_size; - always_comb begin + always_comb begin - // verilator lint_off WIDTHEXPAND - automatic addr_t mst_port_offset = aw_addr[2:0]; - automatic addr_t slv_port_offset = aw_addr[3:0]; + // verilator lint_off WIDTHEXPAND + automatic addr_t mst_port_offset = aw_addr[2:0]; + automatic addr_t slv_port_offset = aw_addr[3:0]; - w_data = '0; + w_data = '0; - for (int b=0; b<16; b++) begin - if ((b >= slv_port_offset) && + for (int b = 0; b < 16; b++) begin + if ((b >= slv_port_offset) && (b - slv_port_offset < (1 << orig_aw_size)) && (b + mst_port_offset - slv_port_offset < 8)) begin - automatic addr_t index = b + mst_port_offset - slv_port_offset; + automatic addr_t index = b + mst_port_offset - slv_port_offset; - // verilator lint_on WIDTHEXPAND - // [#][7:0] = [ +: 8] - w_data[index] = slv_req_i_w_data[8*b +: 8]; + // verilator lint_on WIDTHEXPAND + // [#][7:0] = [ +: 8] + w_data[index] = slv_req_i_w_data[8*b+:8]; - end end - end + end + end endmodule diff --git a/test_regress/t/t_bitsel_slice.v b/test_regress/t/t_bitsel_slice.v index bf26d8a10..c5af87271 100644 --- a/test_regress/t/t_bitsel_slice.v +++ b/test_regress/t/t_bitsel_slice.v @@ -4,80 +4,78 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - logic [2:0] [1:0] in; - always @* in = crc[5:0]; + logic [2:0][1:0] in; + always @* in = crc[5:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic [1:0] [1:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [1:0] [1:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out/*[1:0][1:0]*/), - // Inputs - .clk (clk), - .in (in/*[2:0][1:0]*/)); + Test test ( /*AUTOINST*/ + // Outputs + .out (out/*[1:0][1:0]*/), + // Inputs + .clk (clk), + .in (in/*[2:0][1:0]*/)); - // Aggregate outputs into a single result vector - wire [63:0] result = {60'h0, out[1],out[0]}; + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out[1], out[0]}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hdc21e42d85441511 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hdc21e42d85441511 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); - //bug717 + //bug717 - input clk; - input logic [2:0][1:0] in; + input clk; + input logic [2:0][1:0] in; - output logic [1:0][1:0] out; + output logic [1:0][1:0] out; - always @(posedge clk) begin - out <= in[2 -: 2]; - end + always @(posedge clk) begin + out <= in[2-:2]; + end endmodule diff --git a/test_regress/t/t_bitsel_struct.v b/test_regress/t/t_bitsel_struct.v index 03e271b77..bdeb1d689 100644 --- a/test_regress/t/t_bitsel_struct.v +++ b/test_regress/t/t_bitsel_struct.v @@ -11,19 +11,19 @@ module t; - typedef struct packed { - logic [1:0][15:0] channel; - logic others; - } buss_t; + typedef struct packed { + logic [1:0][15:0] channel; + logic others; + } buss_t; - buss_t b; - reg [7:0] a; + buss_t b; + reg [7:0] a; - initial begin - b = {16'h8765,16'h4321,1'b1}; - a = b.channel[0][8+:8]; - if (a != 8'h43) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + b = {16'h8765, 16'h4321, 1'b1}; + a = b.channel[0][8+:8]; + if (a != 8'h43) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_struct2.v b/test_regress/t/t_bitsel_struct2.v index 41b02b1ea..39cf0fdb4 100644 --- a/test_regress/t/t_bitsel_struct2.v +++ b/test_regress/t/t_bitsel_struct2.v @@ -4,43 +4,43 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - typedef struct packed { - logic [3:2] a; - logic [5:4][3:2] b; - } ab_t; - typedef ab_t [7:6] c_t; // array of structs - typedef struct packed { - c_t [17:16] d; - } e_t; + typedef struct packed { + logic [3:2] a; + logic [5:4][3:2] b; + } ab_t; + typedef ab_t [7:6] c_t; // array of structs + typedef struct packed {c_t [17:16] d;} e_t; - initial begin - e_t e; - `checkh($bits(ab_t),6); - `checkh($bits(c_t),12); - `checkh($bits(e_t),24); - `checkh($bits(e), 24); - `checkh($bits(e.d[17]),12); - `checkh($bits(e.d[16][6]),6); - `checkh($bits(e.d[16][6].b[5]),2); - `checkh($bits(e.d[16][6].b[5][2]), 1); - // - e = 24'b101101010111010110101010; - `checkb(e, 24'b101101010111010110101010); - e.d[17] = 12'b111110011011; - `checkb(e, 24'b111110011011010110101010); - e.d[16][6] = 6'b010101; - `checkb(e, 24'b111110011011010110010101); - e.d[16][6].b[5] = 2'b10; - `checkb(e, 24'b111110011011010110011001); - e.d[16][6].b[5][2] = 1'b1; - // - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + e_t e; + `checkh($bits(ab_t), 6); + `checkh($bits(c_t), 12); + `checkh($bits(e_t), 24); + `checkh($bits(e), 24); + `checkh($bits(e.d[17]), 12); + `checkh($bits(e.d[16][6]), 6); + `checkh($bits(e.d[16][6].b[5]), 2); + `checkh($bits(e.d[16][6].b[5][2]), 1); + // + e = 24'b101101010111010110101010; + `checkb(e, 24'b101101010111010110101010); + e.d[17] = 12'b111110011011; + `checkb(e, 24'b111110011011010110101010); + e.d[16][6] = 6'b010101; + `checkb(e, 24'b111110011011010110010101); + e.d[16][6].b[5] = 2'b10; + `checkb(e, 24'b111110011011010110011001); + e.d[16][6].b[5][2] = 1'b1; + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_struct3.v b/test_regress/t/t_bitsel_struct3.v index 3a63eb106..a54c0e47f 100644 --- a/test_regress/t/t_bitsel_struct3.v +++ b/test_regress/t/t_bitsel_struct3.v @@ -9,48 +9,50 @@ // SPDX-FileCopyrightText: 2013 Jie Xu // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - typedef struct packed { - logic [15:0] channel; - logic [15:0] others; - } buss_t; + typedef struct packed { + logic [15:0] channel; + logic [15:0] others; + } buss_t; - buss_t b; + buss_t b; - reg [7:0] a; - reg [7:0] c; - reg [7:0] d; + reg [7:0] a; + reg [7:0] c; + reg [7:0] d; - union packed { - logic [31:0] [7:0] idx; - struct packed { - logic [15:0] z, y, x; - logic [25:0] [7:0] r; - } nam; - } gpr; + union packed { + logic [31:0][7:0] idx; + struct packed { + logic [15:0] z, y, x; + logic [25:0][7:0] r; + } nam; + } gpr; - reg [14:0] gpr_a; + reg [14:0] gpr_a; - initial begin - b = {16'h8765,16'h4321}; - a = b[19:12]; // This works - c = b[8+:8]; // This fails - d = b[11-:8]; // This fails - `checkh(a, 8'h54); - `checkh(c, 8'h43); - `checkh(d, 8'h32); + initial begin + b = {16'h8765, 16'h4321}; + a = b[19:12]; // This works + c = b[8+:8]; // This fails + d = b[11-:8]; // This fails + `checkh(a, 8'h54); + `checkh(c, 8'h43); + `checkh(d, 8'h32); - gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345; - `checkh (gpr[255:255-14], 15'h091a); - gpr_a = gpr.nam.z[15:1]; - `checkh (gpr_a, 15'h091a); + gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345; + `checkh(gpr[255:255-14], 15'h091a); + gpr_a = gpr.nam.z[15:1]; + `checkh(gpr_a, 15'h091a); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_wire_array_bad.out b/test_regress/t/t_bitsel_wire_array_bad.out index 5fdddc94d..86dc766af 100644 --- a/test_regress/t/t_bitsel_wire_array_bad.out +++ b/test_regress/t/t_bitsel_wire_array_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_bitsel_wire_array_bad.v:16:16: Illegal assignment of constant to unpacked array +%Error: t/t_bitsel_wire_array_bad.v:16:15: Illegal assignment of constant to unpacked array : ... note: In instance 't' - 16 | assign b = a[0]; - | ^ + 16 | assign b = a[0]; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_bitsel_wire_array_bad.v b/test_regress/t/t_bitsel_wire_array_bad.v index f14a20c61..e2a630c14 100644 --- a/test_regress/t/t_bitsel_wire_array_bad.v +++ b/test_regress/t/t_bitsel_wire_array_bad.v @@ -8,11 +8,11 @@ module t; - // a and b are arrays of length 1. - wire a[0:0]; // Array of nets - wire b[0:0]; + // a and b are arrays of length 1. + wire a[0:0]; // Array of nets + wire b[0:0]; - assign a = 1'b0; // Only net assignment allowed - assign b = a[0]; // Only net assignment allowed + assign a = 1'b0; // Only net assignment allowed + assign b = a[0]; // Only net assignment allowed endmodule diff --git a/test_regress/t/t_blocking.v b/test_regress/t/t_blocking.v index 9978352cd..6328b995d 100644 --- a/test_regress/t/t_blocking.v +++ b/test_regress/t/t_blocking.v @@ -4,93 +4,91 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer _mode; + initial _mode = 0; + reg [7:0] a; + reg [7:0] b; + reg [7:0] c; - integer _mode; initial _mode=0; - reg [7:0] a; - reg [7:0] b; - reg [7:0] c; + reg [7:0] mode_d1r; + reg [7:0] mode_d2r; + reg [7:0] mode_d3r; - reg [7:0] mode_d1r; - reg [7:0] mode_d2r; - reg [7:0] mode_d3r; + // surefire lint_off ITENST + // surefire lint_off STMINI + // surefire lint_off NBAJAM - // surefire lint_off ITENST - // surefire lint_off STMINI - // surefire lint_off NBAJAM - - always @ (posedge clk) begin // filp-flops with asynchronous reset - if (0) begin - _mode <= 0; + always @(posedge clk) begin // filp-flops with asynchronous reset + if (0) begin + _mode <= 0; + end + else begin + _mode <= _mode + 1; + if (_mode == 0) begin + $write("[%0t] t_blocking: Running\n", $time); + a <= 8'd0; + b <= 8'd0; + c <= 8'd0; end - else begin - _mode <= _mode + 1; - if (_mode==0) begin - $write("[%0t] t_blocking: Running\n", $time); - a <= 8'd0; - b <= 8'd0; - c <= 8'd0; - end - else if (_mode==1) begin - if (a !== 8'd0) $stop; - if (b !== 8'd0) $stop; - if (c !== 8'd0) $stop; - a <= b; - b <= 8'd1; - c <= b; - if (a !== 8'd0) $stop; - if (b !== 8'd0) $stop; - if (c !== 8'd0) $stop; - end - else if (_mode==2) begin - if (a !== 8'd0) $stop; - if (b !== 8'd1) $stop; - if (c !== 8'd0) $stop; - a <= b; - b <= 8'd2; - c <= b; - if (a !== 8'd0) $stop; - if (b !== 8'd1) $stop; - if (c !== 8'd0) $stop; - end - else if (_mode==3) begin - if (a !== 8'd1) $stop; - if (b !== 8'd2) $stop; - if (c !== 8'd1) $stop; - end - else if (_mode==4) begin - if (mode_d3r != 8'd1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + else if (_mode == 1) begin + if (a !== 8'd0) $stop; + if (b !== 8'd0) $stop; + if (c !== 8'd0) $stop; + a <= b; + b <= 8'd1; + c <= b; + if (a !== 8'd0) $stop; + if (b !== 8'd0) $stop; + if (c !== 8'd0) $stop; end - end + else if (_mode == 2) begin + if (a !== 8'd0) $stop; + if (b !== 8'd1) $stop; + if (c !== 8'd0) $stop; + a <= b; + b <= 8'd2; + c <= b; + if (a !== 8'd0) $stop; + if (b !== 8'd1) $stop; + if (c !== 8'd0) $stop; + end + else if (_mode == 3) begin + if (a !== 8'd1) $stop; + if (b !== 8'd2) $stop; + if (c !== 8'd1) $stop; + end + else if (_mode == 4) begin + if (mode_d3r != 8'd1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end - always @ (posedge clk) begin - mode_d3r <= mode_d2r; - mode_d2r <= mode_d1r; - mode_d1r <= _mode[7:0]; - end + always @(posedge clk) begin + mode_d3r <= mode_d2r; + mode_d2r <= mode_d1r; + mode_d1r <= _mode[7:0]; + end - reg [14:10] bits; - // surefire lint_off SEQASS - always @ (posedge clk) begin - if (_mode==1) begin - bits[14:13] <= 2'b11; - bits[12] <= 1'b1; - end - if (_mode==2) begin - bits[11:10] <= 2'b10; - bits[13] <= 0; - end - if (_mode==3) begin - if (bits !== 5'b10110) $stop; - end - end + reg [14:10] bits; + // surefire lint_off SEQASS + always @(posedge clk) begin + if (_mode == 1) begin + bits[14:13] <= 2'b11; + bits[12] <= 1'b1; + end + if (_mode == 2) begin + bits[11:10] <= 2'b10; + bits[13] <= 0; + end + if (_mode == 3) begin + if (bits !== 5'b10110) $stop; + end + end endmodule diff --git a/test_regress/t/t_c_this.v b/test_regress/t/t_c_this.v index 50bd459f7..d5dcd8f0b 100644 --- a/test_regress/t/t_c_this.v +++ b/test_regress/t/t_c_this.v @@ -4,12 +4,14 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; - always @(posedge clk) begin - $c("const CData xthis = this->clk;"); - $c("const CData thisx = xthis;"); - $c("const CData xthisx = thisx;"); - $c("this->clk = xthisx;"); - end +module t ( + clk +); + input clk; + always @(posedge clk) begin + $c("const CData xthis = this->clk;"); + $c("const CData thisx = xthis;"); + $c("const CData xthisx = thisx;"); + $c("this->clk = xthisx;"); + end endmodule diff --git a/test_regress/t/t_case_genx_bad.out b/test_regress/t/t_case_genx_bad.out index 09c1b5392..e5a63f89d 100644 --- a/test_regress/t/t_case_genx_bad.out +++ b/test_regress/t/t_case_genx_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_case_genx_bad.v:14:9: Use of x/? constant in generate case statement, (no such thing as 'generate casez') +%Error: t/t_case_genx_bad.v:14:7: Use of x/? constant in generate case statement, (no such thing as 'generate casez') : ... note: In instance 't' - 14 | 32'b1xxx: initial begin end - | ^~~~~~~~ + 14 | 32'b1xxx: initial begin end + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_case_genx_bad.v b/test_regress/t/t_case_genx_bad.v index 7c5da4003..21ed53ecf 100644 --- a/test_regress/t/t_case_genx_bad.v +++ b/test_regress/t/t_case_genx_bad.v @@ -6,14 +6,14 @@ module t; - parameter P = 32'b1000; + parameter P = 32'b1000; - generate - case (P) - 32'b0: initial begin end - 32'b1xxx: initial begin end - default initial begin end // No ':' to cover parser - endcase - endgenerate + generate + case (P) + 32'b0: initial begin end + 32'b1xxx: initial begin end + default initial begin end // No ':' to cover parser + endcase + endgenerate endmodule diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v index 3bf1c5124..0325f18b0 100644 --- a/test_regress/t/t_cast.v +++ b/test_regress/t/t_cast.v @@ -5,136 +5,136 @@ // SPDX-License-Identifier: CC0-1.0 interface intf; - typedef logic [7:0] octet; - typedef octet [1:0] word; - octet [1:0] octets; - word [1:0] words; + typedef logic [7:0] octet; + typedef octet [1:0] word; + octet [1:0] octets; + word [1:0] words; endinterface module t; - typedef logic [3:0] mc_t; - typedef mc_t tocast_t; - typedef logic [2:0] [7:0] two_dee_t; + typedef logic [3:0] mc_t; + typedef mc_t tocast_t; + typedef logic [2:0] [7:0] two_dee_t; - typedef struct packed { - logic [15:0] data; - } packed_t; - typedef struct packed { - logic [31:0] data; - } packed2_t; + typedef struct packed { + logic [15:0] data; + } packed_t; + typedef struct packed { + logic [31:0] data; + } packed2_t; - typedef enum [15:0] { - ONE = 1 - } enum_t; + typedef enum [15:0] { + ONE = 1 + } enum_t; - typedef enum_t [3:0] enums_t; + typedef enum_t [3:0] enums_t; - packed_t pdata; - packed_t pdata_reg; - packed2_t pdata2_reg; - assign pdata.data = 16'h1234; - logic [7:0] logic8bit; - assign logic8bit = $bits(logic8bit)'(pdata >> 8); + packed_t pdata; + packed_t pdata_reg; + packed2_t pdata2_reg; + assign pdata.data = 16'h1234; + logic [7:0] logic8bit; + assign logic8bit = $bits(logic8bit)'(pdata >> 8); - mc_t o; - enum_t e; - enums_t es; + mc_t o; + enum_t e; + enums_t es; - intf the_intf(); + intf the_intf(); - logic [15:0] allones = 16'hffff; - parameter FOUR = 4; + logic [15:0] allones = 16'hffff; + parameter FOUR = 4; - localparam two_dee_t two_dee = two_dee_t'(32'habcdef); + localparam two_dee_t two_dee = two_dee_t'(32'habcdef); - // bug925 - localparam [6:0] RESULT = 7'((6*9+92)%96); + // bug925 + localparam [6:0] RESULT = 7'((6*9+92)%96); - logic signed [14:0] samp0 = 15'h0000; - logic signed [14:0] samp1 = 15'h0000; - logic signed [14:0] samp2 = 15'h6000; - logic signed [11:0] coeff0 = 12'h009; - logic signed [11:0] coeff1 = 12'h280; - logic signed [11:0] coeff2 = 12'h4C5; - logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11)); - // verilator lint_off WIDTH - logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11)); - // verilator lint_on WIDTH - logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector - (27'(coeff1 * samp1) >>> 11) + - (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings + logic signed [14:0] samp0 = 15'h0000; + logic signed [14:0] samp1 = 15'h0000; + logic signed [14:0] samp2 = 15'h6000; + logic signed [11:0] coeff0 = 12'h009; + logic signed [11:0] coeff1 = 12'h280; + logic signed [11:0] coeff2 = 12'h4C5; + logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11)); + // verilator lint_off WIDTH + logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11)); + // verilator lint_on WIDTH + logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector + (27'(coeff1 * samp1) >>> 11) + + (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings - logic one = 1'b1; - logic [32:0] b33 = {32'(0), one}; - logic [31:0] b32 = {31'(0), one}; + logic one = 1'b1; + logic [32:0] b33 = {32'(0), one}; + logic [31:0] b32 = {31'(0), one}; - logic [31:0] thirty_two_bits; - two_dee_t two_dee_sig; + logic [31:0] thirty_two_bits; + two_dee_t two_dee_sig; - int i; - initial begin - if (logic8bit != 8'h12) $stop; - if (4'shf > 4'sh0) $stop; - if (signed'(4'hf) > 4'sh0) $stop; - if (4'hf < 4'h0) $stop; - if (unsigned'(4'shf) < 4'h0) $stop; - if (const'(4'shf) !== 4'shf) $stop; - if (4'(allones) !== 4'hf) $stop; - if (6'(allones) !== 6'h3f) $stop; - if ((4)'(allones) !== 4'hf) $stop; - if ((4+2)'(allones) !== 6'h3f) $stop; - if ((4-2)'(allones) !== 2'h3) $stop; - if ((FOUR+2)'(allones) !== 6'h3f) $stop; - if (50 !== RESULT) $stop; + int i; + initial begin + if (logic8bit != 8'h12) $stop; + if (4'shf > 4'sh0) $stop; + if (signed'(4'hf) > 4'sh0) $stop; + if (4'hf < 4'h0) $stop; + if (unsigned'(4'shf) < 4'h0) $stop; + if (const'(4'shf) !== 4'shf) $stop; + if (4'(allones) !== 4'hf) $stop; + if (6'(allones) !== 6'h3f) $stop; + if ((4)'(allones) !== 4'hf) $stop; + if ((4+2)'(allones) !== 6'h3f) $stop; + if ((4-2)'(allones) !== 2'h3) $stop; + if ((FOUR+2)'(allones) !== 6'h3f) $stop; + if (50 !== RESULT) $stop; - e = ONE; - if (e != 1) $stop; - if (e != ONE) $stop; - e = enum_t'(ONE); - if (e != ONE) $stop; - e = enum_t'(16'h1); - if (e != ONE) $stop; - pdata_reg.data = 1; - e = enum_t'(pdata_reg); - if (e != ONE) $stop; + e = ONE; + if (e != 1) $stop; + if (e != ONE) $stop; + e = enum_t'(ONE); + if (e != ONE) $stop; + e = enum_t'(16'h1); + if (e != ONE) $stop; + pdata_reg.data = 1; + e = enum_t'(pdata_reg); + if (e != ONE) $stop; - es = {ONE, ONE, ONE, ONE}; - for (i = 0; i < 4; i++) if (es[i] != ONE) $stop; - es = enums_t'(64'h0001_0001_0001_0001); - for (i = 0; i < 4; i++) if (es[i] != ONE) $stop; + es = {ONE, ONE, ONE, ONE}; + for (i = 0; i < 4; i++) if (es[i] != ONE) $stop; + es = enums_t'(64'h0001_0001_0001_0001); + for (i = 0; i < 4; i++) if (es[i] != ONE) $stop; - o = tocast_t'(4'b1); - if (o != 4'b1) $stop; + o = tocast_t'(4'b1); + if (o != 4'b1) $stop; - the_intf.octets = 16'd1; - pdata_reg = packed_t'(the_intf.octets); - if (pdata_reg.data != 16'd1) $stop; + the_intf.octets = 16'd1; + pdata_reg = packed_t'(the_intf.octets); + if (pdata_reg.data != 16'd1) $stop; - the_intf.words = 32'd1; - pdata2_reg = packed2_t'(the_intf.words); - if (pdata2_reg.data != 32'd1) $stop; + the_intf.words = 32'd1; + pdata2_reg = packed2_t'(the_intf.words); + if (pdata2_reg.data != 32'd1) $stop; - if (15'h6cec != outa) $stop; - if (27'h7ffecec != mida) $stop; - if (27'h7ffecec != midb) $stop; + if (15'h6cec != outa) $stop; + if (27'h7ffecec != mida) $stop; + if (27'h7ffecec != midb) $stop; - if (b33 != 33'b1) $stop; - if (b32 != 32'b1) $stop; + if (b33 != 33'b1) $stop; + if (b32 != 32'b1) $stop; - if (two_dee[0] != 8'hef) $stop; - if (two_dee[1] != 8'hcd) $stop; - if (two_dee[2] != 8'hab) $stop; + if (two_dee[0] != 8'hef) $stop; + if (two_dee[1] != 8'hcd) $stop; + if (two_dee[2] != 8'hab) $stop; - thirty_two_bits = 32'h123456; - two_dee_sig = two_dee_t'(thirty_two_bits); + thirty_two_bits = 32'h123456; + two_dee_sig = two_dee_t'(thirty_two_bits); - if (two_dee_sig[0] != 8'h56) $stop; - if (two_dee_sig[1] != 8'h34) $stop; - if (two_dee_sig[2] != 8'h12) $stop; + if (two_dee_sig[0] != 8'h56) $stop; + if (two_dee_sig[1] != 8'h34) $stop; + if (two_dee_sig[2] != 8'h12) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cast_param_type.v b/test_regress/t/t_cast_param_type.v index f68e63a4e..ca4814eaa 100644 --- a/test_regress/t/t_cast_param_type.v +++ b/test_regress/t/t_cast_param_type.v @@ -20,7 +20,7 @@ function automatic letters_t lfunc(int a); return letters_t'(1); endfunction -module t (); +module t; localparam FMT = lfunc(1); SubA suba0 (); diff --git a/test_regress/t/t_castdyn_castconst_bad.out b/test_regress/t/t_castdyn_castconst_bad.out index e479532a4..946a30ce3 100644 --- a/test_regress/t/t_castdyn_castconst_bad.out +++ b/test_regress/t/t_castdyn_castconst_bad.out @@ -1,17 +1,17 @@ -%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:20:11: $cast will always return one as 'int' is always castable from 'logic[31:0]' - : ... note: In instance 't' - : ... Suggest static cast - 20 | i = $cast(v, 1); - | ^~~~~ +%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:20:9: $cast will always return one as 'int' is always castable from 'logic[31:0]' + : ... note: In instance 't' + : ... Suggest static cast + 20 | i = $cast(v, 1); + | ^~~~~ ... For warning description see https://verilator.org/warn/CASTCONST?v=latest ... Use "/* verilator lint_off CASTCONST */" and lint_on around source to disable this message. -%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:21:11: $cast will always return one as 'class{}Base' is always castable from 'class{}Base' - : ... note: In instance 't' - : ... Suggest static cast - 21 | i = $cast(b, b); - | ^~~~~ -%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:22:11: $cast will always return zero as 'class{}Base' is not castable from 'class{}Other' - : ... note: In instance 't' - 22 | i = $cast(b, o); - | ^~~~~ +%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:21:9: $cast will always return one as 'class{}Base' is always castable from 'class{}Base' + : ... note: In instance 't' + : ... Suggest static cast + 21 | i = $cast(b, b); + | ^~~~~ +%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:22:9: $cast will always return zero as 'class{}Base' is not castable from 'class{}Other' + : ... note: In instance 't' + 22 | i = $cast(b, o); + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_castdyn_castconst_bad.v b/test_regress/t/t_castdyn_castconst_bad.v index 76ec5e7f5..6b5154e95 100644 --- a/test_regress/t/t_castdyn_castconst_bad.v +++ b/test_regress/t/t_castdyn_castconst_bad.v @@ -8,20 +8,20 @@ class Base; endclass class Other; endclass -enum { ZERO } e; +enum {ZERO} e; module t; - int i; - int v; - Base b; - Other o; - initial begin - i = $cast(v, 1); // 1 - i = $cast(b, b); // 1 - i = $cast(b, o); // 0 - i = $cast(e, 0); // 1 - i = $cast(e, 10); // 0 - end + int i; + int v; + Base b; + Other o; + initial begin + i = $cast(v, 1); // 1 + i = $cast(b, b); // 1 + i = $cast(b, o); // 0 + i = $cast(e, 0); // 1 + i = $cast(e, 10); // 0 + end endmodule diff --git a/test_regress/t/t_castdyn_enum.v b/test_regress/t/t_castdyn_enum.v index 44b6bba5b..3c11e1539 100644 --- a/test_regress/t/t_castdyn_enum.v +++ b/test_regress/t/t_castdyn_enum.v @@ -4,65 +4,67 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -typedef enum {TEN=10, - ELEVEN=11, - SIXTEEN=16} enum_t; +typedef enum { + TEN = 10, + ELEVEN = 11, + SIXTEEN = 16 +} enum_t; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - int i; - int i_const; - int cyc; - enum_t en; + int i; + int i_const; + int cyc; + enum_t en; - // Constant propagation tests - initial begin - en = SIXTEEN; - i_const = $cast(en, 1); - if (i_const != 0) $stop; - if (en != SIXTEEN) $stop; + // Constant propagation tests + initial begin + en = SIXTEEN; + i_const = $cast(en, 1); + if (i_const != 0) $stop; + if (en != SIXTEEN) $stop; - en = SIXTEEN; - i_const = $cast(en, 10); - if (i_const != 1) $stop; - if (en != TEN) $stop; - end + en = SIXTEEN; + i_const = $cast(en, 10); + if (i_const != 1) $stop; + if (en != TEN) $stop; + end - // Test loop - always @ (posedge clk) begin - i = $cast(en, cyc); + // Test loop + always @(posedge clk) begin + i = $cast(en, cyc); `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d i=%0d en=%0d\n", $time, cyc, i, en); + $write("[%0t] cyc==%0d i=%0d en=%0d\n", $time, cyc, i, en); `endif - cyc <= cyc + 1; - if (cyc == 10) begin - if (i != 1) $stop; - if (en != TEN) $stop; - end - else if (cyc == 11) begin - if (i != 1) $stop; - if (en != ELEVEN) $stop; - end - else if (cyc == 12) begin - if (i != 0) $stop; - if (en != ELEVEN) $stop; - end - else if (cyc == 16) begin - if (i != 1) $stop; - if (en != SIXTEEN) $stop; - end - else if (cyc == 17) begin - if (i != 0) $stop; - if (en != SIXTEEN) $stop; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc == 10) begin + if (i != 1) $stop; + if (en != TEN) $stop; + end + else if (cyc == 11) begin + if (i != 1) $stop; + if (en != ELEVEN) $stop; + end + else if (cyc == 12) begin + if (i != 0) $stop; + if (en != ELEVEN) $stop; + end + else if (cyc == 16) begin + if (i != 1) $stop; + if (en != SIXTEEN) $stop; + end + else if (cyc == 17) begin + if (i != 0) $stop; + if (en != SIXTEEN) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_castdyn_unsup_bad.out b/test_regress/t/t_castdyn_unsup_bad.out index 781b340eb..5bda83857 100644 --- a/test_regress/t/t_castdyn_unsup_bad.out +++ b/test_regress/t/t_castdyn_unsup_bad.out @@ -1,7 +1,7 @@ -%Error-UNSUPPORTED: t/t_castdyn_unsup_bad.v:13:7: Unsupported: $cast to 'string$[$]' from 'int$[string]' +%Error-UNSUPPORTED: t/t_castdyn_unsup_bad.v:13:5: Unsupported: $cast to 'string$[$]' from 'int$[string]' : ... note: In instance 't' : ... Suggest try static cast - 13 | $cast(q, aarray); - | ^~~~~ + 13 | $cast(q, aarray); + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_castdyn_unsup_bad.v b/test_regress/t/t_castdyn_unsup_bad.v index d36ae6406..f21d7b742 100644 --- a/test_regress/t/t_castdyn_unsup_bad.v +++ b/test_regress/t/t_castdyn_unsup_bad.v @@ -6,11 +6,11 @@ module t; - string q[$]; - int aarray[string]; + string q[$]; + int aarray[string]; - initial begin - $cast(q, aarray); - end + initial begin + $cast(q, aarray); + end endmodule diff --git a/test_regress/t/t_checker.v b/test_regress/t/t_checker.v index 099423cea..182fea31c 100644 --- a/test_regress/t/t_checker.v +++ b/test_regress/t/t_checker.v @@ -4,44 +4,42 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t( + input clk + ); - integer cyc = 0; + integer cyc = 0; - bit failure; - mutex check_bus(cyc, clk, failure); + bit failure; + mutex check_bus(cyc, clk, failure); - integer cyc_d1; - always @ (posedge clk) cyc_d1 <= cyc; + integer cyc_d1; + always @ (posedge clk) cyc_d1 <= cyc; - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d cyc_d1=0x%0x exp=%x failure=%x\n", - $time, cyc, cyc_d1, $onehot0(cyc), failure); + $write("[%0t] cyc==%0d cyc_d1=0x%0x exp=%x failure=%x\n", + $time, cyc, cyc_d1, $onehot0(cyc), failure); `endif - cyc <= cyc + 1; - if (cyc < 3) begin - end - else if (cyc < 90) begin - if (failure !== !$onehot0(cyc)) $stop; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc < 3) begin + end + else if (cyc < 90) begin + if (failure !== !$onehot0(cyc)) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule checker mutex (input logic [31:0] sig, input bit clk, output bit failure); - logic [31:0] last_sig; - assert property (@(negedge clk) $onehot0(sig)) - failure = 1'b0; else failure = 1'b1; - assert property (@(negedge clk) sig == last_sig + 1); - always_ff @(posedge clk) last_sig <= sig; + logic [31:0] last_sig; + assert property (@(negedge clk) $onehot0(sig)) + failure = 1'b0; else failure = 1'b1; + assert property (@(negedge clk) sig == last_sig + 1); + always_ff @(posedge clk) last_sig <= sig; endchecker diff --git a/test_regress/t/t_checker_unsup.out b/test_regress/t/t_checker_unsup.out index 47f44ac75..3f8643ee3 100644 --- a/test_regress/t/t_checker_unsup.out +++ b/test_regress/t/t_checker_unsup.out @@ -1,20 +1,20 @@ -%Error-UNSUPPORTED: t/t_checker_unsup.v:31:12: Unsupported: 'checker' below unit-level - 31 | checker checker_in_module; - | ^~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:29:11: Unsupported: 'checker' below unit-level + 29 | checker checker_in_module; + | ^~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_checker_unsup.v:37:12: Unsupported: 'checker' below unit-level - 37 | checker checker_in_pkg; - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:41:29: Unsupported: checker port variable default value - 41 | checker Chk(input defaulted = 1'b0); +%Error-UNSUPPORTED: t/t_checker_unsup.v:35:11: Unsupported: 'checker' below unit-level + 35 | checker checker_in_pkg; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:39:29: Unsupported: checker port variable default value + 39 | checker Chk(input defaulted = 1'b0); | ^ -%Error-UNSUPPORTED: t/t_checker_unsup.v:45:4: Unsupported: checker rand - 45 | rand bit randed; - | ^~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:67:4: Unsupported: default clocking identifier - 67 | default clocking clk; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:70:12: Unsupported: recursive 'checker' - 70 | checker ChkChk; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:43:3: Unsupported: checker rand + 43 | rand bit randed; + | ^~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:65:3: Unsupported: default clocking identifier + 65 | default clocking clk; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:68:11: Unsupported: recursive 'checker' + 68 | checker ChkChk; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_checker_unsup.v b/test_regress/t/t_checker_unsup.v index 4926cd4ab..7f4e236b8 100644 --- a/test_regress/t/t_checker_unsup.v +++ b/test_regress/t/t_checker_unsup.v @@ -4,83 +4,81 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t( + input clk + ); - integer cyc = 0; + integer cyc = 0; - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d\n", $time, cyc); + $write("[%0t] cyc==%0d\n", $time, cyc); `endif - cyc <= cyc + 1; - if (cyc == 0) begin - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc == 0) begin + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - Chk check(clk, cyc); + Chk check(clk, cyc); - checker checker_in_module; - endchecker + checker checker_in_module; + endchecker endmodule package Pkg; - checker checker_in_pkg; - endchecker + checker checker_in_pkg; + endchecker endpackage checker Chk(input defaulted = 1'b0); - bit clk; - bit in; - bit rst; - rand bit randed; // TODO test this + bit clk; + bit in; + bit rst; + rand bit randed; // TODO test this - int counter = 0; + int counter = 0; - int ival; - final if (ival != 1234) $stop; - genvar g; - if (0) begin - initial ival = 1; - end - else begin - initial ival = 1234; - end + int ival; + final if (ival != 1234) $stop; + genvar g; + if (0) begin + initial ival = 1; + end + else begin + initial ival = 1234; + end - int ival2; - case (1) - 0: initial ival2 = 0; - default: initial ival2 = 12345; - endcase - final if (ival2 != 12345) $stop; + int ival2; + case (1) + 0: initial ival2 = 0; + default: initial ival2 = 12345; + endcase + final if (ival2 != 12345) $stop; - default clocking clk; // TODO test this - default disable iff rst; // TODO test this + default clocking clk; // TODO test this + default disable iff rst; // TODO test this - checker ChkChk; // TODO flag unsupported - endchecker + checker ChkChk; // TODO flag unsupported + endchecker - function automatic int f; // TODO test this - endfunction + function automatic int f; // TODO test this + endfunction - clocking cb1 @(posedge clk); // TODO test this - input in; - output out; - endclocking + clocking cb1 @(posedge clk); // TODO test this + input in; + output out; + endclocking - always_ff @(posedge clk) - counter <= counter + 1'b1; + always_ff @(posedge clk) + counter <= counter + 1'b1; - a1: assert property (@(posedge clk) counter == in); + a1: assert property (@(posedge clk) counter == in); endchecker diff --git a/test_regress/t/t_class1.v b/test_regress/t/t_class1.v index 1c4dc3736..d00b5cccb 100644 --- a/test_regress/t/t_class1.v +++ b/test_regress/t/t_class1.v @@ -7,32 +7,32 @@ typedef class Cls; class Cls; - int imembera; - int imemberb; + int imembera; + int imemberb; endclass : Cls module t; - typedef Cls Cls2; + typedef Cls Cls2; - initial begin - Cls c; - Cls2 c2; - if (c != null) $stop; - if (c) $stop; - if (c2) $stop; - $display("Display: null = \"%p\"", c); // null - c = new; - c2 = new; - if (c == null) $stop; - if (!c) $stop; - if (!c2) $stop; - $display("Display: newed = \"%p\"", c); // '{imembera:0, imemberb:0} - c.imembera = 10; - c.imemberb = 20; - $display("Display: set = \"%p\"", c); // '{imembera:10, imemberb:20} - if (c.imembera != 10) $stop; - if (c.imemberb != 20) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + Cls2 c2; + if (c != null) $stop; + if (c) $stop; + if (c2) $stop; + $display("Display: null = \"%p\"", c); // null + c = new; + c2 = new; + if (c == null) $stop; + if (!c) $stop; + if (!c2) $stop; + $display("Display: newed = \"%p\"", c); // '{imembera:0, imemberb:0} + c.imembera = 10; + c.imemberb = 20; + $display("Display: set = \"%p\"", c); // '{imembera:10, imemberb:20} + if (c.imembera != 10) $stop; + if (c.imemberb != 20) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class2.v b/test_regress/t/t_class2.v index d3bfc7962..5ef217e4a 100644 --- a/test_regress/t/t_class2.v +++ b/test_regress/t/t_class2.v @@ -5,41 +5,41 @@ // SPDX-License-Identifier: CC0-1.0 package Pkg; - typedef enum { ENUMP_VAL = 33 } enump_t; + typedef enum {ENUMP_VAL = 33} enump_t; endpackage module t; -class Cls; - int imembera; - int imemberb; - typedef enum { ENUM_VAL = 22 } enum_t; -endclass : Cls + class Cls; + int imembera; + int imemberb; + typedef enum {ENUM_VAL = 22} enum_t; + endclass : Cls - Cls c; - Cls d; + Cls c; + Cls d; - Cls::enum_t e; + Cls::enum_t e; - initial begin - // Alternate between two versions to make sure we don't - // constant propagate between them. - c = new; - d = new; - e = Cls::ENUM_VAL; - c.imembera = 10; - d.imembera = 11; - c.imemberb = 20; - d.imemberb = 21; - if (c.imembera != 10) $stop; - if (d.imembera != 11) $stop; - if (c.imemberb != 20) $stop; - if (d.imemberb != 21) $stop; - if (Pkg::ENUMP_VAL != 33) $stop; - if (Cls::ENUM_VAL != 22) $stop; - if (c.ENUM_VAL != 22) $stop; - if (e != Cls::ENUM_VAL) $stop; - if (e != 22) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Alternate between two versions to make sure we don't + // constant propagate between them. + c = new; + d = new; + e = Cls::ENUM_VAL; + c.imembera = 10; + d.imembera = 11; + c.imemberb = 20; + d.imemberb = 21; + if (c.imembera != 10) $stop; + if (d.imembera != 11) $stop; + if (c.imemberb != 20) $stop; + if (d.imemberb != 21) $stop; + if (Pkg::ENUMP_VAL != 33) $stop; + if (Cls::ENUM_VAL != 22) $stop; + if (c.ENUM_VAL != 22) $stop; + if (e != Cls::ENUM_VAL) $stop; + if (e != 22) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_builtin_bad.out b/test_regress/t/t_class_builtin_bad.out index ebe06364a..60dc885a8 100644 --- a/test_regress/t/t_class_builtin_bad.out +++ b/test_regress/t/t_class_builtin_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_class_builtin_bad.v:8:17: The 'rand_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.8) +%Error: t/t_class_builtin_bad.v:8:16: The 'rand_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.8) : ... note: In instance 't' - 8 | function int rand_mode(bit onoff); - | ^~~~~~~~~ + 8 | function int rand_mode(bit onoff); + | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_builtin_bad.v:11:17: The 'constraint_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.9) +%Error: t/t_class_builtin_bad.v:11:16: The 'constraint_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.9) : ... note: In instance 't' - 11 | function int constraint_mode(bit onoff); - | ^~~~~~~~~~~~~~~ + 11 | function int constraint_mode(bit onoff); + | ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_builtin_bad.v b/test_regress/t/t_class_builtin_bad.v index 5f3c42ade..e157f5b77 100644 --- a/test_regress/t/t_class_builtin_bad.v +++ b/test_regress/t/t_class_builtin_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - function int rand_mode(bit onoff); - return 1; - endfunction - function int constraint_mode(bit onoff); - return 1; - endfunction + function int rand_mode(bit onoff); + return 1; + endfunction + function int constraint_mode(bit onoff); + return 1; + endfunction endclass module t; - initial begin - Cls c; - end + initial begin + Cls c; + end endmodule diff --git a/test_regress/t/t_class_eq.v b/test_regress/t/t_class_eq.v index be9814153..8a17f094b 100644 --- a/test_regress/t/t_class_eq.v +++ b/test_regress/t/t_class_eq.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; class A; int num; diff --git a/test_regress/t/t_class_extends_arg.v b/test_regress/t/t_class_extends_arg.v index 08f6323d2..784a66c7d 100644 --- a/test_regress/t/t_class_extends_arg.v +++ b/test_regress/t/t_class_extends_arg.v @@ -26,7 +26,7 @@ class Cls5Imp extends Base(5); // Implicit new endclass -module t (); +module t; Cls5Exp ce; Cls5Imp ci; diff --git a/test_regress/t/t_class_new_typed.v b/test_regress/t/t_class_new_typed.v index b870a8b59..76dedbf49 100644 --- a/test_regress/t/t_class_new_typed.v +++ b/test_regress/t/t_class_new_typed.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; class SuperCls; int s = 2; function new(int def = 3); diff --git a/test_regress/t/t_class_wide.v b/test_regress/t/t_class_wide.v index 271d7c1a3..22fe39756 100644 --- a/test_regress/t/t_class_wide.v +++ b/test_regress/t/t_class_wide.v @@ -12,7 +12,7 @@ class item; bit [`WIDTH-1:0] data; endclass -module t (); +module t; logic [`WIDTH-1:0] data; item item0 = new; diff --git a/test_regress/t/t_clocked_release_combo.v b/test_regress/t/t_clocked_release_combo.v index 0698ffbfd..0d5bcef73 100644 --- a/test_regress/t/t_clocked_release_combo.v +++ b/test_regress/t/t_clocked_release_combo.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTIDRIVEN -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); input clk; logic [31:0] lhs1, lhs2, rhs; @@ -36,16 +36,16 @@ module t (/*AUTOARG*/ if (cyc == 0) cond <= 1; if (cyc == 3) cond <= 0; if (cyc > 1 && cyc < 4) begin - if (lhs1 != 'hdeadbeef) $stop; - if (lhs2 != 'hfeedface) $stop; + if (lhs1 != 'hdeadbeef) $stop; + if (lhs2 != 'hfeedface) $stop; end if (cyc > 4 && cyc < 8) begin - if (lhs1 != '1) $stop; - if (lhs2 != '1) $stop; + if (lhs1 != '1) $stop; + if (lhs2 != '1) $stop; end if (cyc >= 8) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_clocker.v b/test_regress/t/t_clocker.v index e51d195e9..5816818c6 100644 --- a/test_regress/t/t_clocker.v +++ b/test_regress/t/t_clocker.v @@ -9,51 +9,51 @@ localparam ID_MSB = 1; -module t (/*AUTOARG*/ - // Inputs - clk, - res, - res8, - res16 - ); - input clk; - output reg res; - // When not inlining the below may trigger CLKDATA - output reg [7:0] res8; - output reg [15:0] res16; +module t ( /*AUTOARG*/ + // Inputs + clk, + res, + res8, + res16 +); + input clk; + output reg res; + // When not inlining the below may trigger CLKDATA + output reg [7:0] res8; + output reg [15:0] res16; - wire [7:0] clkSet; - wire clk_1; - wire [2:0] clk_3; - wire [3:0] clk_4; - wire clk_final; - reg [7:0] count; + wire [7:0] clkSet; + wire clk_1; + wire [2:0] clk_3; + wire [3:0] clk_4; + wire clk_final; + reg [7:0] count; - assign clkSet = {8{clk}}; - assign clk_4 = clkSet[7:4]; - assign clk_1 = clk_4[0];; + assign clkSet = {8{clk}}; + assign clk_4 = clkSet[7:4]; + assign clk_1 = clk_4[0]; + ; - // arraysel - assign clk_3 = {3{clk_1}}; - assign clk_final = clk_3[0]; + // arraysel + assign clk_3 = {3{clk_1}}; + assign clk_final = clk_3[0]; - assign res8 = {clk_3, 1'b0, clk_4}; - assign res16 = {count, clk_3, clk_1, clk_4}; + assign res8 = {clk_3, 1'b0, clk_4}; + assign res16 = {count, clk_3, clk_1, clk_4}; - initial - count = 0; + initial count = 0; - always @(posedge clk_final or negedge clk_final) begin - count = count + 1; - res <= clk_final; - if ( count == 8'hf) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk_final or negedge clk_final) begin + count = count + 1; + res <= clk_final; + if (count == 8'hf) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_clocking_empty_block.v b/test_regress/t/t_clocking_empty_block.v index 76d371dcb..3bacba39b 100644 --- a/test_regress/t/t_clocking_empty_block.v +++ b/test_regress/t/t_clocking_empty_block.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Alex Mykyta // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; logic clk = 0; logic x; logic y; diff --git a/test_regress/t/t_comb_do_not_convert_to.v b/test_regress/t/t_comb_do_not_convert_to.v index 33b172315..b8250eb1c 100644 --- a/test_regress/t/t_comb_do_not_convert_to.v +++ b/test_regress/t/t_comb_do_not_convert_to.v @@ -13,45 +13,45 @@ module t ( output reg o_3, output reg o_4, output reg o_5 - ); +); - input clk; + input clk; - reg a = 0; - reg b = 0; + reg a = 0; + reg b = 0; - event e; + event e; - // We must not convert these blocks into combinational blocks + // We must not convert these blocks into combinational blocks - always @(i) begin - a <= ~a; - o_0 = i; - end + always @(i) begin + a <= ~a; + o_0 = i; + end - always @(i) begin - force b = 1; - o_1 = i; - end + always @(i) begin + force b = 1; + o_1 = i; + end - always @(i) begin - release b; - o_2 = i; - end + always @(i) begin + release b; + o_2 = i; + end - always @(i) begin - -> e; - o_3 = i; - end + always @(i) begin + ->e; + o_3 = i; + end - always @(i) begin - ->> e; - o_4 = i; - end + always @(i) begin + ->>e; + o_4 = i; + end - always @(i) begin - $display("Hello"); - o_5 = i; - end + always @(i) begin + $display("Hello"); + o_5 = i; + end endmodule diff --git a/test_regress/t/t_comb_input_0.v b/test_regress/t/t_comb_input_0.v index 8ed63208b..003785e9b 100644 --- a/test_regress/t/t_comb_input_0.v +++ b/test_regress/t/t_comb_input_0.v @@ -7,9 +7,9 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module top( - clk, - inc +module top ( + clk, + inc ); input clk; @@ -23,7 +23,7 @@ module top( always @(posedge clk) begin $display("cyc: %d sum: %d", cyc, sum); - if (sum != 2*cyc + 1) $stop; + if (sum != 2 * cyc + 1) $stop; cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_comb_input_1.v b/test_regress/t/t_comb_input_1.v index 98a81e175..54d30f01b 100644 --- a/test_regress/t/t_comb_input_1.v +++ b/test_regress/t/t_comb_input_1.v @@ -7,9 +7,9 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module top( - clk, - inc +module top ( + clk, + inc ); input clk; @@ -28,7 +28,7 @@ module top( always @(posedge clk) begin $display("cyc: %d sum: %d", cyc, sum); - if (sum != 2*cyc + 1) $stop; + if (sum != 2 * cyc + 1) $stop; cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_comb_input_2.v b/test_regress/t/t_comb_input_2.v index d2047021b..39d1acaef 100644 --- a/test_regress/t/t_comb_input_2.v +++ b/test_regress/t/t_comb_input_2.v @@ -14,9 +14,9 @@ `define IMPURE_ONE (|($random | $random)) `endif -module top( - clk, - inc +module top ( + clk, + inc ); input clk; @@ -37,7 +37,7 @@ module top( always @(posedge clk) begin $display("cyc: %d sum: %d", cyc, sum); - if (sum != 2*cyc + 1) $stop; + if (sum != 2 * cyc + 1) $stop; cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.v b/test_regress/t/t_comb_loop_through_unpacked_array.v index d7992c98f..c88b1e5d3 100644 --- a/test_regress/t/t_comb_loop_through_unpacked_array.v +++ b/test_regress/t/t_comb_loop_through_unpacked_array.v @@ -6,14 +6,14 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module top( - input wire a, - input wire b, - output wire o +module top ( + input wire a, + input wire b, + output wire o ); - logic [255:0] array [1:0]; - logic [255:0] tmp [1:0]; + logic [255:0] array[1:0]; + logic [255:0] tmp[1:0]; // Nonsensical, but needs to compile. (In some real designs we can end up // with combinational loops via unpacked arrays) diff --git a/test_regress/t/t_compiler_include.v b/test_regress/t/t_compiler_include.v index 90437a0b3..58085ee32 100644 --- a/test_regress/t/t_compiler_include.v +++ b/test_regress/t/t_compiler_include.v @@ -6,6 +6,9 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (input logic[31:0] in, output logic[31:0] out); - assign out = in; +module t ( + input logic [31:0] in, + output logic [31:0] out +); + assign out = in; endmodule diff --git a/test_regress/t/t_compiler_include_dpi.v b/test_regress/t/t_compiler_include_dpi.v index 25f6dd00a..297cade39 100644 --- a/test_regress/t/t_compiler_include_dpi.v +++ b/test_regress/t/t_compiler_include_dpi.v @@ -7,25 +7,30 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; - int a = 123; - int b = 321; - int out; + int a = 123; + int b = 321; + int out; - import "DPI-C" function void dpii_add - (int a, int b, ref int out); - import "DPI-C" function int dpii_add_check - (int actual, int expected); + import "DPI-C" function void dpii_add( + int a, + int b, + ref int out + ); + import "DPI-C" function int dpii_add_check( + int actual, + int expected + ); - initial begin - dpii_add(a, b, out); - if (dpii_add_check(out, (a + b)) != 1) begin - $write("%%Error: Failure in DPI tests\n"); - $stop; - end - else begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + initial begin + dpii_add(a, b, out); + if (dpii_add_check(out, (a + b)) != 1) begin + $write("%%Error: Failure in DPI tests\n"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_concat_casts.v b/test_regress/t/t_concat_casts.v index 014348ad7..c90070bee 100644 --- a/test_regress/t/t_concat_casts.v +++ b/test_regress/t/t_concat_casts.v @@ -5,37 +5,39 @@ // SPDX-License-Identifier: CC0-1.0 package my_pkg; - typedef enum logic [1:0] { - SIG_0, SIG_1, SIG_2 - } sig_t; + typedef enum logic [1:0] { + SIG_0, + SIG_1, + SIG_2 + } sig_t; endpackage : my_pkg module t; - import my_pkg::*; + import my_pkg::*; - typedef logic [7:0] foo_t; - typedef logic [31:0] bar_t; + typedef logic [7:0] foo_t; + typedef logic [31:0] bar_t; - bar_t [1:0] the_bars; + bar_t [1:0] the_bars; - foo_t [0:0][1:0] the_foos; + foo_t [0:0][1:0] the_foos; - always_comb begin - the_bars = {32'd7, 32'd8}; - the_foos[0] = {foo_t'(the_bars[1]), foo_t'(the_bars[0])}; - end + always_comb begin + the_bars = {32'd7, 32'd8}; + the_foos[0] = {foo_t'(the_bars[1]), foo_t'(the_bars[0])}; + end - logic [6:0] data; - logic [2:0] opt; + logic [6:0] data; + logic [2:0] opt; - assign data = 7'b110_0101; - assign opt = {data[5], sig_t'(data[1:0])}; + assign data = 7'b110_0101; + assign opt = {data[5], sig_t'(data[1:0])}; - initial begin - if (the_foos != 'h0708) $stop(); - if (opt != 'b101) $stop(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (the_foos != 'h0708) $stop(); + if (opt != 'b101) $stop(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_concat_impure.v b/test_regress/t/t_concat_impure.v index 16499b370..3c28aabf1 100644 --- a/test_regress/t/t_concat_impure.v +++ b/test_regress/t/t_concat_impure.v @@ -7,21 +7,21 @@ int global_variable = 0; function int side_effect; - global_variable++; + global_variable++; return 1; endfunction module t; - reg [15:0] x; - reg [15:0] y; - initial begin - {x, y} = side_effect() + 2; + reg [15:0] x; + reg [15:0] y; + initial begin + {x, y} = side_effect() + 2; - if (y != 3) $stop; - if (x != 0) $stop; - if (global_variable != 1) $stop; + if (y != 3) $stop; + if (x != 0) $stop; + if (global_variable != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_concat_link_bad.out b/test_regress/t/t_concat_link_bad.out index a4fc82936..82f785bf5 100644 --- a/test_regress/t/t_concat_link_bad.out +++ b/test_regress/t/t_concat_link_bad.out @@ -1,25 +1,25 @@ -%Error: t/t_concat_link_bad.v:13:20: Syntax error: Not expecting REPLICATE under a DOT in dotted expression - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ - t/t_concat_link_bad.v:13:34: ... Resolving this reference - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ +%Error: t/t_concat_link_bad.v:13:18: Syntax error: Not expecting REPLICATE under a DOT in dotted expression + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ + t/t_concat_link_bad.v:13:32: ... Resolving this reference + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_concat_link_bad.v:13:26: Syntax error: Not expecting CONCAT under a REPLICATE in dotted expression - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ - t/t_concat_link_bad.v:13:34: ... Resolving this reference - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ -%Error: t/t_concat_link_bad.v:13:20: Syntax error: Not expecting CONST under a REPLICATE in dotted expression - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ - t/t_concat_link_bad.v:13:34: ... Resolving this reference - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ -%Warning-IMPLICIT: t/t_concat_link_bad.v:13:12: Signal definition not found, creating implicitly: 'bar_s' - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^~~~~ +%Error: t/t_concat_link_bad.v:13:24: Syntax error: Not expecting CONCAT under a REPLICATE in dotted expression + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ + t/t_concat_link_bad.v:13:32: ... Resolving this reference + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ +%Error: t/t_concat_link_bad.v:13:18: Syntax error: Not expecting CONST under a REPLICATE in dotted expression + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ + t/t_concat_link_bad.v:13:32: ... Resolving this reference + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ +%Warning-IMPLICIT: t/t_concat_link_bad.v:13:10: Signal definition not found, creating implicitly: 'bar_s' + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^~~~~ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_concat_link_bad.v b/test_regress/t/t_concat_link_bad.v index 576f03b59..e05d338f0 100644 --- a/test_regress/t/t_concat_link_bad.v +++ b/test_regress/t/t_concat_link_bad.v @@ -6,10 +6,10 @@ module t; - typedef logic [3:0] foo_t; + typedef logic [3:0] foo_t; - foo_t foo_s; + foo_t foo_s; - assign bar_s = {foo_s, foo_s}.f1; + assign bar_s = {foo_s, foo_s}.f1; endmodule diff --git a/test_regress/t/t_concat_opt.v b/test_regress/t/t_concat_opt.v index 3f85fa53b..adfde02b3 100644 --- a/test_regress/t/t_concat_opt.v +++ b/test_regress/t/t_concat_opt.v @@ -6,66 +6,62 @@ // // The test was added together with the concat optimization. -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [31:0] in_a; - reg [31:0] in_b; - reg [31:0] in_c; - reg [31:0] in_d; - reg [31:0] in_e; - reg [15:0] in_f; - wire [31:0] in_g; + reg [31:0] in_a; + reg [31:0] in_b; + reg [31:0] in_c; + reg [31:0] in_d; + reg [31:0] in_e; + reg [15:0] in_f; + wire [31:0] in_g; - assign in_g = in_a << 4; + assign in_g = in_a << 4; - reg [31:0] out_x; - reg [31:0] out_y; - reg [31:0] out_z; - reg [31:0] out_o; - reg [31:0] out_p; - reg [31:0] out_q; + reg [31:0] out_x; + reg [31:0] out_y; + reg [31:0] out_z; + reg [31:0] out_o; + reg [31:0] out_p; + reg [31:0] out_q; - assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f}; - assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]}; - assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]}; - assign out_o = out_z | out_y; - assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]}; - assign out_q = {{in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]}}; + assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f}; + assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]}; + assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]}; + assign out_o = out_z | out_y; + assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]}; + assign out_q = { + {in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, + {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]} + }; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - in_a <= cyc; - in_b <= cyc + 1; - in_c <= cyc + 3; - in_d <= cyc + 8; - in_e <= cyc; - in_f <= cyc[15:0]; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + in_a <= cyc; + in_b <= cyc + 1; + in_c <= cyc + 3; + in_d <= cyc + 8; + in_e <= cyc; + in_f <= cyc[15:0]; - if (out_x != (in_a & {2{in_f}})) - $stop; - if (out_y != (in_a&in_b)) - $stop; - if (out_z != (in_e&in_d&in_c)) - $stop; - if (out_o != (((in_a&in_b)|(in_c&in_e&in_d)))) - $stop; - if (out_p != (in_a & {2{in_f}} | in_e)) - $stop; - if (out_q != (in_a ^ in_g)) - $stop; + if (out_x != (in_a & {2{in_f}})) $stop; + if (out_y != (in_a & in_b)) $stop; + if (out_z != (in_e & in_d & in_c)) $stop; + if (out_o != (((in_a & in_b) | (in_c & in_e & in_d)))) $stop; + if (out_p != (in_a & {2{in_f}} | in_e)) $stop; + if (out_q != (in_a ^ in_g)) $stop; - if (cyc==100) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 100) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule diff --git a/test_regress/t/t_concat_or.v b/test_regress/t/t_concat_or.v index 5fa2acd57..03017634d 100644 --- a/test_regress/t/t_concat_or.v +++ b/test_regress/t/t_concat_or.v @@ -4,69 +4,71 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - i299, - // Inputs - i190, i191, i192, i193, i194, i195, i196, i197, i198, i199, i200, i201, i202, - i203, i204, i205, i182, i183, i184, i185, i186, i187, i188, i189, i206, i282, - i284, i286, i287, i289, i290, i294, i34, i288, i31, i296, i37, i38 - ); - input [3:0] i190; - input [3:0] i191; - input [3:0] i192; - input [3:0] i193; - input [3:0] i194; - input [3:0] i195; - input [3:0] i196; - input [3:0] i197; - input [3:0] i198; - input [3:0] i199; - input [3:0] i200; - input [3:0] i201; - input [3:0] i202; - input [3:0] i203; - input [3:0] i204; - input [3:0] i205; - input [3:0] i182; - input [3:0] i183; - input [3:0] i184; - input [3:0] i185; - input [3:0] i186; - input [3:0] i187; - input [3:0] i188; - input [3:0] i189; - input [3:0] i206; - input [3:0] i282; - input [3:0] i284; - input [3:0] i286; - input [3:0] i287; - input [3:0] i289; - input [3:0] i290; - input [3:0] i294; - input [3:0] i34; - input [3:0] i288; - input [3:0] i31; - input [3:0] i296; - input [3:0] i37; - input [3:0] i38; +// verilog_format: off - output [3:0] i299; - assign i299 = { i296[2:0] | i31[3:1] | i282[3:1] | i284[3:1] | i34[3:1] - | i286[3:1] | i287[3:1] | i37[3:1] | i38[3:1] - | i288[3:1] | i289[3:1] | i290[3:1] | i182[3:1] - | i183[3:1] | i184[3:1] | i185[3:1] | i186[3:1] - | i187[3:1] | i188[3:1] | i189[3:1] | i190[3:1] - | i191[3:1] | i192[3:1] | i193[3:1] | i194[3:1] - | i195[3:1] | i196[3:1] | i197[3:1] | i198[3:1] - | i199[3:1] | i200[3:1] | i201[3:1] | i202[3:1] - | i203[3:1] | i204[3:1] | i205[3:1] | i206[3:1] - , - i294[0] | i289[0] | i290[0] | i182[0] | i183[0] - | i184[0] | i185[0] | i186[0] | i187[0] | i188[0] - | i189[0] | i190[0] | i191[0] | i192[0] | i193[0] - | i194[0] | i195[0] | i196[0] | i197[0] | i198[0] - | i199[0] | i200[0] | i201[0] | i202[0] | i203[0] - | i204[0] | i205[0] | i206[0] }; +module t(/*AUTOARG*/ + // Outputs + i299, + // Inputs + i190, i191, i192, i193, i194, i195, i196, i197, i198, i199, i200, i201, i202, + i203, i204, i205, i182, i183, i184, i185, i186, i187, i188, i189, i206, i282, + i284, i286, i287, i289, i290, i294, i34, i288, i31, i296, i37, i38 + ); + input [3:0] i190; + input [3:0] i191; + input [3:0] i192; + input [3:0] i193; + input [3:0] i194; + input [3:0] i195; + input [3:0] i196; + input [3:0] i197; + input [3:0] i198; + input [3:0] i199; + input [3:0] i200; + input [3:0] i201; + input [3:0] i202; + input [3:0] i203; + input [3:0] i204; + input [3:0] i205; + input [3:0] i182; + input [3:0] i183; + input [3:0] i184; + input [3:0] i185; + input [3:0] i186; + input [3:0] i187; + input [3:0] i188; + input [3:0] i189; + input [3:0] i206; + input [3:0] i282; + input [3:0] i284; + input [3:0] i286; + input [3:0] i287; + input [3:0] i289; + input [3:0] i290; + input [3:0] i294; + input [3:0] i34; + input [3:0] i288; + input [3:0] i31; + input [3:0] i296; + input [3:0] i37; + input [3:0] i38; + + output [3:0] i299; + assign i299 = { i296[2:0] | i31[3:1] | i282[3:1] | i284[3:1] | i34[3:1] + | i286[3:1] | i287[3:1] | i37[3:1] | i38[3:1] + | i288[3:1] | i289[3:1] | i290[3:1] | i182[3:1] + | i183[3:1] | i184[3:1] | i185[3:1] | i186[3:1] + | i187[3:1] | i188[3:1] | i189[3:1] | i190[3:1] + | i191[3:1] | i192[3:1] | i193[3:1] | i194[3:1] + | i195[3:1] | i196[3:1] | i197[3:1] | i198[3:1] + | i199[3:1] | i200[3:1] | i201[3:1] | i202[3:1] + | i203[3:1] | i204[3:1] | i205[3:1] | i206[3:1] + , + i294[0] | i289[0] | i290[0] | i182[0] | i183[0] + | i184[0] | i185[0] | i186[0] | i187[0] | i188[0] + | i189[0] | i190[0] | i191[0] | i192[0] | i193[0] + | i194[0] | i195[0] | i196[0] | i197[0] | i198[0] + | i199[0] | i200[0] | i201[0] | i202[0] | i203[0] + | i204[0] | i205[0] | i206[0] }; endmodule diff --git a/test_regress/t/t_concat_sel.v b/test_regress/t/t_concat_sel.v index 295680318..7cca57d66 100644 --- a/test_regress/t/t_concat_sel.v +++ b/test_regress/t/t_concat_sel.v @@ -5,70 +5,70 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [3:0] a = crc[3:0]; - wire [3:0] b = crc[19:16]; + // Take CRC data and apply to testblock inputs + wire [3:0] a = crc[3:0]; + wire [3:0] b = crc[19:16]; - // TEST - wire [3:0] out1 = {a,b}[2 +: 4]; - wire [3:0] out2 = {a,b}[5 -: 4]; - wire [3:0] out3 = {a,b}[5 : 2]; - wire [0:0] out4 = {a,b}[2]; + // TEST + wire [3:0] out1 = {a,b}[2 +: 4]; + wire [3:0] out2 = {a,b}[5 -: 4]; + wire [3:0] out3 = {a,b}[5 : 2]; + wire [0:0] out4 = {a,b}[2]; - // Aggregate outputs into a single result vector - wire [63:0] result = {51'h0, out4, out3, out2, out1}; + // Aggregate outputs into a single result vector + wire [63:0] result = {51'h0, out4, out3, out2, out1}; - initial begin - if ({16'h1234}[0] != 1'b0) $stop; - if ({16'h1234}[2] != 1'b1) $stop; - if ({16'h1234}[11:4] != 8'h23) $stop; - if ({16'h1234}[4+:8] != 8'h23) $stop; - if ({16'h1234}[11-:8] != 8'h23) $stop; - if ({8'h12, 8'h34}[0] != 1'b0) $stop; - if ({8'h12, 8'h34}[2] != 1'b1) $stop; - if ({8'h12, 8'h34}[11:4] != 8'h23) $stop; - if ({8'h12, 8'h34}[4+:8] != 8'h23) $stop; - if ({8'h12, 8'h34}[11-:8] != 8'h23) $stop; + initial begin + if ({16'h1234}[0] != 1'b0) $stop; + if ({16'h1234}[2] != 1'b1) $stop; + if ({16'h1234}[11:4] != 8'h23) $stop; + if ({16'h1234}[4+:8] != 8'h23) $stop; + if ({16'h1234}[11-:8] != 8'h23) $stop; + if ({8'h12, 8'h34}[0] != 1'b0) $stop; + if ({8'h12, 8'h34}[2] != 1'b1) $stop; + if ({8'h12, 8'h34}[11:4] != 8'h23) $stop; + if ({8'h12, 8'h34}[4+:8] != 8'h23) $stop; + if ({8'h12, 8'h34}[11-:8] != 8'h23) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; - end - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h4afe43fb79d7b71e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + end endmodule diff --git a/test_regress/t/t_concat_string.v b/test_regress/t/t_concat_string.v index a8c36346e..b8666f582 100644 --- a/test_regress/t/t_concat_string.v +++ b/test_regress/t/t_concat_string.v @@ -7,25 +7,27 @@ typedef enum {efgh} en; module t; - initial begin - en e; - string s; + initial begin + en e; + string s; - s = {"a", "b"}; - if (s != "ab") $stop; + s = {"a", "b"}; + if (s != "ab") $stop; - e = efgh; - s = {"abcd", e.name(), "ijkl"}; - if (s != "abcdefghijkl") $stop; + e = efgh; + s = {"abcd", e.name(), "ijkl"}; + if (s != "abcdefghijkl") $stop; - // hang V3Width if complexity grows exponential (2**52 should suffice) - s = {"a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", - "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z", - "a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", - "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z"}; - if (s != "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz") $stop; + // hang V3Width if complexity grows exponential (2**52 should suffice) + // verilog_format: off + s = {"a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", + "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z", + "a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", + "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z"}; + // verilog_format: on + if (s != "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_concat_unpack.v b/test_regress/t/t_concat_unpack.v index 41ff5f43c..54d10648b 100644 --- a/test_regress/t/t_concat_unpack.v +++ b/test_regress/t/t_concat_unpack.v @@ -4,33 +4,31 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - wire [31:0] arr [0:7]; - assign arr[0:7] = { - {16'hffff, 16'h0000}, - {16'h0000, 16'h0000}, - {16'h0a0a, 16'h0000}, - {16'ha0a0, 16'h0000}, - {16'hffff, 16'h0000}, - {16'h0000, 16'h0000}, - {16'h0a0a, 16'h0000}, - {16'ha0a0, 16'h0000} - }; + wire [31:0] arr[0:7]; + assign arr[0:7] = { + {16'hffff, 16'h0000}, + {16'h0000, 16'h0000}, + {16'h0a0a, 16'h0000}, + {16'ha0a0, 16'h0000}, + {16'hffff, 16'h0000}, + {16'h0000, 16'h0000}, + {16'h0a0a, 16'h0000}, + {16'ha0a0, 16'h0000} + }; - int cyc = 0; + int cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 9) begin - if (arr[0] !== 32'hffff0000) $stop; - if (arr[7] !== 32'ha0a00000) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 9) begin + if (arr[0] !== 32'hffff0000) $stop; + if (arr[7] !== 32'ha0a00000) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_const.v b/test_regress/t/t_const.v index e142ce051..4ae937699 100644 --- a/test_regress/t/t_const.v +++ b/test_regress/t/t_const.v @@ -6,17 +6,17 @@ module t; - initial begin - // verilator lint_off WIDTH - if (32'hxxxxxxxx !== 'hx) $stop; - if (32'hzzzzzzzz !== 'hz) $stop; - if (32'h???????? !== 'h?) $stop; - if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; - if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; - if (68'h?_????????_???????? !== 'd?) $stop; - // verilator lint_on WIDTH - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // verilator lint_off WIDTH + if (32'hxxxxxxxx !== 'hx) $stop; + if (32'hzzzzzzzz !== 'hz) $stop; + if (32'h???????? !== 'h?) $stop; + if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + if (68'h?_????????_???????? !== 'd?) $stop; + // verilator lint_on WIDTH + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_const_bad.out b/test_regress/t/t_const_bad.out index 5ef1e1fd6..db77ac73a 100644 --- a/test_regress/t/t_const_bad.out +++ b/test_regress/t/t_const_bad.out @@ -1,15 +1,15 @@ -%Warning-WIDTHXZEXPAND: t/t_const_bad.v:13:39: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +%Warning-WIDTHXZEXPAND: t/t_const_bad.v:13:37: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : ... note: In instance 't' - 13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; - | ^~~ + 13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + | ^~~ ... For warning description see https://verilator.org/warn/WIDTHXZEXPAND?v=latest ... Use "/* verilator lint_off WIDTHXZEXPAND */" and lint_on around source to disable this message. -%Warning-WIDTHXZEXPAND: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz +%Warning-WIDTHXZEXPAND: t/t_const_bad.v:14:37: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : ... note: In instance 't' - 14 | if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; - | ^~~ -%Warning-WIDTHXZEXPAND: t/t_const_bad.v:15:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz + 14 | if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + | ^~~ +%Warning-WIDTHXZEXPAND: t/t_const_bad.v:15:37: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : ... note: In instance 't' - 15 | if (68'h?_????????_???????? !== 'd?) $stop; - | ^~~ + 15 | if (68'h?_????????_???????? !== 'd?) $stop; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_bad.v b/test_regress/t/t_const_bad.v index 6d3edd361..ba87ae32f 100644 --- a/test_regress/t/t_const_bad.v +++ b/test_regress/t/t_const_bad.v @@ -6,15 +6,15 @@ module t; - initial begin - if (32'hxxxxxxxx !== 'hx) $stop; - if (32'hzzzzzzzz !== 'hz) $stop; - if (32'h???????? !== 'h?) $stop; - if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; - if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; - if (68'h?_????????_???????? !== 'd?) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (32'hxxxxxxxx !== 'hx) $stop; + if (32'hzzzzzzzz !== 'hz) $stop; + if (32'h???????? !== 'h?) $stop; + if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + if (68'h?_????????_???????? !== 'd?) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_const_bitoptree_bug3096.v b/test_regress/t/t_const_bitoptree_bug3096.v index 6d783a25e..51c125982 100644 --- a/test_regress/t/t_const_bitoptree_bug3096.v +++ b/test_regress/t/t_const_bitoptree_bug3096.v @@ -8,17 +8,17 @@ // From issue #3096 -module decoder( - input wire [31:0] instr_i, - // Making 'a' an output preserves it as a sub-expression and causes a missing clean - output wire a, - output wire illegal_instr_o - ); - /* verilator lint_off WIDTH */ - wire b = ! instr_i[12:5]; - wire c = ! instr_i[1:0]; - wire d = ! instr_i[15:13]; - /* verilator lint_on WIDTH */ - assign a = d ? b : 1'h1; - assign illegal_instr_o = c ? a : 1'h0; +module decoder ( + input wire [31:0] instr_i, + // Making 'a' an output preserves it as a sub-expression and causes a missing clean + output wire a, + output wire illegal_instr_o +); + /* verilator lint_off WIDTH */ + wire b = !instr_i[12:5]; + wire c = !instr_i[1:0]; + wire d = !instr_i[15:13]; + /* verilator lint_on WIDTH */ + assign a = d ? b : 1'h1; + assign illegal_instr_o = c ? a : 1'h0; endmodule diff --git a/test_regress/t/t_const_dec_mixed_bad.out b/test_regress/t/t_const_dec_mixed_bad.out index 8e07f25e2..5b452d6f8 100644 --- a/test_regress/t/t_const_dec_mixed_bad.out +++ b/test_regress/t/t_const_dec_mixed_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_const_dec_mixed_bad.v:9:30: Mixing X/Z/? with digits not legal in decimal constant: x_1 - 9 | parameter [200:0] MIXED = 32'dx_1; - | ^~~~~~~ +%Error: t/t_const_dec_mixed_bad.v:9:29: Mixing X/Z/? with digits not legal in decimal constant: x_1 + 9 | parameter [200:0] MIXED = 32'dx_1; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_const_dec_mixed_bad.v b/test_regress/t/t_const_dec_mixed_bad.v index 99ac432f4..2bd1fc8fa 100644 --- a/test_regress/t/t_const_dec_mixed_bad.v +++ b/test_regress/t/t_const_dec_mixed_bad.v @@ -6,6 +6,6 @@ module t; - parameter [200:0] MIXED = 32'dx_1; + parameter [200:0] MIXED = 32'dx_1; endmodule diff --git a/test_regress/t/t_const_hi.v b/test_regress/t/t_const_hi.v index 5843d2d18..14b5ab813 100644 --- a/test_regress/t/t_const_hi.v +++ b/test_regress/t/t_const_hi.v @@ -4,50 +4,47 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [1:0] reg_i; - reg [1049:0] pad0; - reg [1049:0] reg_o; - reg [1049:0] spad1; + integer cyc = 0; + reg [1:0] reg_i; + reg [1049:0] pad0; + reg [1049:0] reg_o; + reg [1049:0] spad1; - /*AUTOWIRE*/ + /*AUTOWIRE*/ - always_comb begin - if (reg_i[1] == 1'b1) - reg_o = {986'd0, 64'hffff0000ffff0000}; - else if (reg_i[0] == 1'b1) - reg_o = {64'hffff0000ffff0000, 986'd0}; - else - reg_o = 1050'd0; - end + always_comb begin + if (reg_i[1] == 1'b1) reg_o = {986'd0, 64'hffff0000ffff0000}; + else if (reg_i[0] == 1'b1) reg_o = {64'hffff0000ffff0000, 986'd0}; + else reg_o = 1050'd0; + end - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - reg_i <= 2'b00; - pad0 <= '1; - spad1 <= '1; - end - else if (cyc == 1) begin - reg_i <= 2'b01; - end - else if (cyc == 2) begin - if (reg_o != {64'hffff0000ffff0000, 986'd0}) $stop; - reg_i <= 2'b10; - end - else if (cyc == 99) begin - if (reg_o != {986'd0, 64'hffff0000ffff0000}) $stop; - if (pad0 != '1) $stop; - if (spad1 != '1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + reg_i <= 2'b00; + pad0 <= '1; + spad1 <= '1; + end + else if (cyc == 1) begin + reg_i <= 2'b01; + end + else if (cyc == 2) begin + if (reg_o != {64'hffff0000ffff0000, 986'd0}) $stop; + reg_i <= 2'b10; + end + else if (cyc == 99) begin + if (reg_o != {986'd0, 64'hffff0000ffff0000}) $stop; + if (pad0 != '1) $stop; + if (spad1 != '1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_const_number_bad.out b/test_regress/t/t_const_number_bad.out index cfd7ea94e..795db19d0 100644 --- a/test_regress/t/t_const_number_bad.out +++ b/test_regress/t/t_const_number_bad.out @@ -1,26 +1,26 @@ -%Error: t/t_const_number_bad.v:9:29: Number is missing value digits: 32'd - 9 | parameter integer FOO2 = 32'd-6; - | ^~~~ +%Error: t/t_const_number_bad.v:9:28: Number is missing value digits: 32'd + 9 | parameter integer FOO2 = 32'd-6; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_const_number_bad.v:10:29: Number is missing value digits: 32'd - 10 | parameter integer FOO3 = 32'd; - | ^~~~ -%Error: t/t_const_number_bad.v:11:29: Number is missing value digits: 32'h - 11 | parameter integer FOO4 = 32'h; - | ^~~~ -%Error: t/t_const_number_bad.v:13:29: Illegal character in binary constant: 2 - 13 | parameter integer FOO5 = 32'b2; - | ^~~~~ -%Error: t/t_const_number_bad.v:14:29: Illegal character in octal constant - 14 | parameter integer FOO6 = 32'o8; - | ^~~~~ -%Error: t/t_const_number_bad.v:17:33: Illegal character in binary constant: 4 - 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; - | ^~~~~~ -%Error: t/t_const_number_bad.v:17:33: Too many digits for 1 bit number: '1'b1?4' - 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; - | ^~~~~~ -%Error: t/t_const_number_bad.v:17:39: syntax error, unexpected INTEGER NUMBER, expecting ';' - 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; - | ^~~ +%Error: t/t_const_number_bad.v:10:28: Number is missing value digits: 32'd + 10 | parameter integer FOO3 = 32'd; + | ^~~~ +%Error: t/t_const_number_bad.v:11:28: Number is missing value digits: 32'h + 11 | parameter integer FOO4 = 32'h; + | ^~~~ +%Error: t/t_const_number_bad.v:13:28: Illegal character in binary constant: 2 + 13 | parameter integer FOO5 = 32'b2; + | ^~~~~ +%Error: t/t_const_number_bad.v:14:28: Illegal character in octal constant + 14 | parameter integer FOO6 = 32'o8; + | ^~~~~ +%Error: t/t_const_number_bad.v:17:32: Illegal character in binary constant: 4 + 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; + | ^~~~~~ +%Error: t/t_const_number_bad.v:17:32: Too many digits for 1 bit number: '1'b1?4' + 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; + | ^~~~~~ +%Error: t/t_const_number_bad.v:17:38: syntax error, unexpected INTEGER NUMBER, expecting ';' + 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_number_bad.v b/test_regress/t/t_const_number_bad.v index b10a58750..b0d41042f 100644 --- a/test_regress/t/t_const_number_bad.v +++ b/test_regress/t/t_const_number_bad.v @@ -6,14 +6,14 @@ module t; - parameter integer FOO2 = 32'd-6; // Minus doesn't go here - parameter integer FOO3 = 32'd; - parameter integer FOO4 = 32'h; + parameter integer FOO2 = 32'd-6; // Minus doesn't go here + parameter integer FOO3 = 32'd; + parameter integer FOO4 = 32'h; - parameter integer FOO5 = 32'b2; - parameter integer FOO6 = 32'o8; + parameter integer FOO5 = 32'b2; + parameter integer FOO6 = 32'o8; - // See bug2432, this is questionable, some simulators take this, others do not - parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; // bug2432 - intentionally no spaces near ? + // See bug2432, this is questionable, some simulators take this, others do not + parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; // bug2432 - intentionally no spaces near ? endmodule diff --git a/test_regress/t/t_const_number_unsized.v b/test_regress/t/t_const_number_unsized.v index e3d32a420..4f351ecda 100644 --- a/test_regress/t/t_const_number_unsized.v +++ b/test_regress/t/t_const_number_unsized.v @@ -4,53 +4,56 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - int s; - logic [255:0] n; + int s; + logic [255:0] n; - initial begin - s = $bits('d123); - `checkd(s, 32); - s = $bits('h123); - `checkd(s, 32); - s = $bits('o123); - `checkd(s, 32); - s = $bits('b101); - `checkd(s, 32); + initial begin + s = $bits('d123); + `checkd(s, 32); + s = $bits('h123); + `checkd(s, 32); + s = $bits('o123); + `checkd(s, 32); + s = $bits('b101); + `checkd(s, 32); - // verilator lint_off WIDTHEXPAND + // verilator lint_off WIDTHEXPAND - // Used to warn "Too many digits for 32 bit number" - // ... As that number was unsized ('...) it is limited to 32 bits - // But other simulators don't warn, and language of (IEEE 1800-2023 5.7.1) - // has been updated to accepting this legal - n = 'd123456789123456789123456789; - s = $bits('d123456789123456789123456789); - `checkh(n, 256'h661efdf2e3b19f7c045f15); - `checkd(s, 87); + // Used to warn "Too many digits for 32 bit number" + // ... As that number was unsized ('...) it is limited to 32 bits + // But other simulators don't warn, and language of (IEEE 1800-2023 5.7.1) + // has been updated to accepting this legal + n = 'd123456789123456789123456789; + s = $bits('d123456789123456789123456789); + `checkh(n, 256'h661efdf2e3b19f7c045f15); + `checkd(s, 87); - n = 'h123456789123456789123456789; - s = $bits('h123456789123456789123456789); - `checkh(n, 256'h123456789123456789123456789); - `checkd(s, 108); + n = 'h123456789123456789123456789; + s = $bits('h123456789123456789123456789); + `checkh(n, 256'h123456789123456789123456789); + `checkd(s, 108); - //FIX octal digits in master test, if don't merge this - n = 'o123456777123456777123456777; - s = $bits('o123456777123456777123456777); - `checkh(n, 256'h53977fca72eff94e5dff); - `checkd(s, 81); + //FIX octal digits in master test, if don't merge this + n = 'o123456777123456777123456777; + s = $bits('o123456777123456777123456777); + `checkh(n, 256'h53977fca72eff94e5dff); + `checkd(s, 81); - n = 'b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010; - s = $bits('b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010); - `checkh(n, 256'haaaaaaaaaaaaaaaaaaaaaaa); - `checkd(s, 92); + n = 'b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010; + s = $bits('b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010 + ); + `checkh(n, 256'haaaaaaaaaaaaaaaaaaaaaaa); + `checkd(s, 92); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_const_number_v_bad.out b/test_regress/t/t_const_number_v_bad.out index b222a145f..cc3f8bd2c 100644 --- a/test_regress/t/t_const_number_v_bad.out +++ b/test_regress/t/t_const_number_v_bad.out @@ -1,21 +1,21 @@ -%Warning-NEWERSTD: t/t_const_number_v_bad.v:11:25: Unbased unsized literals require IEEE 1800-2005 or later. - 11 | wire [127:0] FOO1 = '0; - | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:11:23: Unbased unsized literals require IEEE 1800-2005 or later. + 11 | wire [127:0] FOO1 = '0; + | ^~ ... For warning description see https://verilator.org/warn/NEWERSTD?v=latest ... Use "/* verilator lint_off NEWERSTD */" and lint_on around source to disable this message. -%Warning-NEWERSTD: t/t_const_number_v_bad.v:12:25: Unbased unsized literals require IEEE 1800-2005 or later. - 12 | wire [127:0] FOO2 = '1; - | ^~ -%Warning-NEWERSTD: t/t_const_number_v_bad.v:13:25: Unbased unsized literals require IEEE 1800-2005 or later. - 13 | wire [127:0] FOO3 = 'x; - | ^~ -%Warning-NEWERSTD: t/t_const_number_v_bad.v:14:25: Unbased unsized literals require IEEE 1800-2005 or later. - 14 | wire [127:0] FOO4 = 'X; - | ^~ -%Warning-NEWERSTD: t/t_const_number_v_bad.v:15:25: Unbased unsized literals require IEEE 1800-2005 or later. - 15 | wire [127:0] FOO5 = 'z; - | ^~ -%Warning-NEWERSTD: t/t_const_number_v_bad.v:16:25: Unbased unsized literals require IEEE 1800-2005 or later. - 16 | wire [127:0] FOO6 = 'Z; - | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:12:23: Unbased unsized literals require IEEE 1800-2005 or later. + 12 | wire [127:0] FOO2 = '1; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:13:23: Unbased unsized literals require IEEE 1800-2005 or later. + 13 | wire [127:0] FOO3 = 'x; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:14:23: Unbased unsized literals require IEEE 1800-2005 or later. + 14 | wire [127:0] FOO4 = 'X; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:15:23: Unbased unsized literals require IEEE 1800-2005 or later. + 15 | wire [127:0] FOO5 = 'z; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:16:23: Unbased unsized literals require IEEE 1800-2005 or later. + 16 | wire [127:0] FOO6 = 'Z; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_const_number_v_bad.v b/test_regress/t/t_const_number_v_bad.v index c9564cd70..f5ef1875a 100644 --- a/test_regress/t/t_const_number_v_bad.v +++ b/test_regress/t/t_const_number_v_bad.v @@ -6,13 +6,13 @@ module t; - // "unbased_unsized_literal" is SystemVerilog only - // Should fail with "NEWERSTD" - wire [127:0] FOO1 = '0; - wire [127:0] FOO2 = '1; - wire [127:0] FOO3 = 'x; - wire [127:0] FOO4 = 'X; - wire [127:0] FOO5 = 'z; - wire [127:0] FOO6 = 'Z; + // "unbased_unsized_literal" is SystemVerilog only + // Should fail with "NEWERSTD" + wire [127:0] FOO1 = '0; + wire [127:0] FOO2 = '1; + wire [127:0] FOO3 = 'x; + wire [127:0] FOO4 = 'X; + wire [127:0] FOO5 = 'z; + wire [127:0] FOO6 = 'Z; endmodule diff --git a/test_regress/t/t_const_op_red_scope.v b/test_regress/t/t_const_op_red_scope.v index 520bc2eb8..45991e723 100644 --- a/test_regress/t/t_const_op_red_scope.v +++ b/test_regress/t/t_const_op_red_scope.v @@ -4,114 +4,120 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [7:0] in = crc[7:0]; + // Take CRC data and apply to testblock inputs + wire [7:0] in = crc[7:0]; - /*AUTOWIRE*/ + /*AUTOWIRE*/ - wire out0; - wire out1; - wire out2; - wire out3; - wire out4; - wire out5; - wire out6; - wire out7; + wire out0; + wire out1; + wire out2; + wire out3; + wire out4; + wire out5; + wire out6; + wire out7; - /*SelFlop AUTO_TEMPLATE(.n(@), + /*SelFlop AUTO_TEMPLATE(.n(@), .out(out@)); */ - SelFlop selflop0(/*AUTOINST*/ - // Outputs - .out (out0), // Templated - // Inputs - .clk (clk), - .in (in[7:0]), - .n (0)); // Templated - SelFlop selflop1(/*AUTOINST*/ - // Outputs - .out (out1), // Templated - // Inputs - .clk (clk), - .in (in[7:0]), - .n (1)); // Templated - SelFlop selflop2(/*AUTOINST*/ - // Outputs - .out (out2), // Templated - // Inputs - .clk (clk), - .in (in[7:0]), - .n (2)); // Templated - SelFlop selflop3(/*AUTOINST*/ - // Outputs - .out (out3), // Templated - // Inputs - .clk (clk), - .in (in[7:0]), - .n (3)); // Templated + SelFlop selflop0 ( /*AUTOINST*/ + // Outputs + .out(out0), // Templated + // Inputs + .clk(clk), + .in(in[7:0]), + .n(0) + ); // Templated + SelFlop selflop1 ( /*AUTOINST*/ + // Outputs + .out(out1), // Templated + // Inputs + .clk(clk), + .in(in[7:0]), + .n(1) + ); // Templated + SelFlop selflop2 ( /*AUTOINST*/ + // Outputs + .out(out2), // Templated + // Inputs + .clk(clk), + .in(in[7:0]), + .n(2) + ); // Templated + SelFlop selflop3 ( /*AUTOINST*/ + // Outputs + .out(out3), // Templated + // Inputs + .clk(clk), + .in(in[7:0]), + .n(3) + ); // Templated - // Aggregate outputs into a single result vector - wire outo = out0|out1|out2|out3; - wire outa = out0&out1&out2&out3; - wire outx = out0^out1^out2^out3; - wire [63:0] result = {61'h0, outo, outa, outx}; + // Aggregate outputs into a single result vector + wire outo = out0 | out1 | out2 | out3; + wire outa = out0 & out1 & out2 & out3; + wire outx = out0 ^ out1 ^ out2 ^ out3; + wire [63:0] result = {61'h0, outo, outa, outx}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc < 90) begin - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h118c5809c7856d78 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h118c5809c7856d78 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module SelFlop(/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in, n - ); +module SelFlop ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in, + n +); - input clk; - input [7:0] in; - input [2:0] n; - output reg out; + input clk; + input [7:0] in; + input [2:0] n; + output reg out; - // verilator no_inline_module + // verilator no_inline_module - always @(posedge clk) begin - out <= in[n]; - end + always @(posedge clk) begin + out <= in[n]; + end endmodule diff --git a/test_regress/t/t_const_overflow_bad.out b/test_regress/t/t_const_overflow_bad.out index 1085a37de..db62260b2 100644 --- a/test_regress/t/t_const_overflow_bad.out +++ b/test_regress/t/t_const_overflow_bad.out @@ -1,17 +1,17 @@ -%Error: t/t_const_overflow_bad.v:9:34: Too many digits for 94 bit number: '94'd123456789012345678901234567890' - 9 | parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_const_overflow_bad.v:9:33: Too many digits for 94 bit number: '94'd123456789012345678901234567890' + 9 | parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_const_overflow_bad.v:11:31: Too many digits for 8 bit number: '8'habc' - 11 | parameter [200:0] SMALLH = 8'habc; - | ^~~~~~ -%Error: t/t_const_overflow_bad.v:12:31: Too many digits for 6 bit number: '6'o1234' - 12 | parameter [200:0] SMALLO = 6'o1234; - | ^~~~~~~ -%Error: t/t_const_overflow_bad.v:13:31: Too many digits for 3 bit number: '3'b1111' - 13 | parameter [200:0] SMALLB = 3'b1111; - | ^~~~~~~ -%Error: t/t_const_overflow_bad.v:19:35: Too many digits for 129 bit number: '129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d' - 19 | parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_const_overflow_bad.v:11:30: Too many digits for 8 bit number: '8'habc' + 11 | parameter [200:0] SMALLH = 8'habc; + | ^~~~~~ +%Error: t/t_const_overflow_bad.v:12:30: Too many digits for 6 bit number: '6'o1234' + 12 | parameter [200:0] SMALLO = 6'o1234; + | ^~~~~~~ +%Error: t/t_const_overflow_bad.v:13:30: Too many digits for 3 bit number: '3'b1111' + 13 | parameter [200:0] SMALLB = 3'b1111; + | ^~~~~~~ +%Error: t/t_const_overflow_bad.v:19:34: Too many digits for 129 bit number: '129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d' + 19 | parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_overflow_bad.v b/test_regress/t/t_const_overflow_bad.v index fd6301033..61b88ec86 100644 --- a/test_regress/t/t_const_overflow_bad.v +++ b/test_regress/t/t_const_overflow_bad.v @@ -6,16 +6,16 @@ module t; - parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; // One to many digits + parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; // One to many digits - parameter [200:0] SMALLH = 8'habc; // One to many digits - parameter [200:0] SMALLO = 6'o1234; // One to many digits - parameter [200:0] SMALLB = 3'b1111; // One to many digits + parameter [200:0] SMALLH = 8'habc; // One to many digits + parameter [200:0] SMALLO = 6'o1234; // One to many digits + parameter [200:0] SMALLB = 3'b1111; // One to many digits - // We'll allow this though; no reason to be cruel - parameter [200:0] OKH = 8'h000000001; + // We'll allow this though; no reason to be cruel + parameter [200:0] OKH = 8'h000000001; - // bug1380 - parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; + // bug1380 + parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; endmodule diff --git a/test_regress/t/t_const_sel_sel_extend.v b/test_regress/t/t_const_sel_sel_extend.v index 40304abc8..21a2ea115 100644 --- a/test_regress/t/t_const_sel_sel_extend.v +++ b/test_regress/t/t_const_sel_sel_extend.v @@ -4,19 +4,19 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 -module t( - output wire res +module t ( + output wire res ); - function automatic logic foo(logic bar); - foo = '0; - endfunction + function automatic logic foo(logic bar); + foo = '0; + endfunction - logic a, b; - logic [0:0][1:0] array; + logic a, b; + logic [0:0][1:0] array; - assign b = 0; - assign a = foo(b); - assign res = array[a][a]; + assign b = 0; + assign a = foo(b); + assign res = array[a][a]; endmodule diff --git a/test_regress/t/t_const_slicesel.v b/test_regress/t/t_const_slicesel.v index d77eb2696..8bcc4424b 100644 --- a/test_regress/t/t_const_slicesel.v +++ b/test_regress/t/t_const_slicesel.v @@ -6,15 +6,15 @@ module t; -localparam int unsigned A2 [1:0] = '{5,6}; -localparam int unsigned A3 [2:0] = '{4,5,6}; + localparam int unsigned A2[1:0] = '{5, 6}; + localparam int unsigned A3[2:0] = '{4, 5, 6}; -// Matching sizes with slicesel are okay. -localparam int unsigned B22 [1:0] = A2[1:0]; -localparam int unsigned B33 [2:0] = A3[2:0]; + // Matching sizes with slicesel are okay. + localparam int unsigned B22[1:0] = A2[1:0]; + localparam int unsigned B33[2:0] = A3[2:0]; -// See issue #3186 -localparam int unsigned B32_B [1:0] = A3[1:0]; -localparam int unsigned B32_T [1:0] = A3[2:1]; + // See issue #3186 + localparam int unsigned B32_B[1:0] = A3[1:0]; + localparam int unsigned B32_T[1:0] = A3[2:1]; endmodule diff --git a/test_regress/t/t_const_string_func.v b/test_regress/t/t_const_string_func.v index 275f37078..732b7f372 100644 --- a/test_regress/t/t_const_string_func.v +++ b/test_regress/t/t_const_string_func.v @@ -4,20 +4,19 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; - function automatic string foo_func(); - foo_func = "FOO"; - foo_func = $sformatf("%sBAR", foo_func); - for (int i = 0; i < 4; i++) - foo_func = $sformatf("%s%0d", foo_func, i); - endfunction + function automatic string foo_func(); + foo_func = "FOO"; + foo_func = $sformatf("%sBAR", foo_func); + for (int i = 0; i < 4; i++) foo_func = $sformatf("%s%0d", foo_func, i); + endfunction - localparam string the_foo = foo_func(); + localparam string the_foo = foo_func(); - initial begin - if (the_foo != "FOOBAR0123") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (the_foo != "FOOBAR0123") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_cls_arr_member.v b/test_regress/t/t_constraint_cls_arr_member.v index 87fac6d50..44bf40ee2 100644 --- a/test_regress/t/t_constraint_cls_arr_member.v +++ b/test_regress/t/t_constraint_cls_arr_member.v @@ -24,7 +24,7 @@ class container_a; rand item_t items[4]; constraint val_c { foreach (items[i]) { - items[i].value inside {[10:200]}; + items[i].value inside {[10 : 200]}; } } function new(); @@ -37,9 +37,7 @@ class container_b; rand item_t items[4]; constraint order_c { foreach (items[i]) { - if (i != 0) { - items[i].value > items[i-1].value; - } + if (i != 0) {items[i].value > items[i-1].value;} } } function new(); @@ -81,7 +79,7 @@ module t; for (int i = 1; i < 4; i++) begin if (cb.items[i].value <= cb.items[i-1].value) begin $write("%%Error: %s:%0d: ordering violated: items[%0d]=%0d <= items[%0d]=%0d\n", - `__FILE__, `__LINE__, i, cb.items[i].value, i-1, cb.items[i-1].value); + `__FILE__, `__LINE__, i, cb.items[i].value, i - 1, cb.items[i-1].value); `stop; end end @@ -92,7 +90,7 @@ module t; for (int i = 1; i < 4; i++) begin if (cc.items[i].value <= cc.items[i-1].value) begin $write("%%Error: %s:%0d: ordering violated: items[%0d]=%0d <= items[%0d]=%0d\n", - `__FILE__, `__LINE__, i, cc.items[i].value, i-1, cc.items[i-1].value); + `__FILE__, `__LINE__, i, cc.items[i].value, i - 1, cc.items[i-1].value); `stop; end end diff --git a/test_regress/t/t_cover_toggle_min.v b/test_regress/t/t_cover_toggle_min.v index be1abc641..c41c82dc4 100644 --- a/test_regress/t/t_cover_toggle_min.v +++ b/test_regress/t/t_cover_toggle_min.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t(); +module t; logic[1:0] a; logic[1:0] b; logic[1:0] c; diff --git a/test_regress/t/t_cover_trace_always.v b/test_regress/t/t_cover_trace_always.v index 89fe43625..74d4eaf13 100644 --- a/test_regress/t/t_cover_trace_always.v +++ b/test_regress/t/t_cover_trace_always.v @@ -14,7 +14,7 @@ module imply(input logic p, input logic q, output logic r); end endmodule -module t(); +module t; logic p; logic q; logic r; diff --git a/test_regress/t/t_covergroup_func_override_bad.v b/test_regress/t/t_covergroup_func_override_bad.v index ce1507536..2f758be96 100644 --- a/test_regress/t/t_covergroup_func_override_bad.v +++ b/test_regress/t/t_covergroup_func_override_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ -module t(); +module t; covergroup cg; function sample(); diff --git a/test_regress/t/t_covergroup_new_override_bad.v b/test_regress/t/t_covergroup_new_override_bad.v index 8a31bc11e..a38753936 100644 --- a/test_regress/t/t_covergroup_new_override_bad.v +++ b/test_regress/t/t_covergroup_new_override_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ -module t(); +module t; covergroup cg; function new(); diff --git a/test_regress/t/t_cuse_forward.v b/test_regress/t/t_cuse_forward.v index 98f1f4995..a94b8b584 100644 --- a/test_regress/t/t_cuse_forward.v +++ b/test_regress/t/t_cuse_forward.v @@ -7,17 +7,17 @@ class Baz; endclass -class Bar#(type T) extends T; +class Bar #( + type T +) extends T; endclass class Foo; - typedef struct { - int field; - } Zee; + typedef struct {int field;} Zee; task t1(); // Refer to Baz CLASSREFDTYPE node in implementation (via CLASSEXTENDS) - Bar#(Baz) b = new; + Bar #(Baz) b = new; endtask // Refer to the very same Baz CLASSREFDTYPE node again, this time within interface task t2(Bar#(Baz)::T b); @@ -29,7 +29,7 @@ class Moo; Foo::Zee z; endclass -module t(); +module t; initial begin // Use Moo in top module to add Moo to root, causing inclusion of Foo header into // root header. diff --git a/test_regress/t/t_dpi_binary.v b/test_regress/t/t_dpi_binary.v index 5f97ed49e..5349afbea 100644 --- a/test_regress/t/t_dpi_binary.v +++ b/test_regress/t/t_dpi_binary.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; initial begin // All Finished is in dpic_final diff --git a/test_regress/t/t_dpi_context.v b/test_regress/t/t_dpi_context.v index a23fa6abb..1b61b4b1e 100644 --- a/test_regress/t/t_dpi_context.v +++ b/test_regress/t/t_dpi_context.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; sub a (.inst(1)); sub b (.inst(2)); diff --git a/test_regress/t/t_dpi_display.v b/test_regress/t/t_dpi_display.v index 31bf4ad60..61caa63f7 100644 --- a/test_regress/t/t_dpi_display.v +++ b/test_regress/t/t_dpi_display.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; `ifndef VERILATOR `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." diff --git a/test_regress/t/t_dpi_display_bad.v b/test_regress/t/t_dpi_display_bad.v index 536da6df3..8e97f97f7 100644 --- a/test_regress/t/t_dpi_display_bad.v +++ b/test_regress/t/t_dpi_display_bad.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; `ifndef VERILATOR `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." diff --git a/test_regress/t/t_dpi_dup_bad.v b/test_regress/t/t_dpi_dup_bad.v index 493613856..358f00094 100644 --- a/test_regress/t/t_dpi_dup_bad.v +++ b/test_regress/t/t_dpi_dup_bad.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; // Same name w/ different args import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); diff --git a/test_regress/t/t_dpi_import_mix_bad.v b/test_regress/t/t_dpi_import_mix_bad.v index bb6fa043f..f00216a6e 100644 --- a/test_regress/t/t_dpi_import_mix_bad.v +++ b/test_regress/t/t_dpi_import_mix_bad.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; import "DPI-C" function int foo (int i); export "DPI-C" function foo; // Bad mix diff --git a/test_regress/t/t_dpi_name_bad.v b/test_regress/t/t_dpi_name_bad.v index 32cd549d2..a1b4838d5 100644 --- a/test_regress/t/t_dpi_name_bad.v +++ b/test_regress/t/t_dpi_name_bad.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; import "DPI-C" function int \badly.named (int i); diff --git a/test_regress/t/t_dpi_string.v b/test_regress/t/t_dpi_string.v index 6c9c6dddc..eb723c6b1 100644 --- a/test_regress/t/t_dpi_string.v +++ b/test_regress/t/t_dpi_string.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; import "DPI-C" function int dpii_string(input string DSM_NAME); diff --git a/test_regress/t/t_dpi_sys.v b/test_regress/t/t_dpi_sys.v index 1b0ab5082..232b94e6c 100644 --- a/test_regress/t/t_dpi_sys.v +++ b/test_regress/t/t_dpi_sys.v @@ -10,7 +10,7 @@ import "DPI-C" dpii_sys_task = function void \$dpii_sys (int i); import "DPI-C" dpii_sys_func = function int \$dpii_func (int i); -module t (); +module t; `ifndef verilator `error "Only Verilator supports PLI-ish DPI calls." diff --git a/test_regress/t/t_enum_bad_value.v b/test_regress/t/t_enum_bad_value.v index a9d71a590..b6b40906c 100644 --- a/test_regress/t/t_enum_bad_value.v +++ b/test_regress/t/t_enum_bad_value.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; enum bit signed [3:0] {OK1 = -1} ok1_t; // As is signed, loss of 1 bits is ok per IEEE enum bit signed [3:0] {OK2 = 3} ok2_t; diff --git a/test_regress/t/t_enum_const_methods.v b/test_regress/t/t_enum_const_methods.v index 0e4ed8596..d67975577 100644 --- a/test_regress/t/t_enum_const_methods.v +++ b/test_regress/t/t_enum_const_methods.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2022 Todd Strader // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; typedef enum [1:0] {E0, E1, E2} enm_t; diff --git a/test_regress/t/t_enum_name2.v b/test_regress/t/t_enum_name2.v index e99bd993f..de05825a5 100644 --- a/test_regress/t/t_enum_name2.v +++ b/test_regress/t/t_enum_name2.v @@ -13,7 +13,7 @@ package our_pkg; } T_Opcode; endpackage : our_pkg -module t (); +module t; our our (); endmodule diff --git a/test_regress/t/t_event_control_assign.v b/test_regress/t/t_event_control_assign.v index 1142d7eec..4d97ab5ba 100644 --- a/test_regress/t/t_event_control_assign.v +++ b/test_regress/t/t_event_control_assign.v @@ -8,7 +8,7 @@ int evt_recv_cnt; int new_evt_recv_cnt; -module t(); +module t; class Foo; event evt1; diff --git a/test_regress/t/t_event_control_pass.v b/test_regress/t/t_event_control_pass.v index 1426a817e..703c30fa8 100644 --- a/test_regress/t/t_event_control_pass.v +++ b/test_regress/t/t_event_control_pass.v @@ -24,7 +24,7 @@ endclass bit got_event; -module t(); +module t; initial begin Bar bar; diff --git a/test_regress/t/t_event_control_star.v b/test_regress/t/t_event_control_star.v index 9b2579c8f..c82ba653a 100644 --- a/test_regress/t/t_event_control_star.v +++ b/test_regress/t/t_event_control_star.v @@ -6,7 +6,7 @@ // Based on ivtest's nested_impl_event1.v by Martin Whitaker. -module t(); +module t; reg a; reg b; diff --git a/test_regress/t/t_final.v b/test_regress/t/t_final.v index 1a3156f4c..610061f1f 100644 --- a/test_regress/t/t_final.v +++ b/test_regress/t/t_final.v @@ -16,7 +16,7 @@ module submodule (); final ; // Empty test endmodule -module t (); +module t; generate for (genvar i = 0; i < 100; i = i + 1) begin : module_set submodule u_submodule(); diff --git a/test_regress/t/t_flag_fi.v b/test_regress/t/t_flag_fi.v index 28de5623e..8bcb12bc1 100644 --- a/test_regress/t/t_flag_fi.v +++ b/test_regress/t/t_flag_fi.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; initial begin $c("myfunction();"); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_flag_ldflags.v b/test_regress/t/t_flag_ldflags.v index ee945cb7a..b3b4a9907 100644 --- a/test_regress/t/t_flag_ldflags.v +++ b/test_regress/t/t_flag_ldflags.v @@ -10,7 +10,7 @@ import "DPI-C" pure function void dpii_a_library(); import "DPI-C" pure function void dpii_c_library(); import "DPI-C" pure function void dpii_so_library(); -module t (); +module t; initial begin dpii_a_library(); // From .a file dpii_c_library(); // From .cpp file diff --git a/test_regress/t/t_fork_block_item_declaration.v b/test_regress/t/t_fork_block_item_declaration.v index 79f996d63..c48501c1d 100644 --- a/test_regress/t/t_fork_block_item_declaration.v +++ b/test_regress/t/t_fork_block_item_declaration.v @@ -21,7 +21,7 @@ class Foo; endtask endclass -module t(); +module t; initial begin automatic int desired_counts[10] = '{10{1}}; counts = '{10{0}}; diff --git a/test_regress/t/t_fork_initial.v b/test_regress/t/t_fork_initial.v index 8bf3bee57..e274d7fed 100644 --- a/test_regress/t/t_fork_initial.v +++ b/test_regress/t/t_fork_initial.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; initial fork reg i; i = 1'b1; diff --git a/test_regress/t/t_fork_join_none_any_nested.v b/test_regress/t/t_fork_join_none_any_nested.v index 6a0f99875..2a7e7ac6c 100644 --- a/test_regress/t/t_fork_join_none_any_nested.v +++ b/test_regress/t/t_fork_join_none_any_nested.v @@ -25,7 +25,7 @@ class Foo; endtask endclass -module t(); +module t; reg a, b, c; initial begin diff --git a/test_regress/t/t_fork_join_none_class_cap.v b/test_regress/t/t_fork_join_none_class_cap.v index 49cd26392..aae0d6d6b 100644 --- a/test_regress/t/t_fork_join_none_class_cap.v +++ b/test_regress/t/t_fork_join_none_class_cap.v @@ -40,7 +40,7 @@ class Foo; endtask endclass -module t(); +module t; initial begin Foo foo; foo = new; diff --git a/test_regress/t/t_fork_join_none_virtual.v b/test_regress/t/t_fork_join_none_virtual.v index 6a0df7c6a..d67d5efe5 100644 --- a/test_regress/t/t_fork_join_none_virtual.v +++ b/test_regress/t/t_fork_join_none_virtual.v @@ -44,7 +44,7 @@ class Subfoo extends Foo; virtual task do_something();#5;endtask endclass -module t(); +module t; initial begin Subfoo subfoo; Foo foo; diff --git a/test_regress/t/t_fork_output_arg.v b/test_regress/t/t_fork_output_arg.v index 7c80d81d7..892b049f6 100644 --- a/test_regress/t/t_fork_output_arg.v +++ b/test_regress/t/t_fork_output_arg.v @@ -20,7 +20,7 @@ task automatic test; if (o != 100) $stop; endtask -module t(); +module t; initial begin test(); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_func_automatic_clear.v b/test_regress/t/t_func_automatic_clear.v index 512f8c529..1e1f41928 100644 --- a/test_regress/t/t_func_automatic_clear.v +++ b/test_regress/t/t_func_automatic_clear.v @@ -13,7 +13,7 @@ // Bug5747: Make sure that a variable with automatic storage is freshly // allocated when entering the function. -module t(); +module t; function automatic int ts_queue(); static int qs[$]; qs.push_back(0); diff --git a/test_regress/t/t_func_complex.v b/test_regress/t/t_func_complex.v index 0489cf568..561717d29 100644 --- a/test_regress/t/t_func_complex.v +++ b/test_regress/t/t_func_complex.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; typedef integer q_t[$]; function void queue_set(ref q_t q); diff --git a/test_regress/t/t_func_real_param.v b/test_regress/t/t_func_real_param.v index 21a95626b..60dcd09c6 100644 --- a/test_regress/t/t_func_real_param.v +++ b/test_regress/t/t_func_real_param.v @@ -6,7 +6,7 @@ // bug475 -module t(); +module t; function real get_real_one; input ignored; diff --git a/test_regress/t/t_func_refio_bad.v b/test_regress/t/t_func_refio_bad.v index a8eef79b2..b81984b26 100644 --- a/test_regress/t/t_func_refio_bad.v +++ b/test_regress/t/t_func_refio_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; typedef integer q_t[$]; function void queue_set(ref q_t q); diff --git a/test_regress/t/t_func_v.v b/test_regress/t/t_func_v.v index b7ab4cfb2..3b8f45236 100644 --- a/test_regress/t/t_func_v.v +++ b/test_regress/t/t_func_v.v @@ -6,7 +6,7 @@ // See bug569 -module t(); +module t; `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif diff --git a/test_regress/t/t_fuzz_triand_bad.v b/test_regress/t/t_fuzz_triand_bad.v index 648e830f1..6b63e35a5 100644 --- a/test_regress/t/t_fuzz_triand_bad.v +++ b/test_regress/t/t_fuzz_triand_bad.v @@ -4,6 +4,6 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; tri g=g.and.g; endmodule diff --git a/test_regress/t/t_gate_opt.v b/test_regress/t/t_gate_opt.v index aacdc2fd0..bdc237edc 100644 --- a/test_regress/t/t_gate_opt.v +++ b/test_regress/t/t_gate_opt.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 // bug5101 -module t (); +module t; logic [1:0] in0, in1, out; logic sel; diff --git a/test_regress/t/t_iface_self_ref_typedef.v b/test_regress/t/t_iface_self_ref_typedef.v index 298f795a1..9ff06e25d 100644 --- a/test_regress/t/t_iface_self_ref_typedef.v +++ b/test_regress/t/t_iface_self_ref_typedef.v @@ -7,12 +7,14 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // Self-referential typedef: typedef iface#(T) this_type inside interface iface -interface my_iface #(type T = logic); - typedef my_iface #(T) self_t; +interface my_iface #( + type T = logic +); + typedef my_iface#(T) self_t; T data; endinterface -module t (); +module t; my_iface #(logic [7:0]) if0 (); initial begin diff --git a/test_regress/t/t_iface_typedef_struct_member.v b/test_regress/t/t_iface_typedef_struct_member.v index 9c7fcb3c0..6a4d75a7b 100644 --- a/test_regress/t/t_iface_typedef_struct_member.v +++ b/test_regress/t/t_iface_typedef_struct_member.v @@ -28,7 +28,9 @@ endpackage // The struct-in-union pattern triggers MemberDType fixup (line 1056). // The $bits() usage in sub_mod forces widthing during V3Param, moving // template RefDTypes into the type table before the template dies. -interface types_if #(parameter cfg_pkg::cfg_t cfg = 0)(); +interface types_if #( + parameter cfg_pkg::cfg_t cfg = 0 +) (); typedef logic [$clog2(cfg.NumUnits)-1:0] idx_t; typedef struct packed { @@ -39,33 +41,35 @@ interface types_if #(parameter cfg_pkg::cfg_t cfg = 0)(); typedef struct packed { logic [3:0] cmd; union packed { - addr_t addr; // struct-in-union: MemberDType trigger + addr_t addr; // struct-in-union: MemberDType trigger logic [31:0] raw; } payload; } req_t; endinterface -module sub_mod #(parameter cfg_pkg::cfg_t cfg = 0)(); - types_if #(cfg) types(); - typedef types.idx_t idx_t; - typedef types.req_t req_t; +module sub_mod #( + parameter cfg_pkg::cfg_t cfg = 0 +) (); + types_if #(cfg) types (); + typedef types.idx_t idx_t; + typedef types.req_t req_t; typedef types.addr_t addr_t; localparam int ReqWidth = $bits(req_t); - idx_t s_idx; - req_t s_req; + idx_t s_idx; + req_t s_req; addr_t s_addr; endmodule module t; localparam cfg_pkg::cfg_t CFG = '{NumUnits: 5, LineSize: 32}; - types_if #(CFG) types(); + types_if #(CFG) types (); typedef types.req_t req_t; req_t top_req; - sub_mod #(.cfg(CFG)) sub(); + sub_mod #(.cfg(CFG)) sub (); initial begin #1; diff --git a/test_regress/t/t_iface_typedef_wrong_clone.v b/test_regress/t/t_iface_typedef_wrong_clone.v index 2b79650b3..ce2fbd552 100644 --- a/test_regress/t/t_iface_typedef_wrong_clone.v +++ b/test_regress/t/t_iface_typedef_wrong_clone.v @@ -26,7 +26,9 @@ typedef struct packed { } sc_cfg_t; // Inner types interface - parameterized with struct typedef -interface sc_types_if #(parameter sc_cfg_t cfg = 0)(); +interface sc_types_if #( + parameter sc_cfg_t cfg = 0 +) (); typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.DataBits-1:0] data_t; @@ -37,25 +39,29 @@ interface sc_types_if #(parameter sc_cfg_t cfg = 0)(); endinterface // Cache interface - wraps types interface and re-exports typedefs -interface sc_if #(parameter sc_cfg_t cfg = 0)(); - sc_types_if #(cfg) sc_io(); +interface sc_if #( + parameter sc_cfg_t cfg = 0 +) (); + sc_types_if #(cfg) sc_io (); typedef sc_io.addr_t addr_t; typedef sc_io.data_t data_t; - typedef sc_io.pkt_t pkt_t; + typedef sc_io.pkt_t pkt_t; addr_t rq_addr_i; endinterface // Wrapper module that uses the cache interface -module sc_wrap #(parameter sc_cfg_t cfg = 0)(); - sc_if #(cfg) cache(); +module sc_wrap #( + parameter sc_cfg_t cfg = 0 +) (); + sc_if #(cfg) cache (); typedef cache.addr_t addr_t; - typedef cache.pkt_t pkt_t; + typedef cache.pkt_t pkt_t; addr_t local_addr; - pkt_t local_pkt; + pkt_t local_pkt; assign cache.rq_addr_i = local_addr; endmodule @@ -64,10 +70,10 @@ endmodule // This creates two clones of sc_if (and sc_types_if) with different params module t; localparam sc_cfg_t cfg_narrow = '{AddrBits: 16, DataBits: 32}; - localparam sc_cfg_t cfg_wide = '{AddrBits: 32, DataBits: 64}; + localparam sc_cfg_t cfg_wide = '{AddrBits: 32, DataBits: 64}; - sc_wrap #(.cfg(cfg_narrow)) narrow(); - sc_wrap #(.cfg(cfg_wide)) wide(); + sc_wrap #(.cfg(cfg_narrow)) narrow (); + sc_wrap #(.cfg(cfg_wide)) wide (); initial begin #1; diff --git a/test_regress/t/t_initial_delay_assign.v b/test_regress/t/t_initial_delay_assign.v index a5eaec7e6..5219cfb1d 100644 --- a/test_regress/t/t_initial_delay_assign.v +++ b/test_regress/t/t_initial_delay_assign.v @@ -23,7 +23,7 @@ end \ -module t (); +module t; reg foo1; wire bar1; initial foo1 = '0; diff --git a/test_regress/t/t_inside_nonint.v b/test_regress/t/t_inside_nonint.v index b37e7675a..eb9429883 100644 --- a/test_regress/t/t_inside_nonint.v +++ b/test_regress/t/t_inside_nonint.v @@ -16,7 +16,7 @@ function bit check_double(real d); return 1'b0; endfunction -module t(); +module t; initial begin if (!check_string("WO")) $stop; diff --git a/test_regress/t/t_interface_ar2a.v b/test_regress/t/t_interface_ar2a.v index e2102953b..8e2142d3f 100644 --- a/test_regress/t/t_interface_ar2a.v +++ b/test_regress/t/t_interface_ar2a.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2020 Thierry Tambe // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; ahb_slave_intf AHB_S[1](); diff --git a/test_regress/t/t_interface_ar2b.v b/test_regress/t/t_interface_ar2b.v index 6e8766ff9..f715e7a47 100644 --- a/test_regress/t/t_interface_ar2b.v +++ b/test_regress/t/t_interface_ar2b.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2020 Thierry Tambe // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; sub sub [1] (); diff --git a/test_regress/t/t_interface_array_nocolon.v b/test_regress/t/t_interface_array_nocolon.v index 5ef95ea2b..cce609d06 100644 --- a/test_regress/t/t_interface_array_nocolon.v +++ b/test_regress/t/t_interface_array_nocolon.v @@ -16,7 +16,7 @@ module foo_subm ); endmodule -module t (); +module t; localparam N = 3; diff --git a/test_regress/t/t_interface_array_nocolon_bad.v b/test_regress/t/t_interface_array_nocolon_bad.v index 79c6c570d..b88110bfe 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.v +++ b/test_regress/t/t_interface_array_nocolon_bad.v @@ -16,7 +16,7 @@ module foo_subm ); endmodule -module t (); +module t; localparam N = 3; diff --git a/test_regress/t/t_interface_gen10.v b/test_regress/t/t_interface_gen10.v index 0e00daee2..d3f31b60b 100644 --- a/test_regress/t/t_interface_gen10.v +++ b/test_regress/t/t_interface_gen10.v @@ -19,7 +19,7 @@ module t1(intf mod_intf); end endmodule -module t(); +module t; generate begin : TestIf intf #(.PARAM(1)) my_intf [0:0] (); diff --git a/test_regress/t/t_interface_gen11.v b/test_regress/t/t_interface_gen11.v index 6ae54e8da..0fc617cde 100644 --- a/test_regress/t/t_interface_gen11.v +++ b/test_regress/t/t_interface_gen11.v @@ -27,7 +27,7 @@ module t2(intf mod_intfs [1:0]); endgenerate endmodule -module t(); +module t; intf #(.PARAM(1)) my_intf [1:0] (); diff --git a/test_regress/t/t_interface_gen5.v b/test_regress/t/t_interface_gen5.v index db58f6764..ca54aaf56 100644 --- a/test_regress/t/t_interface_gen5.v +++ b/test_regress/t/t_interface_gen5.v @@ -19,7 +19,7 @@ module t1(intf mod_intf); end endmodule -module t(); +module t; generate begin : TestIf intf #(.PARAM(1)) my_intf (); diff --git a/test_regress/t/t_interface_gen6.v b/test_regress/t/t_interface_gen6.v index b3a9e5620..18858412d 100644 --- a/test_regress/t/t_interface_gen6.v +++ b/test_regress/t/t_interface_gen6.v @@ -12,7 +12,7 @@ interface intf logic val; endinterface -module t(); +module t; generate if (1) begin diff --git a/test_regress/t/t_interface_gen7.v b/test_regress/t/t_interface_gen7.v index fb457286e..a9dfb6e8a 100644 --- a/test_regress/t/t_interface_gen7.v +++ b/test_regress/t/t_interface_gen7.v @@ -21,7 +21,7 @@ module t1(intf mod_intf); end endmodule -module t(); +module t; intf #(.PARAM(1)) my_intf [1:0] (); diff --git a/test_regress/t/t_interface_gen8.v b/test_regress/t/t_interface_gen8.v index f3f464fbd..1de7133b9 100644 --- a/test_regress/t/t_interface_gen8.v +++ b/test_regress/t/t_interface_gen8.v @@ -19,7 +19,7 @@ module t1(intf mod_intf); end endmodule -module t(); +module t; //intf #(.PARAM(1)) my_intf [1:0] (); intf #(.PARAM(1)) my_intf (); diff --git a/test_regress/t/t_interface_gen9.v b/test_regress/t/t_interface_gen9.v index 4f8d6bd59..a329dba5f 100644 --- a/test_regress/t/t_interface_gen9.v +++ b/test_regress/t/t_interface_gen9.v @@ -12,7 +12,7 @@ module t1(input logic foo); end endmodule -module t(); +module t; logic [1:0] my_foo; diff --git a/test_regress/t/t_interface_localparam.v b/test_regress/t/t_interface_localparam.v index 5957fc49c..a753aa752 100644 --- a/test_regress/t/t_interface_localparam.v +++ b/test_regress/t/t_interface_localparam.v @@ -46,7 +46,7 @@ module Core( end endmodule -module t(); +module t; SimpleIntf intf(); diff --git a/test_regress/t/t_interface_mp_func.v b/test_regress/t/t_interface_mp_func.v index be8089001..fe12a85c8 100644 --- a/test_regress/t/t_interface_mp_func.v +++ b/test_regress/t/t_interface_mp_func.v @@ -18,7 +18,7 @@ interface pads_if(); endtask endinterface -module t(); +module t; pads_if padsif[1:0](); pads_if padsif_arr[1:0](); initial begin diff --git a/test_regress/t/t_interface_nested_struct_param.v b/test_regress/t/t_interface_nested_struct_param.v index a4932167b..76491f549 100644 --- a/test_regress/t/t_interface_nested_struct_param.v +++ b/test_regress/t/t_interface_nested_struct_param.v @@ -33,24 +33,24 @@ endpackage // Nested types interface: derives struct typedef from computed localparams interface types_if #( - parameter cfg_pkg::cfg_t cfg = '0 -)(); + parameter cfg_pkg::cfg_t cfg = '0 +) (); // Computed localparams - these use division and $clog2 of cfg fields. // With default cfg='0, these produce X/undefined values. - localparam int NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int NUM_LINES = cfg.Capacity / cfg.LineSize; localparam int LINES_PER_WAY = NUM_LINES / cfg.Associativity; - localparam int BLOCK_BITS = $clog2(cfg.LineSize); - localparam int ROW_BITS = $clog2(LINES_PER_WAY); - localparam int TAG_BITS = cfg.AddrBits - ROW_BITS - BLOCK_BITS; + localparam int BLOCK_BITS = $clog2(cfg.LineSize); + localparam int ROW_BITS = $clog2(LINES_PER_WAY); + localparam int TAG_BITS = cfg.AddrBits - ROW_BITS - BLOCK_BITS; typedef logic [TAG_BITS-1:0] tag_t; typedef logic [ROW_BITS-1:0] row_t; typedef logic [BLOCK_BITS-1:0] block_t; typedef struct packed { - logic vld; - tag_t tag; - row_t row; + logic vld; + tag_t tag; + row_t row; block_t block; } entry_t; endinterface @@ -58,28 +58,28 @@ endinterface // Wrapper interface: instantiates types_if as a nested cell // (mirrors simple_cache_if which instantiates simple_cache_types_if) interface wrapper_if #( - parameter cfg_pkg::cfg_t cfg = '0 -)(); - types_if #(cfg) types(); + parameter cfg_pkg::cfg_t cfg = '0 +) (); + types_if #(cfg) types (); - typedef types.tag_t tag_t; + typedef types.tag_t tag_t; - logic req_vld; - tag_t req_tag; + logic req_vld; + tag_t req_tag; endinterface // Sub-module parameterized by entry width // (mirrors flop_nr / sram_generic_1r1w parameterized by $bits(sc_tag_t)) module entry_store #( - parameter int ENTRY_WIDTH = 8, - parameter int DEPTH = 4 -)( - input logic clk, - input logic wr_en, - input logic [ENTRY_WIDTH-1:0] wr_data, - output logic [ENTRY_WIDTH-1:0] rd_data + parameter int ENTRY_WIDTH = 8, + parameter int DEPTH = 4 +) ( + input logic clk, + input logic wr_en, + input logic [ENTRY_WIDTH-1:0] wr_data, + output logic [ENTRY_WIDTH-1:0] rd_data ); - logic [ENTRY_WIDTH-1:0] mem [DEPTH]; + logic [ENTRY_WIDTH-1:0] mem[DEPTH]; always_ff @(posedge clk) begin if (wr_en) mem[0] <= wr_data; end @@ -91,14 +91,14 @@ endmodule // (mirrors simple_cache which receives simple_cache_if, instantiates // simple_cache_types_if, and uses types.sc_tag_t) module inner_mod #( - parameter cfg_pkg::cfg_t cfg = '0 -)( - input logic clk, - wrapper_if io + parameter cfg_pkg::cfg_t cfg = '0 +) ( + input logic clk, + wrapper_if io ); // Local instantiation of types_if - same cfg, so gets same clone // as the one inside wrapper_if via "De-parameterize to prev" - types_if #(cfg) types(); + types_if #(cfg) types (); typedef types.entry_t entry_t; typedef types.tag_t tag_t; @@ -106,37 +106,37 @@ module inner_mod #( entry_t wr_entry; entry_t rd_entry; - assign wr_entry.vld = io.req_vld; - assign wr_entry.tag = io.req_tag; - assign wr_entry.row = '0; + assign wr_entry.vld = io.req_vld; + assign wr_entry.tag = io.req_tag; + assign wr_entry.row = '0; assign wr_entry.block = '0; // Use $bits of the struct typedef as a value parameter to sub-module. // This is the critical pattern: $bits(entry_t) must resolve using the // clone's struct (correct width), not the template's (zero/X width). entry_store #( - .ENTRY_WIDTH($bits(entry_t)), - .DEPTH(8) + .ENTRY_WIDTH($bits(entry_t)), + .DEPTH(8) ) u_store ( - .clk(clk), - .wr_en(io.req_vld), - .wr_data(wr_entry), - .rd_data(rd_entry) + .clk(clk), + .wr_en(io.req_vld), + .wr_data(wr_entry), + .rd_data(rd_entry) ); endmodule // Outer wrapper module: instantiates wrapper_if and inner_mod // (mirrors mblit_simple_cache_wrap) module outer_mod #( - parameter cfg_pkg::cfg_t cfg = '0 -)( - input logic clk + parameter cfg_pkg::cfg_t cfg = '0 +) ( + input logic clk ); - wrapper_if #(cfg) wif(); + wrapper_if #(cfg) wif (); inner_mod #(cfg) u_inner ( - .clk(clk), - .io(wif) + .clk(clk), + .io(wif) ); endmodule @@ -155,10 +155,10 @@ module t; // TAG_BITS = 64 - 3 - 6 = 55 // entry_t = 1 + 55 + 3 + 6 = 65 bits localparam cfg_pkg::cfg_t MY_CFG = '{ - AddrBits: 64, - Capacity: 1024, - LineSize: 64, - Associativity: 2 + AddrBits: 64, + Capacity: 1024, + LineSize: 64, + Associativity: 2 }; outer_mod #(.cfg(MY_CFG)) u_outer (.clk(clk)); @@ -172,8 +172,7 @@ module t; if (cyc > 5) begin // Verify the struct round-trips correctly if (u_outer.u_inner.rd_entry.vld !== 1'b1 && cyc > 10) begin - $display("FAIL cyc=%0d: rd_entry.vld=%b expected 1", - cyc, u_outer.u_inner.rd_entry.vld); + $display("FAIL cyc=%0d: rd_entry.vld=%b expected 1", cyc, u_outer.u_inner.rd_entry.vld); $stop; end end diff --git a/test_regress/t/t_interface_param_another_bad.v b/test_regress/t/t_interface_param_another_bad.v index 25e66288e..fb3b9eb5a 100644 --- a/test_regress/t/t_interface_param_another_bad.v +++ b/test_regress/t/t_interface_param_another_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2017 Johan Bjork // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; simple_bus sb_intf (); simple_bus #(.PARAMETER(sb_intf.dummy)) simple (); initial begin diff --git a/test_regress/t/t_jumps_uninit_destructor_call.v b/test_regress/t/t_jumps_uninit_destructor_call.v index ddcdce134..717f660ff 100644 --- a/test_regress/t/t_jumps_uninit_destructor_call.v +++ b/test_regress/t/t_jumps_uninit_destructor_call.v @@ -26,14 +26,14 @@ class Foo; // without having it initialized first. endtask task automatic return_before_select(bit b, int idx); - if (b) return; // goto + if (b) return; // goto // This will create two temporary strings used to select from `arrb` and assign to it. arrb[arra[idx]] = #10 "yah!"; // jump here endtask endclass -module t(); +module t; initial begin Foo foo; foo = new; diff --git a/test_regress/t/t_lint_const_func_dpi_bad.v b/test_regress/t/t_lint_const_func_dpi_bad.v index 6647afd4b..538f63ad4 100644 --- a/test_regress/t/t_lint_const_func_dpi_bad.v +++ b/test_regress/t/t_lint_const_func_dpi_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2021 Donald Owen // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; import "DPI-C" function int dpiFunc(); localparam PARAM = dpiFunc(); endmodule diff --git a/test_regress/t/t_lint_const_func_gen_bad.v b/test_regress/t/t_lint_const_func_gen_bad.v index 95dd6abe0..12013395b 100644 --- a/test_regress/t/t_lint_const_func_gen_bad.v +++ b/test_regress/t/t_lint_const_func_gen_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2021 Donald Owen // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; if (1) begin: GenConstFunc // IEEE 1800-2023 13.4.3, constant functions shall not be declared inside a //generate block diff --git a/test_regress/t/t_lint_infinite_bad.v b/test_regress/t/t_lint_infinite_bad.v index 8e11c11f4..0b74bcef1 100644 --- a/test_regress/t/t_lint_infinite_bad.v +++ b/test_regress/t/t_lint_infinite_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; initial begin forever begin end diff --git a/test_regress/t/t_lint_once_bad.v b/test_regress/t/t_lint_once_bad.v index a148e5510..22ba2bd3f 100644 --- a/test_regress/t/t_lint_once_bad.v +++ b/test_regress/t/t_lint_once_bad.v @@ -7,7 +7,7 @@ // Check that we report warnings only once on parameterized modules // Also check that we don't suppress warnings on the same line -module t (); +module t; sub #(.A(1)) sub1(); sub #(.A(2)) sub2(); sub #(.A(3)) sub3(); diff --git a/test_regress/t/t_lint_only.v b/test_regress/t/t_lint_only.v index e0ab4d0df..1921847c3 100644 --- a/test_regress/t/t_lint_only.v +++ b/test_regress/t/t_lint_only.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; initial begin $stop; end diff --git a/test_regress/t/t_lint_repeat_bad.v b/test_regress/t/t_lint_repeat_bad.v index 747c3b6b0..5f9f79e86 100644 --- a/test_regress/t/t_lint_repeat_bad.v +++ b/test_regress/t/t_lint_repeat_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; sub #(.Z(0)) sub1 (); sub #(.Z(1)) sub2 (); diff --git a/test_regress/t/t_lint_restore_bad.v b/test_regress/t/t_lint_restore_bad.v index 8566a9650..dadf0e143 100644 --- a/test_regress/t/t_lint_restore_bad.v +++ b/test_regress/t/t_lint_restore_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; reg [3:0] four; reg [4:0] five; diff --git a/test_regress/t/t_lint_restore_prag_bad.v b/test_regress/t/t_lint_restore_prag_bad.v index 71a05c912..c66468779 100644 --- a/test_regress/t/t_lint_restore_prag_bad.v +++ b/test_regress/t/t_lint_restore_prag_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; // No matching save // verilator lint_restore diff --git a/test_regress/t/t_lint_subout_bad.v b/test_regress/t/t_lint_subout_bad.v index 52f2da80a..df2d7ec7c 100644 --- a/test_regress/t/t_lint_subout_bad.v +++ b/test_regress/t/t_lint_subout_bad.v @@ -6,7 +6,7 @@ // verilator lint_off UNDRIVEN -module t(); +module t; wire sig; sub sub0(.out(33'b0)); sub sub1(.out({32'b0, sig})); diff --git a/test_regress/t/t_lint_width.v b/test_regress/t/t_lint_width.v index ff2c55d58..707f06911 100644 --- a/test_regress/t/t_lint_width.v +++ b/test_regress/t/t_lint_width.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; // This isn't a width violation, as +/- 1'b1 is a common idiom // that's fairly harmless diff --git a/test_regress/t/t_lint_width_bad.v b/test_regress/t/t_lint_width_bad.v index 9c004f754..b2c4db6c6 100644 --- a/test_regress/t/t_lint_width_bad.v +++ b/test_regress/t/t_lint_width_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; // See also t_math_width diff --git a/test_regress/t/t_lparam_assign_iface_const.v b/test_regress/t/t_lparam_assign_iface_const.v index 9237520e4..140051d89 100644 --- a/test_regress/t/t_lparam_assign_iface_const.v +++ b/test_regress/t/t_lparam_assign_iface_const.v @@ -5,32 +5,31 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 typedef struct { - int BAR_INT; - bit BAR_BIT; - byte BAR_ARRAY [0:3]; + int BAR_INT; + bit BAR_BIT; + byte BAR_ARRAY[0:3]; } foo_t; -interface intf - #(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}}) - (); +interface intf #( + parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}} +) (); endinterface -module sub (intf the_intf_port [4]); - localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; +module sub ( + intf the_intf_port[4] +); + localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; initial begin #1; - if (intf_foo_bar_int != 4) $stop; + if (intf_foo_bar_int != 4) $stop; end endmodule -module t (); - intf the_intf [4] (); +module t; + intf the_intf[4] (); - sub - the_sub ( - .the_intf_port (the_intf) - ); + sub the_sub (.the_intf_port(the_intf)); initial begin #2; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_bad.v b/test_regress/t/t_lparam_assign_iface_typedef_bad.v index 2a030945b..806f6f2a2 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_bad.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_bad.v @@ -8,20 +8,20 @@ // Correct syntax is: localparam type p0_rq_t = if0.rq_t; interface x_if #( - parameter int p_awidth = 4, - parameter int p_dwidth = 7 -)(); + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); typedef struct packed { logic [p_awidth-1:0] addr; logic [p_dwidth-1:0] data; } rq_t; endinterface -module t(); +module t; x_if #( - .p_awidth(16), - .p_dwidth(8) - ) if0(); + .p_awidth(16), + .p_dwidth(8) + ) if0 (); localparam p0_rq_t = if0.rq_t; // Bad: missing 'type' keyword diff --git a/test_regress/t/t_lparam_dep_iface0.v b/test_regress/t/t_lparam_dep_iface0.v index 54abb8d2e..842ec3e84 100644 --- a/test_regress/t/t_lparam_dep_iface0.v +++ b/test_regress/t/t_lparam_dep_iface0.v @@ -12,18 +12,20 @@ // verilog_format: on typedef struct { - int BAR_INT; - bit BAR_BIT; - byte BAR_ARRAY [0:3]; + int BAR_INT; + bit BAR_BIT; + byte BAR_ARRAY[0:3]; } foo_t; -interface intf - #(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}}) - (); +interface intf #( + parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}} +) (); endinterface -module sub (intf single_intf_port); - localparam byte single_foo_bar_byte = single_intf_port.FOO.BAR_ARRAY[3]; +module sub ( + intf single_intf_port +); + localparam byte single_foo_bar_byte = single_intf_port.FOO.BAR_ARRAY[3]; initial begin #1; @@ -31,13 +33,10 @@ module sub (intf single_intf_port); end endmodule -module t (); +module t; intf single_intf (); - sub - the_sub ( - .single_intf_port(single_intf) - ); + sub the_sub (.single_intf_port(single_intf)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface1.v b/test_regress/t/t_lparam_dep_iface1.v index c9029fc01..43d9254b6 100644 --- a/test_regress/t/t_lparam_dep_iface1.v +++ b/test_regress/t/t_lparam_dep_iface1.v @@ -12,18 +12,20 @@ // verilog_format: on typedef struct { - int BAR_INT; - bit BAR_BIT; - byte BAR_ARRAY [0:3]; + int BAR_INT; + bit BAR_BIT; + byte BAR_ARRAY[0:3]; } foo_t; -interface intf - #(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}}) - (); +interface intf #( + parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}} +) (); endinterface -module sub (intf the_intf_port [4]); - localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; +module sub ( + intf the_intf_port[4] +); + localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; initial begin #1; @@ -31,13 +33,10 @@ module sub (intf the_intf_port [4]); end endmodule -module t (); - intf the_intf [4] (); +module t; + intf the_intf[4] (); - sub - the_sub ( - .the_intf_port (the_intf) - ); + sub the_sub (.the_intf_port(the_intf)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface10.v b/test_regress/t/t_lparam_dep_iface10.v index 0e34e4793..7fbfb5672 100644 --- a/test_regress/t/t_lparam_dep_iface10.v +++ b/test_regress/t/t_lparam_dep_iface10.v @@ -19,24 +19,26 @@ package scp; endpackage interface a_if #( - parameter a_p = 0 -)(); + parameter a_p = 0 +) (); localparam int LP0 = a_p * 2; typedef logic [LP0-1:0] a_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); localparam int LP_MUL = cfg.ABits * cfg.BBits; localparam int LP_ADD = cfg.ABits + cfg.BBits; - a_if #(LP_MUL) types_mul(); - a_if #(LP_ADD) types_add(); + a_if #(LP_MUL) types_mul (); + a_if #(LP_ADD) types_add (); endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.types_mul.a_t a_mul_t; @@ -52,17 +54,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface11.v b/test_regress/t/t_lparam_dep_iface11.v index 6ed0ccd3c..eee64ae45 100644 --- a/test_regress/t/t_lparam_dep_iface11.v +++ b/test_regress/t/t_lparam_dep_iface11.v @@ -19,33 +19,35 @@ package scp; endpackage interface a_if #( - parameter a_p = 0 -)(); + parameter a_p = 0 +) (); localparam int LP0 = a_p * 2; typedef logic [LP0-1:0] a_t; endinterface interface b_if #( - parameter b_p = 0 -)(); + parameter b_p = 0 +) (); localparam int LP0 = b_p + 3; typedef logic [LP0-1:0] b_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_inst(); - b_if #(LP0) b_inst(); + a_if #(LP0) a_inst (); + b_if #(LP0) b_inst (); typedef a_inst.a_t a_t; typedef b_inst.b_t b_t; endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.a_t a_t; @@ -61,17 +63,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface12.v b/test_regress/t/t_lparam_dep_iface12.v index e462e4cca..d8f8421e1 100644 --- a/test_regress/t/t_lparam_dep_iface12.v +++ b/test_regress/t/t_lparam_dep_iface12.v @@ -20,40 +20,42 @@ endpackage // Level 4: innermost interface interface d_if #( - parameter d_p = 0 -)(); + parameter d_p = 0 +) (); localparam int LP0 = d_p + 1; typedef logic [LP0-1:0] d_t; endinterface // Level 3 interface c_if #( - parameter c_p = 0 -)(); + parameter c_p = 0 +) (); localparam int LP0 = c_p * 2; - d_if #(LP0) d_inst(); + d_if #(LP0) d_inst (); typedef d_inst.d_t c_t; endinterface // Level 2 interface b_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - c_if #(LP0) c_inst(); + c_if #(LP0) c_inst (); typedef c_inst.c_t b_t; endinterface // Level 1: outermost interface interface a_if #( - parameter scp::cfg_t cfg = 0 -)(); - b_if #(cfg) b_inst(); + parameter scp::cfg_t cfg = 0 +) (); + b_if #(cfg) b_inst (); typedef b_inst.b_t a_t; endinterface -module m #(parameter scp::cfg_t cfg=0) ( - a_if io +module m #( + parameter scp::cfg_t cfg = 0 +) ( + a_if io ); typedef io.a_t a_t; @@ -69,17 +71,12 @@ module m #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t cfg = '{ABits : 2, BBits : 3}; a_if #(cfg) a_io (); - m #(cfg) m_inst( - .io(a_io) - ); + m #(cfg) m_inst (.io(a_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface13.v b/test_regress/t/t_lparam_dep_iface13.v index 4feff82f7..1b5ac1d7f 100644 --- a/test_regress/t/t_lparam_dep_iface13.v +++ b/test_regress/t/t_lparam_dep_iface13.v @@ -29,37 +29,39 @@ package sc; endpackage interface simple_cache_types_if #( - parameter sc::cfg_t cfg = 0 -)(); + parameter sc::cfg_t cfg = 0 +) (); - localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; - localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; - localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); - localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); - localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; - localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; - localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; + localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; endinterface interface simple_cache_if #( - parameter sc::cfg_t cfg = 0 -)(); - simple_cache_types_if #(cfg) types(); + parameter sc::cfg_t cfg = 0 +) (); + simple_cache_types_if #(cfg) types (); endinterface -module simple_cache #(parameter sc::cfg_t cfg=0) ( - simple_cache_if io +module simple_cache #( + parameter sc::cfg_t cfg = 0 +) ( + simple_cache_if io ); localparam num_rld_beats = cfg.LineSize / cfg.RefillWidth; localparam num_arrays = cfg.FgWidth / cfg.RefillWidth; - localparam dat_array_width = cfg.RefillWidth*8; - localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE; - localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; - localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY; - localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS; + localparam dat_array_width = cfg.RefillWidth * 8; + localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE; + localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; + localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY; + localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS; initial begin #1; @@ -75,28 +77,26 @@ module simple_cache #(parameter sc::cfg_t cfg=0) ( endmodule -module t(); +module t; localparam sc::cfg_t sc_cfg = '{ - CmdTagBits : $clog2(6), - Associativity : 2, - Capacity : 1024, - LineSize : 64, - StateBits : 2, - AddrBits : 64, - MissQSize : 2, + CmdTagBits : $clog2(6), + Associativity : 2, + Capacity : 1024, + LineSize : 64, + StateBits : 2, + AddrBits : 64, + MissQSize : 2, - FgWidth : 16, - RefillWidth : 8 + FgWidth : 16, + RefillWidth : 8 }; simple_cache_if #(sc_cfg) sc_io (); - simple_cache #(sc_cfg) simple_cache( - .io(sc_io) - ); + simple_cache #(sc_cfg) simple_cache (.io(sc_io)); - localparam int SC_DROWS_PER_LINE = sc_io.types.SC_DROWS_PER_LINE; + localparam int SC_DROWS_PER_LINE = sc_io.types.SC_DROWS_PER_LINE; initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface14.v b/test_regress/t/t_lparam_dep_iface14.v index 04ac60423..c14a92a87 100644 --- a/test_regress/t/t_lparam_dep_iface14.v +++ b/test_regress/t/t_lparam_dep_iface14.v @@ -15,18 +15,22 @@ // verilog_format: on typedef struct packed { - int unsigned ABits; - int unsigned BBits; + int unsigned ABits; + int unsigned BBits; } scp_cfg_t; -interface a_if #(parameter a_p = 0)(); +interface a_if #( + parameter a_p = 0 +) (); localparam int LP0 = a_p * 2; typedef logic [LP0-1:0] a_t; endinterface -interface sct_if #(parameter scp_cfg_t cfg = 0)(); +interface sct_if #( + parameter scp_cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_if0(); + a_if #(LP0) a_if0 (); typedef a_if0.a_t a_t; // Captured typedef from nested interface endinterface @@ -34,39 +38,43 @@ interface intf #( parameter type data_t = bit, parameter int arr[2][4] ) (); - data_t data; - logic [$bits(data)-1:0] other_data; + data_t data; + logic [$bits(data)-1:0] other_data; endinterface module sub #( parameter int width, parameter int arr[2][4] ) (); - typedef struct packed { - logic [3:3] [0:0] [width-1:0] field; - } user_type_t; + typedef struct packed {logic [3:3][0:0][width-1:0] field;} user_type_t; - // This has a PIN that assigns data_t - intf #( - .data_t(user_type_t), - .arr(arr) - ) the_intf (); + // This has a PIN that assigns data_t + intf #( + .data_t(user_type_t), + .arr(arr) + ) the_intf (); - logic [width-1:0] signal; + logic [width-1:0] signal; - always_comb begin - the_intf.data.field = signal; - the_intf.other_data = signal; - end + always_comb begin + the_intf.data.field = signal; + the_intf.other_data = signal; + end endmodule -module t (); +module t; localparam scp_cfg_t sc_cfg = '{ABits: 2, BBits: 3}; sct_if #(sc_cfg) types (); - sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); - sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); + sub #( + .width(8), + .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub8 (); + sub #( + .width(16), + .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub16 (); typedef types.a_if0.a_t a_t; typedef types.a_t a2_t; @@ -75,7 +83,7 @@ module t (); #1; `checkd(12, $bits(a_t)); `checkd(12, $bits(a2_t)); - `checkd(8, $bits(sub8.the_intf.data)); + `checkd(8, $bits(sub8.the_intf.data)); `checkd(16, $bits(sub16.the_intf.data)); #1; diff --git a/test_regress/t/t_lparam_dep_iface15.v b/test_regress/t/t_lparam_dep_iface15.v index 2af8515ac..c48ac66fb 100644 --- a/test_regress/t/t_lparam_dep_iface15.v +++ b/test_regress/t/t_lparam_dep_iface15.v @@ -19,41 +19,45 @@ typedef struct packed { int unsigned BBits; } scp_cfg_t; -interface a_if #(parameter a_p = 0)(); +interface a_if #( + parameter a_p = 0 +) (); localparam int LP0 = a_p; typedef logic [LP0-1:0] a_t; endinterface -interface sct_if #(parameter scp_cfg_t cfg = 0)(); +interface sct_if #( + parameter scp_cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_if0(); + a_if #(LP0) a_if0 (); typedef a_if0.a_t a_t; endinterface -interface sc_if #(parameter scp_cfg_t cfg = 0)(); - sct_if #(cfg) types(); +interface sc_if #( + parameter scp_cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); typedef types.a_t a_t; endinterface interface intf #( - parameter type data_t = bit, - parameter int arr[2][4] + parameter type data_t = bit, + parameter int arr[2][4] ) (); data_t data; logic [$bits(data)-1:0] other_data; endinterface module sub #( - parameter int width, - parameter int arr[2][4] + parameter int width, + parameter int arr[2][4] ) (); - typedef struct packed { - logic [3:3] [0:0] [width-1:0] field; - } user_type_t; + typedef struct packed {logic [3:3][0:0][width-1:0] field;} user_type_t; intf #( - .data_t(user_type_t), - .arr(arr) + .data_t(user_type_t), + .arr(arr) ) the_intf (); logic [width-1:0] signal; @@ -64,8 +68,10 @@ module sub #( end endmodule -module sc #(parameter scp_cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp_cfg_t cfg = 0 +) ( + sc_if io ); typedef io.a_t a_t; @@ -75,14 +81,20 @@ module sc #(parameter scp_cfg_t cfg=0) ( end endmodule -module t (); +module t; localparam scp_cfg_t sc_cfg = '{ABits: 2, BBits: 3}; sc_if #(sc_cfg) sc_io (); sc #(sc_cfg) sc_inst (.io(sc_io)); - sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); - sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); + sub #( + .width(8), + .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub8 (); + sub #( + .width(16), + .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub16 (); typedef sc_io.types.a_if0.a_t inner_t; typedef sc_io.types.a_t mid_t; diff --git a/test_regress/t/t_lparam_dep_iface16.v b/test_regress/t/t_lparam_dep_iface16.v index 1a68ec3e2..4e04f1c00 100644 --- a/test_regress/t/t_lparam_dep_iface16.v +++ b/test_regress/t/t_lparam_dep_iface16.v @@ -18,37 +18,41 @@ typedef struct packed { int unsigned BBits; } scp_cfg_t; -interface a_if #(parameter a_p = 0)(); +interface a_if #( + parameter a_p = 0 +) (); localparam int LP0 = a_p; typedef logic [LP0-1:0] a_t; endinterface -interface sct_if #(parameter scp_cfg_t cfg = 0)(); +interface sct_if #( + parameter scp_cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_if0(); + a_if #(LP0) a_if0 (); typedef a_if0.a_t a_t; endinterface -interface sc_if #(parameter scp_cfg_t cfg = 0)(); - sct_if #(cfg) types(); +interface sc_if #( + parameter scp_cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); typedef types.a_t a_t; endinterface interface intf #( - parameter type data_t = bit, - parameter int arr[2][4] + parameter type data_t = bit, + parameter int arr[2][4] ) (); data_t data; logic [$bits(data)-1:0] other_data; endinterface module sub #( - parameter int width, - parameter int arr[2][4] + parameter int width, + parameter int arr[2][4] ) (); - typedef struct packed { - logic [3:3] [0:0] [width-1:0] field; - } user_type_t; + typedef struct packed {logic [3:3][0:0][width-1:0] field;} user_type_t; intf #( .data_t(user_type_t), @@ -58,13 +62,15 @@ module sub #( logic [width-1:0] signal; always_comb begin - the_intf.data.field = signal; - the_intf.other_data = signal; + the_intf.data.field = signal; + the_intf.other_data = signal; end endmodule -module sc #(parameter scp_cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp_cfg_t cfg = 0 +) ( + sc_if io ); typedef io.a_t a_t; @@ -74,13 +80,18 @@ module sc #(parameter scp_cfg_t cfg=0) ( end endmodule -module t (input clk); +module t ( + input clk +); localparam scp_cfg_t sc_cfg = '{ABits: 2, BBits: 3}; sc_if #(sc_cfg) sc_io (); sc #(sc_cfg) sc_inst (.io(sc_io)); - sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); + sub #( + .width(8), + .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub8 (); typedef sc_io.types.a_if0.a_t inner_t; typedef sc_io.types.a_t mid_t; diff --git a/test_regress/t/t_lparam_dep_iface2.v b/test_regress/t/t_lparam_dep_iface2.v index afa27b5f2..6189846a0 100644 --- a/test_regress/t/t_lparam_dep_iface2.v +++ b/test_regress/t/t_lparam_dep_iface2.v @@ -25,7 +25,9 @@ package p2; } cfg_t; endpackage -interface types_if #(parameter p1::cfg_t cfg=0)(); +interface types_if #( + parameter p1::cfg_t cfg = 0 +) (); localparam int ABits = cfg.ABits; localparam int BBits = cfg.BBits; @@ -35,7 +37,9 @@ interface types_if #(parameter p1::cfg_t cfg=0)(); } a_t; endinterface -interface io_if #(parameter p1::cfg_t cfg=0)(); +interface io_if #( + parameter p1::cfg_t cfg = 0 +) (); localparam int ABits = cfg.ABits; localparam int BBits = cfg.BBits; @@ -44,8 +48,8 @@ interface io_if #(parameter p1::cfg_t cfg=0)(); typedef types.a_t a_t; endinterface -module modA( - io_if io +module modA ( + io_if io ); localparam int ABits = io.types.ABits; @@ -62,24 +66,16 @@ module modA( endmodule -module t (); - localparam p2::cfg_t mcfg = '{ - CBits : 8, - DBits : 16 - }; +module t; + localparam p2::cfg_t mcfg = '{CBits : 8, DBits : 16}; - localparam p1::cfg_t cfg = '{ - ABits : mcfg.CBits, - BBits : mcfg.CBits + mcfg.DBits - }; + localparam p1::cfg_t cfg = '{ABits : mcfg.CBits, BBits : mcfg.CBits + mcfg.DBits}; io_if #(cfg) modA_io (); typedef modA_io.types.a_t a_t; - modA modA_inst ( - .io(modA_io) - ); + modA modA_inst (.io(modA_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface3.v b/test_regress/t/t_lparam_dep_iface3.v index 5675fc8c1..cd4a2f573 100644 --- a/test_regress/t/t_lparam_dep_iface3.v +++ b/test_regress/t/t_lparam_dep_iface3.v @@ -29,16 +29,16 @@ package sc; endpackage interface simple_cache_types_if #( - parameter sc::cfg_t cfg = 0 -)(); + parameter sc::cfg_t cfg = 0 +) (); - localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; - localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; - localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); - localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); - localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; - localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; - localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; + localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.Associativity-1:0] assoc_oh_t; @@ -73,9 +73,9 @@ interface simple_cache_types_if #( endinterface interface simple_cache_if #( - parameter sc::cfg_t cfg = 0 -)(); - simple_cache_types_if #(cfg) types(); + parameter sc::cfg_t cfg = 0 +) (); + simple_cache_types_if #(cfg) types (); typedef types.cmd_tag_t cmd_tag_t; typedef types.addr_t addr_t; @@ -83,8 +83,10 @@ interface simple_cache_if #( endinterface -module simple_cache #(parameter sc::cfg_t cfg=0) ( - simple_cache_if io +module simple_cache #( + parameter sc::cfg_t cfg = 0 +) ( + simple_cache_if io ); typedef io.types.addr_t addr_t; @@ -99,11 +101,11 @@ module simple_cache #(parameter sc::cfg_t cfg=0) ( localparam num_rld_beats = cfg.LineSize / cfg.RefillWidth; localparam num_arrays = cfg.FgWidth / cfg.RefillWidth; - localparam dat_array_width = cfg.RefillWidth*8; - localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE; - localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; - localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY; - localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS; + localparam dat_array_width = cfg.RefillWidth * 8; + localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE; + localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; + localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY; + localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS; initial begin #1; @@ -119,26 +121,24 @@ module simple_cache #(parameter sc::cfg_t cfg=0) ( endmodule -module t(); +module t; localparam sc::cfg_t sc_cfg = '{ - CmdTagBits : $clog2(6), - Associativity : 2, - Capacity : 1024, - LineSize : 64, - StateBits : 2, - AddrBits : 64, - MissQSize : 2, + CmdTagBits : $clog2(6), + Associativity : 2, + Capacity : 1024, + LineSize : 64, + StateBits : 2, + AddrBits : 64, + MissQSize : 2, - FgWidth : 16, - RefillWidth : 8 + FgWidth : 16, + RefillWidth : 8 }; simple_cache_if #(sc_cfg) sc_io (); - simple_cache #(sc_cfg) simple_cache( - .io(sc_io) - ); + simple_cache #(sc_cfg) simple_cache (.io(sc_io)); //localparam int SC_DROWS_PER_LINE = sc_io.types.SC_DROWS_PER_LINE; //localparam int SC_NUM_LINES = sc_io.types.SC_NUM_LINES; diff --git a/test_regress/t/t_lparam_dep_iface4.v b/test_regress/t/t_lparam_dep_iface4.v index d81eab7c0..f31de4c9c 100644 --- a/test_regress/t/t_lparam_dep_iface4.v +++ b/test_regress/t/t_lparam_dep_iface4.v @@ -19,10 +19,10 @@ package scp; endpackage interface sct_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); - localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; typedef logic [(cfg.Capacity / cfg.LineSize)-1:0] sc_num_lines_t; @@ -31,17 +31,19 @@ interface sct_if #( endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); - sct_if #(cfg) types(); + parameter scp::cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); - localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; + localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; typedef io.types.sc_num_lines_t sc_num_lines_t; typedef io.types.sc_num_lines_2_t sc_num_lines_2_t; @@ -57,18 +59,13 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); +module t; - localparam scp::cfg_t sc_cfg = '{ - Capacity : 1024, - LineSize : 64 - }; + localparam scp::cfg_t sc_cfg = '{Capacity : 1024, LineSize : 64}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) simple_cache( - .io(sc_io) - ); + sc #(sc_cfg) simple_cache (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface5.v b/test_regress/t/t_lparam_dep_iface5.v index cb0c654d9..7fdb47e79 100644 --- a/test_regress/t/t_lparam_dep_iface5.v +++ b/test_regress/t/t_lparam_dep_iface5.v @@ -21,29 +21,31 @@ package scp; endpackage interface sct_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); // this is intentional as I want all the dependencies to be resolved - localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; - localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; - localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); - localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); - localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; typedef logic [SC_TAG_BITS-1:0] tag_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); - sct_if #(cfg) types(); + parameter scp::cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); - sct_if #(cfg) types(); + sct_if #(cfg) types (); typedef io.types.tag_t tag_t; typedef types.tag_t tag2_t; @@ -55,21 +57,19 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); +module t; localparam scp::cfg_t sc_cfg = '{ - Associativity : 2, - Capacity : 1024, - LineSize : 64, - AddrBits : 64 + Associativity : 2, + Capacity : 1024, + LineSize : 64, + AddrBits : 64 }; sc_if #(sc_cfg) sc_io (); typedef sc_io.types.tag_t tag_t; - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface6.v b/test_regress/t/t_lparam_dep_iface6.v index e19b8a6a4..fb6cd6375 100644 --- a/test_regress/t/t_lparam_dep_iface6.v +++ b/test_regress/t/t_lparam_dep_iface6.v @@ -19,32 +19,34 @@ package scp; endpackage interface a_if #( - parameter a_p = 0 -)(); - localparam int LP0 = a_p; + parameter a_p = 0 +) (); + localparam int LP0 = a_p; typedef logic [LP0-1:0] a_t; endinterface interface sct_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); // this is intentional as I want all the dependencies to be resolved - localparam int LP0 = cfg.ABits * cfg.BBits; + localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_if0(); + a_if #(LP0) a_if0 (); typedef a_if0.a_t a_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); - sct_if #(cfg) types(); + parameter scp::cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); typedef types.a_t a_t; endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.a_t a_t; @@ -56,17 +58,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface7.v b/test_regress/t/t_lparam_dep_iface7.v index 133d8a802..e045e9de5 100644 --- a/test_regress/t/t_lparam_dep_iface7.v +++ b/test_regress/t/t_lparam_dep_iface7.v @@ -19,22 +19,24 @@ package scp; endpackage interface a_if #( - parameter a_p = 0 -)(); - localparam int LP0 = a_p * 2; + parameter a_p = 0 +) (); + localparam int LP0 = a_p * 2; typedef logic [LP0-1:0] a_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); - localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) types(); + localparam int LP0 = cfg.ABits * cfg.BBits; + a_if #(LP0) types (); endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.types.a_t a_t; @@ -46,17 +48,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface8.v b/test_regress/t/t_lparam_dep_iface8.v index 3d8c325c0..cb9c0223f 100644 --- a/test_regress/t/t_lparam_dep_iface8.v +++ b/test_regress/t/t_lparam_dep_iface8.v @@ -20,31 +20,33 @@ endpackage // Level 3: innermost interface interface a_if #( - parameter a_p = 0 -)(); + parameter a_p = 0 +) (); localparam int LP0 = a_p * 2; typedef logic [LP0-1:0] a_t; endinterface // Level 2: middle interface interface sct_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_if0(); + a_if #(LP0) a_if0 (); typedef a_if0.a_t a_t; endinterface // Level 1: outermost interface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); - sct_if #(cfg) types(); + parameter scp::cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); typedef types.a_t a_t; endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.a_t a_t; @@ -56,17 +58,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface9.v b/test_regress/t/t_lparam_dep_iface9.v index 0e994e057..3c04fb769 100644 --- a/test_regress/t/t_lparam_dep_iface9.v +++ b/test_regress/t/t_lparam_dep_iface9.v @@ -20,23 +20,25 @@ endpackage // Interface with chained localparam dependencies interface a_if #( - parameter a_p = 0 -)(); - localparam int LP0 = a_p * 2; // LP0 = a_p * 2 - localparam int LP1 = LP0 + 1; // LP1 = LP0 + 1 - localparam int LP2 = LP1 * LP0; // LP2 = LP1 * LP0 + parameter a_p = 0 +) (); + localparam int LP0 = a_p * 2; // LP0 = a_p * 2 + localparam int LP1 = LP0 + 1; // LP1 = LP0 + 1 + localparam int LP2 = LP1 * LP0; // LP2 = LP1 * LP0 typedef logic [LP2-1:0] a_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) types(); + a_if #(LP0) types (); endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.types.a_t a_t; @@ -49,17 +51,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_mailbox_concurrent.v b/test_regress/t/t_mailbox_concurrent.v index a719cfaf5..308c91877 100644 --- a/test_regress/t/t_mailbox_concurrent.v +++ b/test_regress/t/t_mailbox_concurrent.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2024 Liam Braun // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; mailbox #(int) m; task automatic test_get; diff --git a/test_regress/t/t_math_width.v b/test_regress/t/t_math_width.v index d53ae51eb..603cdc21a 100644 --- a/test_regress/t/t_math_width.v +++ b/test_regress/t/t_math_width.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; // See also t_lint_width diff --git a/test_regress/t/t_mod_interface_clocking_bad.v b/test_regress/t/t_mod_interface_clocking_bad.v index e64550fa7..a56f1ed5a 100644 --- a/test_regress/t/t_mod_interface_clocking_bad.v +++ b/test_regress/t/t_mod_interface_clocking_bad.v @@ -27,7 +27,7 @@ module sub ( endmodule -module t (); +module t; logic clk = 0; mem_if m_if (clk); diff --git a/test_regress/t/t_mod_longname.v b/test_regress/t/t_mod_longname.v index 8ba6c653f..7d6d0d0da 100644 --- a/test_regress/t/t_mod_longname.v +++ b/test_regress/t/t_mod_longname.v @@ -10,7 +10,7 @@ `define LONG_NAME_SUB sublongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie `define LONG_NAME_VAR varlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie -module t (); +module t; initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_name_collision.v b/test_regress/t/t_name_collision.v index 4f232e0b3..d2191f1bd 100644 --- a/test_regress/t/t_name_collision.v +++ b/test_regress/t/t_name_collision.v @@ -9,7 +9,7 @@ module HasNameParam (); endmodule -module t (); +module t; HasNameParam a(); initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_opt_merge_cond_relaxed.v b/test_regress/t/t_opt_merge_cond_relaxed.v index c48e0f5e9..d84a24008 100644 --- a/test_regress/t/t_opt_merge_cond_relaxed.v +++ b/test_regress/t/t_opt_merge_cond_relaxed.v @@ -4,8 +4,10 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0) +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on module t; @@ -26,19 +28,19 @@ module t; dpiWr = value; endfunction export "DPI-C" function setDpi; - import "DPI-C" context function void setViaDpi(int value); // calls setDpi(value) + import "DPI-C" context function void setViaDpi(int value); // calls setDpi(value) int dpiRd = 0; function automatic int getDpi(); return dpiRd; endfunction export "DPI-C" function getDpi; - import "DPI-C" context function int getViaDpi(); // calls getDpi() + import "DPI-C" context function int getViaDpi(); // calls getDpi() int tmp; int cnt = 0; - int pub /* verilator public_flat_rd */ = 0; + int pub /* verilator public_flat_rd */ = 0; always @(posedge clk) begin @@ -60,7 +62,7 @@ module t; if (cyc[1:0] == 2'd2) setViaDpi(cyc + 16); ++cnt; if (cyc[1:0] == 2'd2) setViaDpi(cyc + 32); - `check(dpiWr, cyc % 4 == 2 ? cyc + 32 : 13); + `checkd(dpiWr, cyc % 4 == 2 ? cyc + 32 : 13); // DPI call, but no public state involved. dpiRd = 24; @@ -74,7 +76,7 @@ module t; tmp = getViaDpi(); tmp += 20; end - `check(tmp, cyc % 4 == 1 ? 44 : 10); + `checkd(tmp, cyc % 4 == 1 ? 44 : 10); //--------------------------- // NOT Mergeable @@ -82,36 +84,36 @@ module t; // DPI call, possible implicit state chagne. tmp = dpiWr; if (dpiWr[1:0] == 2'd2) setViaDpi(dpiWr & ~32'b11); - if (dpiWr[1:0] == 2'd2) setViaDpi(dpiWr + 10); // Won't execute - `check(dpiWr, cyc % 4 == 2 ? (tmp & ~32'b11) : 13); + if (dpiWr[1:0] == 2'd2) setViaDpi(dpiWr + 10); // Won't execute + `checkd(dpiWr, cyc % 4 == 2 ? (tmp & ~32'b11) : 13); // DPI call, possible implicit state acces. dpiWr = 14; if (cyc[1:0] == 2'd3) setViaDpi(cyc + 32); ++pub; if (cyc[1:0] == 2'd3) setViaDpi(cyc + 64); - `check(dpiWr, cyc % 4 == 3 ? cyc + 64 : 14); + `checkd(dpiWr, cyc % 4 == 3 ? cyc + 64 : 14); // DPI call, possible implicit state change. dpiWr = 11; - tmp = cyc + $c(0); // Prevent repalcing with 'cyc' + tmp = cyc + $c(0); // Prevent repalcing with 'cyc' if (tmp % 3 == 0) begin - setViaDpi(3); - tmp = dpiWr + 2; + setViaDpi(3); + tmp = dpiWr + 2; end - if (tmp % 3 == 0) setViaDpi(4); // Won't execute - `check(dpiWr, cyc % 3 == 0 ? 3 : 11); + if (tmp % 3 == 0) setViaDpi(4); // Won't execute + `checkd(dpiWr, cyc % 3 == 0 ? 3 : 11); dpiWr = 3; // DPI call, possible implicit state change. - tmp = cyc + $c(0); // Prevent repalcing with 'cyc' + tmp = cyc + $c(0); // Prevent repalcing with 'cyc' if (tmp % 2 == 0) begin - setViaDpi(6); - if (cyc[2]) tmp = dpiWr + 1; + setViaDpi(6); + if (cyc[2]) tmp = dpiWr + 1; end - if (tmp % 2 == 0) setViaDpi(4); // Sometime executes - `check(tmp, cyc % 2 == 0 ? (cyc[2] ? 7 : cyc) : cyc); - `check(dpiWr, cyc % 2 == 0 ? (cyc[2] ? 6 : 4) : 3); + if (tmp % 2 == 0) setViaDpi(4); // Sometime executes + `checkd(tmp, cyc % 2 == 0 ? (cyc[2] ? 7 : cyc) : cyc); + `checkd(dpiWr, cyc % 2 == 0 ? (cyc[2] ? 6 : 4) : 3); // DPI call, possible implicit state read. dpiRd = 2; @@ -122,8 +124,8 @@ module t; if (cyc[1:0] == 2'd1) begin dpiRd = 3; end - `check(tmp, cyc % 4 == 1 ? 100 : 2); - `check(dpiRd, cyc % 4 == 1 ? 3 : 2); + `checkd(tmp, cyc % 4 == 1 ? 100 : 2); + `checkd(dpiRd, cyc % 4 == 1 ? 3 : 2); //--------------------------- // Dispaly so not eliminated diff --git a/test_regress/t/t_package_abs.v b/test_regress/t/t_package_abs.v index 5ea79a8e3..a265e1861 100644 --- a/test_regress/t/t_package_abs.v +++ b/test_regress/t/t_package_abs.v @@ -15,7 +15,7 @@ package functions; endfunction endpackage -module t (); +module t; import functions::*; localparam P = 1; generate diff --git a/test_regress/t/t_package_ddecl.v b/test_regress/t/t_package_ddecl.v index 03cedbe40..ad24d2901 100644 --- a/test_regress/t/t_package_ddecl.v +++ b/test_regress/t/t_package_ddecl.v @@ -14,7 +14,7 @@ package functions; endtask endpackage -module t (); +module t; // synthesis translate off import functions::*; // synthesis translate on diff --git a/test_regress/t/t_param_default_override.v b/test_regress/t/t_param_default_override.v index 65caaa4d4..c70582101 100644 --- a/test_regress/t/t_param_default_override.v +++ b/test_regress/t/t_param_default_override.v @@ -42,7 +42,7 @@ module m8 #(parameter int N = 4) endmodule -module t (); +module t; reg [5:0] i0, i1, i2, i3; reg [1:0] S; wire [5:0] Y; diff --git a/test_regress/t/t_param_pattern2.v b/test_regress/t/t_param_pattern2.v index 64211085b..1245de47c 100644 --- a/test_regress/t/t_param_pattern2.v +++ b/test_regress/t/t_param_pattern2.v @@ -10,7 +10,7 @@ module dut assign x = P[2]; endmodule -module t(); +module t; int o; dut #(.P('{1, 2, 3, 4, 5})) u_dut(.x(o)); diff --git a/test_regress/t/t_param_real.v b/test_regress/t/t_param_real.v index 0190587e5..543e317d7 100644 --- a/test_regress/t/t_param_real.v +++ b/test_regress/t/t_param_real.v @@ -14,7 +14,7 @@ module mod #( end endmodule -module t(); +module t; mod #(.HZ(123.45)) mod1(); mod #(.HZ(24.45)) mod2(); diff --git a/test_regress/t/t_param_real2.v b/test_regress/t/t_param_real2.v index ecdca0549..03f225549 100644 --- a/test_regress/t/t_param_real2.v +++ b/test_regress/t/t_param_real2.v @@ -9,7 +9,7 @@ module foo endmodule -module t(); +module t; genvar m, r; generate diff --git a/test_regress/t/t_param_type_cmp.v b/test_regress/t/t_param_type_cmp.v index 547986c89..99ce7ad7b 100644 --- a/test_regress/t/t_param_type_cmp.v +++ b/test_regress/t/t_param_type_cmp.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; logic [2:0] a; logic [2:0] b; diff --git a/test_regress/t/t_param_type_from_iface_struct.v b/test_regress/t/t_param_type_from_iface_struct.v index 9628c9748..65331477a 100644 --- a/test_regress/t/t_param_type_from_iface_struct.v +++ b/test_regress/t/t_param_type_from_iface_struct.v @@ -26,32 +26,36 @@ package cfg_pkg; endpackage // Parameterized inner interface with struct typedefs -interface inner_if #(parameter cfg_pkg::cfg_t cfg = '0); +interface inner_if #( + parameter cfg_pkg::cfg_t cfg = '0 +); typedef struct packed { - logic [cfg.IdBits-1:0] id; + logic [cfg.IdBits-1:0] id; logic [cfg.DataBits-1:0] data; } req_t; typedef struct packed { - logic [cfg.IdBits-1:0] id; - logic [1:0] resp; + logic [cfg.IdBits-1:0] id; + logic [1:0] resp; } resp_t; - req_t req; + req_t req; resp_t resp; endinterface // Outer interface containing a nested inner_if -interface outer_if #(parameter cfg_pkg::cfg_t cfg = '0); - inner_if #(cfg) inner(); +interface outer_if #( + parameter cfg_pkg::cfg_t cfg = '0 +); + inner_if #(cfg) inner (); endinterface // Module with type parameters (consumer of struct typedefs) module typed_mod #( - parameter type req_t = logic, - parameter type resp_t = logic -)( - input logic clk + parameter type req_t = logic, + parameter type resp_t = logic +) ( + input logic clk ); - req_t r; + req_t r; resp_t s; assign r = '0; assign s = '0; @@ -59,30 +63,42 @@ endmodule // Wrapper: takes outer_if ports, typedefs through two-level nesting, // passes as type parameters to typed_mod -module wrap_mod #(parameter int NUM = 1)( - input logic clk, - outer_if ports [NUM] +module wrap_mod #( + parameter int NUM = 1 +) ( + input logic clk, + outer_if ports[NUM] ); - typedef ports[0].inner.req_t local_req_t; + typedef ports[0].inner.req_t local_req_t; typedef ports[0].inner.resp_t local_resp_t; - typed_mod #(.req_t(local_req_t), .resp_t(local_resp_t)) u_sub(.clk(clk)); + typed_mod #( + .req_t(local_req_t), + .resp_t(local_resp_t) + ) u_sub ( + .clk(clk) + ); endmodule -module t(); +module t; logic clk = 0; localparam cfg_pkg::cfg_t CFG_A = '{IdBits: 4, DataBits: 32}; localparam cfg_pkg::cfg_t CFG_B = '{IdBits: 8, DataBits: 64}; // Force inner_if to be cloned with different configs first - inner_if #(CFG_A) early_a(); - inner_if #(CFG_B) early_b(); + inner_if #(CFG_A) early_a (); + inner_if #(CFG_B) early_b (); assign early_a.req = '0; assign early_a.resp = '0; assign early_b.req = '0; assign early_b.resp = '0; - outer_if #(CFG_A) io [2] (); - wrap_mod #(.NUM(2)) u_wrap(.clk(clk), .ports(io)); + outer_if #(CFG_A) io[2] (); + wrap_mod #( + .NUM(2) + ) u_wrap ( + .clk(clk), + .ports(io) + ); initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_param_up_bad.v b/test_regress/t/t_param_up_bad.v index b0632a1dc..92bf6d5e9 100644 --- a/test_regress/t/t_param_up_bad.v +++ b/test_regress/t/t_param_up_bad.v @@ -26,7 +26,7 @@ module parent child c (); endmodule -module t (); +module t; // The parameter must be anything other than the default parent #( 1 ) p (); endmodule diff --git a/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v b/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v index c1eda693e..1f83bb8d6 100644 --- a/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v +++ b/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v @@ -12,30 +12,30 @@ // verilog_format: on package axis; - typedef struct packed { - int unsigned DataWidth; - } cfg_t; + typedef struct packed {int unsigned DataWidth;} cfg_t; endpackage -interface axis_if #(parameter axis::cfg_t cfg = '0)(); +interface axis_if #( + parameter axis::cfg_t cfg = '0 +) (); typedef logic [cfg.DataWidth-1:0] tdata_t; endinterface module axis_chan #( - parameter axis::cfg_t chan_cfg = '0 + parameter axis::cfg_t chan_cfg = '0 ) (); - axis_if #(chan_cfg) axis_channel_io(); + axis_if #(chan_cfg) axis_channel_io (); typedef axis_channel_io.tdata_t data_t; localparam int kWidth = $bits(data_t); initial begin #1; - `checkd(kWidth,32); + `checkd(kWidth, 32); end endmodule module t; localparam axis::cfg_t axis_chan_cfg = '{DataWidth: 32}; - axis_chan #(.chan_cfg(axis_chan_cfg)) u_chan(); + axis_chan #(.chan_cfg(axis_chan_cfg)) u_chan (); initial begin #2; $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_paramgraph_bisect1.v b/test_regress/t/t_paramgraph_bisect1.v index 4de603c87..c97351006 100644 --- a/test_regress/t/t_paramgraph_bisect1.v +++ b/test_regress/t/t_paramgraph_bisect1.v @@ -17,7 +17,7 @@ package rial; -// Configuration structure + // Configuration structure typedef struct packed { // CCA Parameters int unsigned NumDd; @@ -29,16 +29,18 @@ endpackage package cb; typedef struct packed { - int unsigned XdatSize; // raw packet data size + int unsigned XdatSize; // raw packet data size } cfg_t; endpackage -interface ccia_types_if #(parameter rial::cfg_t cfg=0)(); +interface ccia_types_if #( + parameter rial::cfg_t cfg = 0 +) (); // 'base' types typedef logic [$clog2(cfg.DDNumStuff)-1:0] wave_index_t; -// types for tb + // types for tb typedef struct packed { logic [3:0] e_cmd; logic en; @@ -48,39 +50,31 @@ interface ccia_types_if #(parameter rial::cfg_t cfg=0)(); logic [64-(4+1+1+$clog2(cfg.DDNumStuff)+12)-1:0] pad0; } tl_reg_cmd_t; - typedef struct packed { - logic [63:0] raw; - } tl_addr_cmd_t; + typedef struct packed {logic [63:0] raw;} tl_addr_cmd_t; typedef union packed { tl_reg_cmd_t rcmd; tl_addr_cmd_t acmd; } tl_data_fld_t; - typedef union packed { - tl_data_fld_t [cfg.DDNumStuffThreads-1:0] d_a; - } cmd_data_t; + typedef union packed {tl_data_fld_t [cfg.DDNumStuffThreads-1:0] d_a;} cmd_data_t; - typedef struct packed { - cmd_data_t d; - } cmd_beat_t; + typedef struct packed {cmd_data_t d;} cmd_beat_t; endinterface module rial_top #( - parameter rial::cfg_t aer_cfg=0 -)(); + parameter rial::cfg_t aer_cfg = 0 +) (); -// for the types - ccia_types_if #(aer_cfg) ccia_types(); + // for the types + ccia_types_if #(aer_cfg) ccia_types (); -// genvars and locally defined types + // genvars and locally defined types typedef ccia_types.cmd_beat_t cmd_beat_t; // CB and RBUS - localparam cb::cfg_t cb_cfg = '{ - XdatSize:$bits(cmd_beat_t) - }; + localparam cb::cfg_t cb_cfg = '{XdatSize: $bits(cmd_beat_t)}; initial begin #1; @@ -93,19 +87,18 @@ module rial_top #( endmodule // SOC Top w/IO and SOC configuration -module rial_wrap(); +module rial_wrap (); parameter rial::cfg_t aer_cfg = '{ - NumDd : 3, - // CC Parameters - DDNumStuff : 4, - DDNumStuffThreads : 8 + NumDd : 3, + // CC Parameters + DDNumStuff : + 4, + DDNumStuffThreads : 8 }; -// DUT - rial_top #( - .aer_cfg(aer_cfg) - ) rial_top(); + // DUT + rial_top #(.aer_cfg(aer_cfg)) rial_top (); initial begin #2; diff --git a/test_regress/t/t_paramgraph_bits_corruption.v b/test_regress/t/t_paramgraph_bits_corruption.v index e5a34d207..f31d3da79 100644 --- a/test_regress/t/t_paramgraph_bits_corruption.v +++ b/test_regress/t/t_paramgraph_bits_corruption.v @@ -35,7 +35,7 @@ package TestPkg; logic [31:0] field14; logic [31:0] field15; logic [31:0] field16; - logic [12:0] field17; // 525 bits total (16*32 + 13) + logic [12:0] field17; // 525 bits total (16*32 + 13) } cmd_beat_t; typedef struct packed { @@ -50,10 +50,10 @@ package TestPkg; // where the pattern literal gets a 128-bit constant instead of proper 32-bit assignment // Note: cmd_beat_t is referenced directly, not through a localparam type alias localparam cfg_t cb_cfg = '{ - Rids : 32'h1, - Pids : 32'h2, - Fnum : 32'h3, - XdatSize : $bits(cmd_beat_t) // Should be 525, but gets corrupted + Rids : 32'h1, + Pids : 32'h2, + Fnum : 32'h3, + XdatSize : $bits(cmd_beat_t) // Should be 525, but gets corrupted }; endpackage diff --git a/test_regress/t/t_paramgraph_bits_iface_typedef.v b/test_regress/t/t_paramgraph_bits_iface_typedef.v index 81cb7e258..12a236295 100644 --- a/test_regress/t/t_paramgraph_bits_iface_typedef.v +++ b/test_regress/t/t_paramgraph_bits_iface_typedef.v @@ -11,7 +11,7 @@ // Interface with a packed struct typedef interface axis_if #( - parameter int DataWidth = 8 + parameter int DataWidth = 8 ); typedef struct packed { logic [DataWidth-1:0] data; @@ -22,27 +22,27 @@ interface axis_if #( logic tvalid; logic tready; - modport initiator (output tdata, tvalid, input tready); - modport target (input tdata, tvalid, output tready); + modport initiator(output tdata, tvalid, input tready); + modport target(input tdata, tvalid, output tready); endinterface // Simple buffer module that takes a width parameter module skid_buffer #( - parameter int p_width = 8 + parameter int p_width = 8 ) ( - input logic clk, - input logic [p_width-1:0] data_i, - output logic [p_width-1:0] data_o + input logic clk, + input logic [p_width-1:0] data_i, + output logic [p_width-1:0] data_o ); always_ff @(posedge clk) data_o <= data_i; endmodule // Module that uses $bits() of an interface typedef as a parameter module axis_upsizer #( - parameter int p_has_skid = 1 + parameter int p_has_skid = 1 ) ( - input logic clk, - axis_if.initiator op_io + input logic clk, + axis_if.initiator op_io ); // Typedef from interface port typedef op_io.pkt_t op_pkt_t; @@ -50,15 +50,17 @@ module axis_upsizer #( op_pkt_t op_pkt_int; generate - if (p_has_skid>0) begin : gen_skid + if (p_has_skid > 0) begin : gen_skid op_pkt_t skid_src_pkt; // This is the problematic line - $bits(op_pkt_t) used as parameter // The PARAMTYPEDTYPE for op_pkt_t has REQUIREDTYPE that needs resolution - skid_buffer #(.p_width($bits(op_pkt_t))) skid ( - .clk(clk), - .data_i(op_pkt_int), - .data_o(skid_src_pkt) + skid_buffer #( + .p_width($bits(op_pkt_t)) + ) skid ( + .clk(clk), + .data_i(op_pkt_int), + .data_o(skid_src_pkt) ); end endgenerate @@ -67,11 +69,13 @@ endmodule module top; logic clk; - axis_if #(.DataWidth(32)) op_if(); + axis_if #(.DataWidth(32)) op_if (); - axis_upsizer #(.p_has_skid(1)) u_upsizer ( - .clk(clk), - .op_io(op_if.initiator) + axis_upsizer #( + .p_has_skid(1) + ) u_upsizer ( + .clk(clk), + .op_io(op_if.initiator) ); initial begin diff --git a/test_regress/t/t_paramgraph_cloned_refdtype.v b/test_regress/t/t_paramgraph_cloned_refdtype.v index 92700abdc..7b5d37f98 100644 --- a/test_regress/t/t_paramgraph_cloned_refdtype.v +++ b/test_regress/t/t_paramgraph_cloned_refdtype.v @@ -14,7 +14,10 @@ // // A registry class that returns its own type -class uvm_object_registry #(type T = int, string Tname = ""); +class uvm_object_registry #( + type T = int, + string Tname = "" +); typedef uvm_object_registry#(T, Tname) this_type; static function this_type get(); @@ -26,7 +29,9 @@ endclass // A pool class that has a nested type_id typedef pointing to the registry // The key pattern: type_id is a typedef to uvm_object_registry parameterized with THIS class -class uvm_object_string_pool #(type T = int); +class uvm_object_string_pool #( + type T = int +); typedef uvm_object_string_pool#(T) this_type; typedef uvm_object_registry#(uvm_object_string_pool#(T)) type_id; @@ -49,10 +54,14 @@ class uvm_object_string_pool #(type T = int); endclass // Simple wrapper classes to create different specializations -class uvm_queue #(type T = int); +class uvm_queue #( + type T = int +); endclass -class uvm_event #(type T = int); +class uvm_event #( + type T = int +); endclass // Create two different specializations of uvm_object_string_pool @@ -66,8 +75,8 @@ module t; // Before the fix, both would incorrectly return the same registry type // After the fix, each returns its own correctly-specialized registry - uvm_object_registry#(uvm_object_string_pool#(uvm_event#(int))) event_reg; - uvm_object_registry#(uvm_object_string_pool#(uvm_queue#(string))) queue_reg; + uvm_object_registry #(uvm_object_string_pool #(uvm_event #(int))) event_reg; + uvm_object_registry #(uvm_object_string_pool #(uvm_queue #(string))) queue_reg; event_reg = uvm_event_pool::get_type(); queue_reg = uvm_queue_pool::get_type(); diff --git a/test_regress/t/t_paramgraph_comined_iface.v b/test_regress/t/t_paramgraph_comined_iface.v index 8f844903e..c3590707b 100644 --- a/test_regress/t/t_paramgraph_comined_iface.v +++ b/test_regress/t/t_paramgraph_comined_iface.v @@ -26,7 +26,9 @@ typedef struct packed { } axi_cfg_t; // INNERMOST: Parameterized interface with typedefs -interface axi4_if #(parameter axi_cfg_t cfg = 0)(); +interface axi4_if #( + parameter axi_cfg_t cfg = 0 +) (); localparam int unsigned AddrBits = cfg.AddrBits * 2; localparam int unsigned DataBits = cfg.DataBits * 2; localparam int unsigned IdBits = cfg.IdBits * 2; @@ -36,22 +38,24 @@ interface axi4_if #(parameter axi_cfg_t cfg = 0)(); typedef logic [IdBits-1:0] id_t; typedef struct packed { - id_t id; - addr_t addr; + id_t id; + addr_t addr; } ar_chan_t; typedef struct packed { - id_t id; - data_t data; + id_t id; + data_t data; } r_chan_t; ar_chan_t ar; - r_chan_t r; + r_chan_t r; endinterface // MIDDLE: Interface that wraps axi4_if and re-exports its typedefs -interface tlb_io_if #(parameter axi_cfg_t axi_cfg = 0)(); - axi4_if #(.cfg(axi_cfg)) axi_tlb_io(); +interface tlb_io_if #( + parameter axi_cfg_t axi_cfg = 0 +) (); + axi4_if #(.cfg(axi_cfg)) axi_tlb_io (); // Re-export typedefs from nested interface typedef axi_tlb_io.r_chan_t r_chan_t; @@ -61,12 +65,12 @@ endinterface // OUTER: Interface with TWO SIBLING tlb_io_if instances with DIFFERENT params // This is the BLENDED pattern: sibling cells + nested chains interface cca_io_if #( - parameter axi_cfg_t axi_cfg_a = 0, - parameter axi_cfg_t axi_cfg_b = 0 -)(); + parameter axi_cfg_t axi_cfg_a = 0, + parameter axi_cfg_t axi_cfg_b = 0 +) (); // SIBLING CELLS - same interface type, DIFFERENT params - tlb_io_if #(.axi_cfg(axi_cfg_a)) tlb_io_a(); - tlb_io_if #(.axi_cfg(axi_cfg_b)) tlb_io_b(); + tlb_io_if #(.axi_cfg(axi_cfg_a)) tlb_io_a (); + tlb_io_if #(.axi_cfg(axi_cfg_b)) tlb_io_b (); // Re-export from each sibling (these should be DIFFERENT types) typedef tlb_io_a.r_chan_t r_chan_a_t; @@ -76,7 +80,7 @@ endinterface // MODULE: Accesses typedefs from BOTH sibling nested chains via interface port // This is the CRITICAL test - must distinguish between tlb_io_a and tlb_io_b module cca_xbar ( - cca_io_if cca_io + cca_io_if cca_io ); // Access typedefs through SIBLING nested interface chains // These MUST resolve to DIFFERENT types based on the different params @@ -105,12 +109,15 @@ module cca_xbar ( endmodule // TOP MODULE -module t(); +module t; localparam axi_cfg_t cfg_a = '{AddrBits: 32, DataBits: 64, IdBits: 4}; localparam axi_cfg_t cfg_b = '{AddrBits: 40, DataBits: 128, IdBits: 8}; - cca_io_if #(.axi_cfg_a(cfg_a), .axi_cfg_b(cfg_b)) cca_io(); - cca_xbar xbar(.cca_io(cca_io)); + cca_io_if #( + .axi_cfg_a(cfg_a), + .axi_cfg_b(cfg_b) + ) cca_io (); + cca_xbar xbar (.cca_io(cca_io)); initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_array_ports.v b/test_regress/t/t_paramgraph_iface_array_ports.v index be8b6d9bf..db9239cc6 100644 --- a/test_regress/t/t_paramgraph_iface_array_ports.v +++ b/test_regress/t/t_paramgraph_iface_array_ports.v @@ -22,7 +22,9 @@ package axi_pkg; } cfg_t; endpackage -interface axi4_if #(parameter axi_pkg::cfg_t cfg = '0)(); +interface axi4_if #( + parameter axi_pkg::cfg_t cfg = '0 +) (); typedef logic [cfg.IdBits-1:0] id_t; typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.UserBits-1:0] user_t; @@ -34,16 +36,20 @@ interface axi4_if #(parameter axi_pkg::cfg_t cfg = '0)(); } req_t; endinterface -module sink #(parameter int N = 1)(axi4_if tgt_ports [N-1:0]); +module sink #( + parameter int N = 1 +) ( + axi4_if tgt_ports[N-1:0] +); localparam type req_t = tgt_ports[0].req_t; req_t rq; endmodule module top; - localparam axi_pkg::cfg_t cfg = '{IdBits:4, DataBits:32, UserBits:2}; - axi4_if #(.cfg(cfg)) tgt_ports [1:0](); + localparam axi_pkg::cfg_t cfg = '{IdBits: 4, DataBits: 32, UserBits: 2}; + axi4_if #(.cfg(cfg)) tgt_ports[1:0] (); - sink #(.N(2)) u_sink(.tgt_ports(tgt_ports)); + sink #(.N(2)) u_sink (.tgt_ports(tgt_ports)); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_cfg_zero.v b/test_regress/t/t_paramgraph_iface_cfg_zero.v index 5efae55e5..dc14f75f9 100644 --- a/test_regress/t/t_paramgraph_iface_cfg_zero.v +++ b/test_regress/t/t_paramgraph_iface_cfg_zero.v @@ -22,12 +22,16 @@ package aerial; } cfg_t; endpackage -interface aicc_types_if #(parameter aerial::cfg_t cfg = '0)(); +interface aicc_types_if #( + parameter aerial::cfg_t cfg = '0 +) (); typedef logic [$clog2(cfg.NumCc)-1:0] cc_index_t; typedef logic [$clog2(cfg.CCNumIds)-1:0] trans_id_t; endinterface -module child(aicc_types_if types); +module child ( + aicc_types_if types +); localparam type cc_index_t = types.cc_index_t; localparam type trans_id_t = types.trans_id_t; cc_index_t cc_idx; @@ -35,9 +39,9 @@ module child(aicc_types_if types); endmodule module top; - localparam aerial::cfg_t aer_cfg = '{NumCc:4, CCNumWaves:2, CCNumIds:8}; - aicc_types_if #(.cfg(aer_cfg)) types(); - child u_child(.types(types)); + localparam aerial::cfg_t aer_cfg = '{NumCc: 4, CCNumWaves: 2, CCNumIds: 8}; + aicc_types_if #(.cfg(aer_cfg)) types (); + child u_child (.types(types)); initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_deadmod.v b/test_regress/t/t_paramgraph_iface_deadmod.v index e09cb446a..a84770bfb 100644 --- a/test_regress/t/t_paramgraph_iface_deadmod.v +++ b/test_regress/t/t_paramgraph_iface_deadmod.v @@ -18,7 +18,9 @@ package axi4; } cfg_t; endpackage -interface axi4_if #(parameter axi4::cfg_t cfg = '0)(); +interface axi4_if #( + parameter axi4::cfg_t cfg = '0 +) (); typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.DataBits/8-1:0] strb_t; @@ -32,8 +34,8 @@ interface axi4_if #(parameter axi4::cfg_t cfg = '0)(); } aw_chan_t; endinterface -module dead_mod( - axi4_if axi_io +module dead_mod ( + axi4_if axi_io ); typedef axi_io.addr_t addr_t; typedef axi_io.data_t data_t; @@ -45,14 +47,14 @@ module dead_mod( endmodule module dead_top; - localparam axi4::cfg_t cfg = '{IdBits:4, AddrBits:32, DataBits:64, UserBits:2}; - axi4_if #(.cfg(cfg)) axi_io(); + localparam axi4::cfg_t cfg = '{IdBits: 4, AddrBits: 32, DataBits: 64, UserBits: 2}; + axi4_if #(.cfg(cfg)) axi_io (); - dead_mod u_dead(.axi_io(axi_io)); + dead_mod u_dead (.axi_io(axi_io)); endmodule module top; - dead_top dead_top(); + dead_top dead_top (); initial begin #1; $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_paramgraph_iface_dependency1.v b/test_regress/t/t_paramgraph_iface_dependency1.v index a1dcc8e6e..f6980edc2 100644 --- a/test_regress/t/t_paramgraph_iface_dependency1.v +++ b/test_regress/t/t_paramgraph_iface_dependency1.v @@ -11,20 +11,18 @@ // verilog_format: on package a_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage -interface depgraph_if #(a_pkg::cfg_t cfg=0)(); +interface depgraph_if #( + a_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.a-1:0] byte_t; - typedef struct packed { - byte_t a; - } pair_t; + typedef struct packed {byte_t a;} pair_t; endinterface -module a_mod( - depgraph_if ifc +module a_mod ( + depgraph_if ifc ); typedef ifc.pair_t pair_t; @@ -32,20 +30,16 @@ module a_mod( initial begin #1; - `checkd($bits(pair_t),8); + `checkd($bits(pair_t), 8); `checkd(p_a, 8); end endmodule -module t(); - localparam a_pkg::cfg_t cfg = '{ - a: 8 - }; +module t; + localparam a_pkg::cfg_t cfg = '{a: 8}; - depgraph_if #(cfg) ifc(); - a_mod #() a_mod_0( - .ifc(ifc) - ); + depgraph_if #(cfg) ifc (); + a_mod #() a_mod_0 (.ifc(ifc)); initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_dependency2.v b/test_regress/t/t_paramgraph_iface_dependency2.v index 5f8160bbc..442eabaaa 100644 --- a/test_regress/t/t_paramgraph_iface_dependency2.v +++ b/test_regress/t/t_paramgraph_iface_dependency2.v @@ -11,18 +11,16 @@ // verilog_format: on package a_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage package b_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage -interface depgraph_if #(a_pkg::cfg_t cfg=0)(); +interface depgraph_if #( + a_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.a-1:0] byte_t; typedef logic [cfg.a*2-1:0] half_t; typedef struct packed { @@ -35,18 +33,14 @@ interface depgraph_if #(a_pkg::cfg_t cfg=0)(); } pair_u_t; endinterface -module t(); - localparam a_pkg::cfg_t cfg = '{ - a: 8 - }; +module t; + localparam a_pkg::cfg_t cfg = '{a: 8}; - depgraph_if #(cfg) ifc(); + depgraph_if #(cfg) ifc (); typedef ifc.pair_u_t pair_u_t; - localparam b_pkg::cfg_t cfg_b = '{ - a:$bits(pair_u_t) - }; + localparam b_pkg::cfg_t cfg_b = '{a: $bits(pair_u_t)}; initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_dependency3.v b/test_regress/t/t_paramgraph_iface_dependency3.v index 266e56b95..6064d179c 100644 --- a/test_regress/t/t_paramgraph_iface_dependency3.v +++ b/test_regress/t/t_paramgraph_iface_dependency3.v @@ -11,18 +11,16 @@ // verilog_format: on package a_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage package b_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage -interface depgraph_if #(a_pkg::cfg_t cfg=0)(); +interface depgraph_if #( + a_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.a-1:0] byte_t; typedef logic [cfg.a*2-1:0] half_t; typedef struct packed { @@ -31,8 +29,8 @@ interface depgraph_if #(a_pkg::cfg_t cfg=0)(); } pair_t; endinterface -module a_mod( - depgraph_if ifc +module a_mod ( + depgraph_if ifc ); typedef ifc.pair_t pair_t; typedef ifc.half_t half_t; @@ -42,28 +40,22 @@ module a_mod( initial begin #1; - `checkd($bits(pair_t),24); + `checkd($bits(pair_t), 24); `checkd(p_a, 24); `checkd(p_b, 16); end endmodule -module t(); - localparam a_pkg::cfg_t cfg = '{ - a: 8 - }; +module t; + localparam a_pkg::cfg_t cfg = '{a: 8}; - depgraph_if #(cfg) ifc(); + depgraph_if #(cfg) ifc (); typedef ifc.byte_t byte_t; - a_mod #() a_mod_0( - .ifc(ifc) - ); + a_mod #() a_mod_0 (.ifc(ifc)); - localparam b_pkg::cfg_t cfg_b = '{ - a:$bits(byte_t) - }; + localparam b_pkg::cfg_t cfg_b = '{a: $bits(byte_t)}; initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_param_from_port.v b/test_regress/t/t_paramgraph_iface_param_from_port.v index a6f664b38..c5728ca6d 100644 --- a/test_regress/t/t_paramgraph_iface_param_from_port.v +++ b/test_regress/t/t_paramgraph_iface_param_from_port.v @@ -20,19 +20,27 @@ package cfg_pkg; } cfg_t; endpackage -interface types_if #(parameter cfg_pkg::cfg_t cfg = '0)(); +interface types_if #( + parameter cfg_pkg::cfg_t cfg = '0 +) (); typedef logic [cfg.DataWidth-1:0] data_t; typedef logic [cfg.IdWidth-1:0] id_t; endinterface -interface bus_if #(parameter cfg_pkg::cfg_t cfg = '0)(); - types_if #(cfg) types(); +interface bus_if #( + parameter cfg_pkg::cfg_t cfg = '0 +) (); + types_if #(cfg) types (); typedef types.data_t data_t; typedef types.id_t id_t; endinterface -module child(bus_if io, output int data_w, output int id_w); - types_if #(io.cfg) port_types(); +module child ( + bus_if io, + output int data_w, + output int id_w +); + types_if #(io.cfg) port_types (); typedef port_types.data_t p_data_t; typedef port_types.id_t p_id_t; assign data_w = $bits(p_data_t); @@ -40,19 +48,27 @@ module child(bus_if io, output int data_w, output int id_w); endmodule module top; - localparam cfg_pkg::cfg_t cfg0 = '{DataWidth:32, IdWidth:4}; - localparam cfg_pkg::cfg_t cfg1 = '{DataWidth:64, IdWidth:6}; + localparam cfg_pkg::cfg_t cfg0 = '{DataWidth: 32, IdWidth: 4}; + localparam cfg_pkg::cfg_t cfg1 = '{DataWidth: 64, IdWidth: 6}; - bus_if #(cfg0) bus0(); - bus_if #(cfg1) bus1(); + bus_if #(cfg0) bus0 (); + bus_if #(cfg1) bus1 (); int data_w0; int id_w0; int data_w1; int id_w1; - child u0(.io(bus0), .data_w(data_w0), .id_w(id_w0)); - child u1(.io(bus1), .data_w(data_w1), .id_w(id_w1)); + child u0 ( + .io(bus0), + .data_w(data_w0), + .id_w(id_w0) + ); + child u1 ( + .io(bus1), + .data_w(data_w1), + .id_w(id_w1) + ); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_pin.v b/test_regress/t/t_paramgraph_iface_pin.v index 7d1c3d6ab..94d4fe2ed 100644 --- a/test_regress/t/t_paramgraph_iface_pin.v +++ b/test_regress/t/t_paramgraph_iface_pin.v @@ -11,12 +11,12 @@ // verilog_format: on package a_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage -interface depgraph_if #(a_pkg::cfg_t cfg=0)(); +interface depgraph_if #( + a_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.a-1:0] byte_t; typedef logic [2*cfg.a-1:0] half_t; typedef struct packed { @@ -25,8 +25,8 @@ interface depgraph_if #(a_pkg::cfg_t cfg=0)(); } pair_t; endinterface -module a_mod( - depgraph_if ifc +module a_mod ( + depgraph_if ifc ); typedef ifc.byte_t byte_t; typedef ifc.pair_t pair_t; @@ -39,20 +39,16 @@ module a_mod( initial begin #1; `checkd($bits(byte_t), 8); - `checkd($bits(pair_t),24); + `checkd($bits(pair_t), 24); `checkd($bits(flat), 24); end endmodule -module t(); - localparam a_pkg::cfg_t cfg = '{ - a:8 - }; +module t; + localparam a_pkg::cfg_t cfg = '{a: 8}; - depgraph_if #(cfg) ifc(); - a_mod #() a_mod_0( - .ifc(ifc) - ); + depgraph_if #(cfg) ifc (); + a_mod #() a_mod_0 (.ifc(ifc)); initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_port_typedef.v b/test_regress/t/t_paramgraph_iface_port_typedef.v index 99d9050e8..34f1567f4 100644 --- a/test_regress/t/t_paramgraph_iface_port_typedef.v +++ b/test_regress/t/t_paramgraph_iface_port_typedef.v @@ -15,33 +15,42 @@ // verilog_format: on package acme_pkg; - typedef struct packed { - int DataBits; - } cfg_t; + typedef struct packed {int DataBits;} cfg_t; endpackage -interface acme_if #(parameter acme_pkg::cfg_t cfg = '0)(); +interface acme_if #( + parameter acme_pkg::cfg_t cfg = '0 +) (); typedef logic [cfg.DataBits-1:0] data_t; endinterface -module child(acme_if io, output int width_o); +module child ( + acme_if io, + output int width_o +); typedef io.data_t data_t; data_t payload; assign width_o = $bits(data_t); endmodule module top; - localparam acme_pkg::cfg_t cfg0 = '{DataBits:32}; - localparam acme_pkg::cfg_t cfg1 = '{DataBits:64}; + localparam acme_pkg::cfg_t cfg0 = '{DataBits: 32}; + localparam acme_pkg::cfg_t cfg1 = '{DataBits: 64}; - acme_if #(cfg0) io0(); - acme_if #(cfg1) io1(); + acme_if #(cfg0) io0 (); + acme_if #(cfg1) io1 (); int width0; int width1; - child u0(.io(io0), .width_o(width0)); - child u1(.io(io1), .width_o(width1)); + child u0 ( + .io(io0), + .width_o(width0) + ); + child u1 ( + .io(io1), + .width_o(width1) + ); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch.v b/test_regress/t/t_paramgraph_iface_template_mismatch.v index 92e39e58a..6c3ef397c 100644 --- a/test_regress/t/t_paramgraph_iface_template_mismatch.v +++ b/test_regress/t/t_paramgraph_iface_template_mismatch.v @@ -22,15 +22,17 @@ package axi4l; } cfg_t; endpackage -interface axi4l_if #(parameter axi4l::cfg_t cfg = '0)(); +interface axi4l_if #( + parameter axi4l::cfg_t cfg = '0 +) (); typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.DataBits/8-1:0] strb_t; typedef logic [cfg.UserBits-1:0] user_t; endinterface -module ccom_to_axi( - axi4l_if axil_tgt_io +module ccom_to_axi ( + axi4l_if axil_tgt_io ); typedef axil_tgt_io.addr_t addr_t; typedef axil_tgt_io.data_t data_t; @@ -41,21 +43,23 @@ module ccom_to_axi( strb_t strb_q; endmodule -module dummy_consumer(axi4l_if axil_io); +module dummy_consumer ( + axi4l_if axil_io +); typedef axil_io.data_t data_t; data_t sink; endmodule module top; - localparam axi4l::cfg_t cfg = '{AddrBits:32, DataBits:64, UserBits:2}; + localparam axi4l::cfg_t cfg = '{AddrBits: 32, DataBits: 64, UserBits: 2}; // Live specialized instance used elsewhere. - axi4l_if #(.cfg(cfg)) axil_live(); - dummy_consumer u_consume(.axil_io(axil_live)); + axi4l_if #(.cfg(cfg)) axil_live (); + dummy_consumer u_consume (.axil_io(axil_live)); // Template/default instance used in ccom_to_axi. - axi4l_if #(cfg) axil_tgt_io(); - ccom_to_axi u_ccom_to_axi(.axil_tgt_io(axil_tgt_io)); + axi4l_if #(cfg) axil_tgt_io (); + ccom_to_axi u_ccom_to_axi (.axil_tgt_io(axil_tgt_io)); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch2.v b/test_regress/t/t_paramgraph_iface_template_mismatch2.v index 394354d4a..8b7f08fe1 100644 --- a/test_regress/t/t_paramgraph_iface_template_mismatch2.v +++ b/test_regress/t/t_paramgraph_iface_template_mismatch2.v @@ -22,15 +22,17 @@ package axi4l; } cfg_t; endpackage -interface axi4l_if #(parameter axi4l::cfg_t cfg = '{AddrBits:4, DataBits:16, UserBits:1})(); +interface axi4l_if #( + parameter axi4l::cfg_t cfg = '{AddrBits: 4, DataBits: 16, UserBits: 1} +) (); typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.DataBits/8-1:0] strb_t; typedef logic [cfg.UserBits-1:0] user_t; endinterface -module ccom_to_axi( - axi4l_if axil_tgt_io +module ccom_to_axi ( + axi4l_if axil_tgt_io ); typedef axil_tgt_io.addr_t addr_t; typedef axil_tgt_io.data_t data_t; @@ -41,21 +43,23 @@ module ccom_to_axi( strb_t strb_q; endmodule -module dummy_consumer(axi4l_if axil_io); +module dummy_consumer ( + axi4l_if axil_io +); typedef axil_io.data_t data_t; data_t sink; endmodule module top; - localparam axi4l::cfg_t cfg = '{AddrBits:32, DataBits:64, UserBits:2}; + localparam axi4l::cfg_t cfg = '{AddrBits: 32, DataBits: 64, UserBits: 2}; // Live specialized instance used elsewhere. - axi4l_if #(.cfg(cfg)) axil_live(); - dummy_consumer u_consume(.axil_io(axil_live)); + axi4l_if #(.cfg(cfg)) axil_live (); + dummy_consumer u_consume (.axil_io(axil_live)); // Template/default instance used in ccom_to_axi. - axi4l_if #(cfg) axil_tgt_io(); - ccom_to_axi u_ccom_to_axi(.axil_tgt_io(axil_tgt_io)); + axi4l_if #(cfg) axil_tgt_io (); + ccom_to_axi u_ccom_to_axi (.axil_tgt_io(axil_tgt_io)); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch3.v b/test_regress/t/t_paramgraph_iface_template_mismatch3.v index 2ab9ca006..44fd55937 100644 --- a/test_regress/t/t_paramgraph_iface_template_mismatch3.v +++ b/test_regress/t/t_paramgraph_iface_template_mismatch3.v @@ -15,40 +15,42 @@ // verilog_format: on package axi4l; - typedef struct packed { - int DataBits; - } cfg_t; + typedef struct packed {int DataBits;} cfg_t; endpackage -interface axi4l_if #(parameter axi4l::cfg_t cfg = '0)(); +interface axi4l_if #( + parameter axi4l::cfg_t cfg = '0 +) (); typedef logic [cfg.DataBits-1:0] data_t; endinterface -module ccom_to_axi( - axi4l_if axil_tgt_io +module ccom_to_axi ( + axi4l_if axil_tgt_io ); typedef axil_tgt_io.data_t data_t; data_t data_q; endmodule -module dummy_consumer(axi4l_if axil_io); +module dummy_consumer ( + axi4l_if axil_io +); typedef axil_io.data_t data_t; data_t sink; endmodule module top; localparam axi4l::cfg_t cfg = '{ - DataBits:64//, + DataBits: 64 //, }; // Live specialized instance used elsewhere. - axi4l_if #(.cfg(cfg)) axil_live(); - dummy_consumer u_consume(.axil_io(axil_live)); + axi4l_if #(.cfg(cfg)) axil_live (); + dummy_consumer u_consume (.axil_io(axil_live)); // Template/default instance used in ccom_to_axi. - axi4l_if #(cfg) axil_tgt_io(); - ccom_to_axi u_ccom_to_axi(.axil_tgt_io(axil_tgt_io)); + axi4l_if #(cfg) axil_tgt_io (); + ccom_to_axi u_ccom_to_axi (.axil_tgt_io(axil_tgt_io)); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_template_nested.v b/test_regress/t/t_paramgraph_iface_template_nested.v index ea2c99090..eca496bc9 100644 --- a/test_regress/t/t_paramgraph_iface_template_nested.v +++ b/test_regress/t/t_paramgraph_iface_template_nested.v @@ -15,52 +15,56 @@ // verilog_format: on package acme_pkg; - typedef struct packed { - int DataBits; - } cfg_t; + typedef struct packed {int DataBits;} cfg_t; endpackage -interface acme_types_if #(parameter acme_pkg::cfg_t cfg = '0)(); +interface acme_types_if #( + parameter acme_pkg::cfg_t cfg = '0 +) (); typedef logic [cfg.DataBits-1:0] data_t; endinterface -interface acme_tb_if #(parameter acme_pkg::cfg_t cfg = '0)(); - acme_types_if #(cfg) acme_types(); +interface acme_tb_if #( + parameter acme_pkg::cfg_t cfg = '0 +) (); + acme_types_if #(cfg) acme_types (); typedef acme_types.data_t data_t; data_t payload; endinterface -interface acme_if #(parameter acme_pkg::cfg_t cfg = '0)(); - acme_tb_if #(cfg) rq_tb_io_i(); - acme_types_if #(cfg) acme_types(); +interface acme_if #( + parameter acme_pkg::cfg_t cfg = '0 +) (); + acme_tb_if #(cfg) rq_tb_io_i (); + acme_types_if #(cfg) acme_types (); typedef acme_types.data_t data_t; data_t passthru; endinterface -interface acme_wrap_if #(parameter acme_pkg::cfg_t cfg = '0)(); - acme_if #(cfg) acme_io(); +interface acme_wrap_if #( + parameter acme_pkg::cfg_t cfg = '0 +) (); + acme_if #(cfg) acme_io (); typedef acme_io.data_t data_t; data_t leaf; endinterface -module consumer(acme_wrap_if wrap_io); +module consumer ( + acme_wrap_if wrap_io +); typedef wrap_io.data_t data_t; data_t sink; endmodule module top; - localparam acme_pkg::cfg_t cfg0 = '{ - DataBits:64 - }; - localparam acme_pkg::cfg_t cfg1 = '{ - DataBits:128 - }; + localparam acme_pkg::cfg_t cfg0 = '{DataBits: 64}; + localparam acme_pkg::cfg_t cfg1 = '{DataBits: 128}; - acme_wrap_if #(cfg0) wrap0(); - acme_wrap_if #(cfg1) wrap1(); + acme_wrap_if #(cfg0) wrap0 (); + acme_wrap_if #(cfg1) wrap1 (); - consumer u_consume0(.wrap_io(wrap0)); - consumer u_consume1(.wrap_io(wrap1)); + consumer u_consume0 (.wrap_io(wrap0)); + consumer u_consume1 (.wrap_io(wrap1)); initial begin #1; diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v b/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v index 3ca551d2b..e9c5a2207 100644 --- a/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v @@ -14,7 +14,7 @@ interface depgraph_if; endinterface module t_paramgraph_member_refdtype_iface_chain; - depgraph_if ifc(); + depgraph_if ifc (); typedef ifc.byte_t byte_t; typedef byte_t byte_t2; diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v b/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v index f38a8a755..71c037c2c 100644 --- a/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v @@ -19,7 +19,7 @@ interface depgraph_if; endinterface module t_paramgraph_member_refdtype_iface_struct; - depgraph_if ifc(); + depgraph_if ifc (); typedef ifc.byte_t byte_t; typedef ifc.pair_t pair_t; diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v b/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v index dfd79a819..4e375c90b 100644 --- a/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v @@ -15,7 +15,7 @@ interface depgraph_if; endinterface module t_paramgraph_member_refdtype_iface_typedef; - depgraph_if ifc(); + depgraph_if ifc (); typedef ifc.byte_t byte_t; typedef struct packed { diff --git a/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v b/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v index 8297b7179..4b291cba9 100644 --- a/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v +++ b/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v @@ -11,12 +11,12 @@ // verilog_format: on package paramgraph_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage -interface paramgraph_if #(paramgraph_pkg::cfg_t cfg=0)(); +interface paramgraph_if #( + paramgraph_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.a-1:0] byte_t; typedef struct packed { byte_t a; @@ -25,11 +25,9 @@ interface paramgraph_if #(paramgraph_pkg::cfg_t cfg=0)(); endinterface module t_paramgraph_member_refdtype_pkg_iface; - localparam paramgraph_pkg::cfg_t cfg = '{ - a: 8 - }; + localparam paramgraph_pkg::cfg_t cfg = '{a: 8}; - paramgraph_if #(cfg) ifc(); + paramgraph_if #(cfg) ifc (); typedef ifc.byte_t byte_t; typedef ifc.pair_t pair_t; diff --git a/test_regress/t/t_paramgraph_minimal_sibling.v b/test_regress/t/t_paramgraph_minimal_sibling.v index e3d8cd042..87df13b20 100644 --- a/test_regress/t/t_paramgraph_minimal_sibling.v +++ b/test_regress/t/t_paramgraph_minimal_sibling.v @@ -12,19 +12,25 @@ // `define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkd(gotv, + expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // Parameterized interface with a typedef that depends on the parameter -interface a_if #(parameter int WIDTH = 8)(); - localparam LP_WIDTH = WIDTH*2; +interface a_if #( + parameter int WIDTH = 8 +) (); + localparam LP_WIDTH = WIDTH * 2; typedef logic [LP_WIDTH-1:0] data_t; data_t data; endinterface // Wrapper interface with TWO SIBLING instances of a_if with DIFFERENT widths -interface wrapper_if #(parameter int WIDTH_A = 8, parameter int WIDTH_B = 16)(); - a_if #(.WIDTH(WIDTH_A)) a_inst(); - a_if #(.WIDTH(WIDTH_B)) b_inst(); +interface wrapper_if #( + parameter int WIDTH_A = 8, + parameter int WIDTH_B = 16 +) (); + a_if #(.WIDTH(WIDTH_A)) a_inst (); + a_if #(.WIDTH(WIDTH_B)) b_inst (); // Re-export typedefs from each sibling typedef a_inst.data_t a_data_t; @@ -33,7 +39,7 @@ endinterface // Module that accesses typedefs from BOTH siblings via interface port module consumer ( - wrapper_if wif + wrapper_if wif ); // These MUST resolve to DIFFERENT types typedef wif.a_inst.data_t local_a_t; // Should be 10 bits @@ -50,9 +56,12 @@ module consumer ( endmodule // Top module -module t(); - wrapper_if #(.WIDTH_A(10), .WIDTH_B(20)) wif(); - consumer c(.wif(wif)); +module t; + wrapper_if #( + .WIDTH_A(10), + .WIDTH_B(20) + ) wif (); + consumer c (.wif(wif)); initial begin #2; diff --git a/test_regress/t/t_paramgraph_nested_iface_typedef.v b/test_regress/t/t_paramgraph_nested_iface_typedef.v index 77cf1ca1b..afe12a800 100644 --- a/test_regress/t/t_paramgraph_nested_iface_typedef.v +++ b/test_regress/t/t_paramgraph_nested_iface_typedef.v @@ -24,7 +24,9 @@ typedef struct packed { } axi_cfg_t; // Innermost interface - like axi4_if.sv in the real design -interface axi4_if #(parameter axi_cfg_t cfg = '{32, 64, 4, 0})(); +interface axi4_if #( + parameter axi_cfg_t cfg = '{32, 64, 4, 0} +) (); typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.IdBits-1:0] id_t; @@ -33,25 +35,27 @@ interface axi4_if #(parameter axi_cfg_t cfg = '{32, 64, 4, 0})(); // AXI channel typedef typedef struct packed { - id_t id; - addr_t addr; + id_t id; + addr_t addr; logic [7:0] len; } ar_chan_t; typedef struct packed { - id_t id; - data_t data; + id_t id; + data_t data; logic [1:0] resp; - logic last; + logic last; } r_chan_t; ar_chan_t ar; - r_chan_t r; + r_chan_t r; endinterface // Middle interface - wraps the AXI interface -interface tlb_io_if #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})(); - axi4_if #(.cfg(axi_cfg)) axi_tlb_io(); +interface tlb_io_if #( + parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0} +) (); + axi4_if #(.cfg(axi_cfg)) axi_tlb_io (); // Capture typedef from nested interface typedef axi_tlb_io.r_chan_t r_chan_t; @@ -59,8 +63,10 @@ interface tlb_io_if #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})(); endinterface // Outer interface - contains the middle interface -interface cca_io_if #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})(); - tlb_io_if #(.axi_cfg(axi_cfg)) tlb_io(); +interface cca_io_if #( + parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0} +) (); + tlb_io_if #(.axi_cfg(axi_cfg)) tlb_io (); // Capture typedef from doubly-nested interface typedef tlb_io.r_chan_t r_chan_t; @@ -68,8 +74,10 @@ interface cca_io_if #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})(); endinterface // Module that uses the doubly-nested typedef - this is where the error occurred -module cca_xbar #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})( - cca_io_if cca_io +module cca_xbar #( + parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0} +) ( + cca_io_if cca_io ); // This line was causing "Internal Error: Unlinked" before the fix // because cca_io.tlb_io.r_chan_t references a typedef from a nested interface @@ -92,17 +100,17 @@ module cca_xbar #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})( end endmodule -module t(); +module t; localparam axi_cfg_t cfg1 = '{AddrBits: 32, DataBits: 64, IdBits: 4, UserBits: 2}; localparam axi_cfg_t cfg2 = '{AddrBits: 40, DataBits: 128, IdBits: 8, UserBits: 4}; // Instantiate outer interface - cca_io_if #(.axi_cfg(cfg1)) cca_io1(); - cca_io_if #(.axi_cfg(cfg2)) cca_io2(); + cca_io_if #(.axi_cfg(cfg1)) cca_io1 (); + cca_io_if #(.axi_cfg(cfg2)) cca_io2 (); // Instantiate modules that use doubly-nested typedefs - cca_xbar #(.axi_cfg(cfg1)) xbar1(.cca_io(cca_io1)); - cca_xbar #(.axi_cfg(cfg2)) xbar2(.cca_io(cca_io2)); + cca_xbar #(.axi_cfg(cfg1)) xbar1 (.cca_io(cca_io1)); + cca_xbar #(.axi_cfg(cfg2)) xbar2 (.cca_io(cca_io2)); // Also test direct typedef access in top module typedef cca_io1.tlb_io.r_chan_t top_r_chan_t; diff --git a/test_regress/t/t_paramgraph_param_not_const.v b/test_regress/t/t_paramgraph_param_not_const.v index 51569f711..83cd922bb 100644 --- a/test_regress/t/t_paramgraph_param_not_const.v +++ b/test_regress/t/t_paramgraph_param_not_const.v @@ -32,7 +32,9 @@ package a_pkg; } cfg_t; endpackage -interface other_types_if #(parameter a_pkg::cfg_t cfg=0)(); +interface other_types_if #( + parameter a_pkg::cfg_t cfg = 0 +) (); // Create a struct that results in 525 bits typedef struct packed { logic [cfg.p_a-1:0] field1; @@ -42,7 +44,9 @@ interface other_types_if #(parameter a_pkg::cfg_t cfg=0)(); endinterface // Simple interface that takes a parameter -interface simple_if #(parameter cb::cfg_t cfg=0)(); +interface simple_if #( + parameter cb::cfg_t cfg = 0 +) (); logic [cfg.Rids-1:0] rids; logic [cfg.Pids-1:0] pids; logic [cfg.Fnum-1:0] fnum; @@ -50,25 +54,22 @@ interface simple_if #(parameter cb::cfg_t cfg=0)(); endinterface module TestMod; - localparam a_pkg::cfg_t ot_cfg = '{ - p_a : 8, - p_b : 4 - }; + localparam a_pkg::cfg_t ot_cfg = '{p_a : 8, p_b : 4}; - other_types_if #(ot_cfg) other_types(); + other_types_if #(ot_cfg) other_types (); typedef other_types.cmd_beat_t cmd_beat_t; // This pattern assignment should work correctly localparam cb::cfg_t cb_cfg = '{ - Rids : 32'h1, - Pids : 32'h2, - Fnum : 32'h3, - XdatSize : $bits(cmd_beat_t) + Rids : 32'h1, + Pids : 32'h2, + Fnum : 32'h3, + XdatSize : $bits(cmd_beat_t) }; // This should trigger the error - cb_cfg is not recognized as constant - simple_if#(cb_cfg) cb_vc0_io(); + simple_if #(cb_cfg) cb_vc0_io (); initial begin `checkd(cb_cfg.XdatSize, 12); diff --git a/test_regress/t/t_paramgraph_paramtype_default.v b/test_regress/t/t_paramgraph_paramtype_default.v index 8e4bf9ec5..bb4842e49 100644 --- a/test_regress/t/t_paramgraph_paramtype_default.v +++ b/test_regress/t/t_paramgraph_paramtype_default.v @@ -12,17 +12,20 @@ // // Simple type flop - parameterized by type T with default = logic -module tflop #(parameter type T = logic) ( - input logic clk, - input logic reset, - input T reset_strap_i, - output T q_o, - input T d_i +module tflop #( + parameter type T = logic +) ( + input logic clk, + input logic reset, + input T reset_strap_i, + output T q_o, + input T d_i ); always_ff @(posedge clk) begin if (reset) begin q_o <= reset_strap_i; - end else begin + end + else begin q_o <= d_i; end end @@ -30,19 +33,19 @@ endmodule // Module that uses tflop with DEFAULT type parameter (T = logic) module user_mod ( - input logic clk, - input logic reset + input logic clk, + input logic reset ); logic d_in, d_out; // Use tflop with default type parameter T = logic // This should NOT create a specialized clone - it reuses the template tflop vld_reg ( - .clk(clk), - .reset(reset), - .reset_strap_i(1'b0), - .q_o(d_out), - .d_i(d_in) + .clk(clk), + .reset(reset), + .reset_strap_i(1'b0), + .q_o(d_out), + .d_i(d_in) ); initial begin @@ -58,7 +61,10 @@ module t; logic clk = 0; logic reset = 1; - user_mod uut (.clk(clk), .reset(reset)); + user_mod uut ( + .clk(clk), + .reset(reset) + ); initial begin #5 reset = 0; diff --git a/test_regress/t/t_paramgraph_refdtype_iface.v b/test_regress/t/t_paramgraph_refdtype_iface.v index 0577c5b43..753988a41 100644 --- a/test_regress/t/t_paramgraph_refdtype_iface.v +++ b/test_regress/t/t_paramgraph_refdtype_iface.v @@ -19,7 +19,7 @@ interface depgraph_if; endinterface module depgraph_top; - depgraph_if ifc(); + depgraph_if ifc (); typedef ifc.nibble_t nibble_t; diff --git a/test_regress/t/t_paramgraph_refdtype_unlinked.v b/test_regress/t/t_paramgraph_refdtype_unlinked.v index b490eaa41..2056b5a01 100644 --- a/test_regress/t/t_paramgraph_refdtype_unlinked.v +++ b/test_regress/t/t_paramgraph_refdtype_unlinked.v @@ -18,7 +18,9 @@ package Include; typedef logic [11:0] mbox_addr_t; endpackage -interface mbox_if #(parameter int WIDTH = 0); +interface mbox_if #( + parameter int WIDTH = 0 +); typedef Include::mbox_addr_t mbox_addr_t; typedef struct packed { @@ -27,8 +29,10 @@ interface mbox_if #(parameter int WIDTH = 0); } RFTag; endinterface -module mbox #(parameter int WIDTH = 0); - mbox_if #(WIDTH) if_inst(); +module mbox #( + parameter int WIDTH = 0 +); + mbox_if #(WIDTH) if_inst (); // This should reproduce the REFDTYPE UNLINKED error // Using a type cast of an interface typedef in a parameter @@ -42,5 +46,5 @@ module mbox #(parameter int WIDTH = 0); endmodule module top; - mbox #(.WIDTH(14)) u_mbox(); + mbox #(.WIDTH(14)) u_mbox (); endmodule diff --git a/test_regress/t/t_paramgraph_selbit_dtype.v b/test_regress/t/t_paramgraph_selbit_dtype.v index 971a172ea..d47b5606f 100644 --- a/test_regress/t/t_paramgraph_selbit_dtype.v +++ b/test_regress/t/t_paramgraph_selbit_dtype.v @@ -12,13 +12,13 @@ // Spill register with type parameter (simplified from spill_register_flushable) module spill_register #( - parameter type T = logic + parameter type T = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic sel_i, - input T data_i, - output T data_o + input logic clk_i, + input logic rst_ni, + input logic sel_i, + input T data_i, + output T data_o ); // Two registers of type T T a_data_q; @@ -26,15 +26,16 @@ module spill_register #( logic b_full_q; always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - a_data_q <= '0; - b_data_q <= '0; - b_full_q <= 1'b0; - end else begin - a_data_q <= data_i; - b_data_q <= a_data_q; - b_full_q <= sel_i; - end + if (!rst_ni) begin + a_data_q <= '0; + b_data_q <= '0; + b_full_q <= 1'b0; + end + else begin + a_data_q <= data_i; + b_data_q <= a_data_q; + b_full_q <= sel_i; + end end // This is the problematic line - ternary expression with type parameter variables @@ -44,41 +45,45 @@ endmodule // Wrapper module that passes type parameter through (like spill_register_flushable wrapper) module spill_wrapper #( - parameter type T = logic + parameter type T = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic sel_i, - input T data_i, - output T data_o + input logic clk_i, + input logic rst_ni, + input logic sel_i, + input T data_i, + output T data_o ); // Instantiate spill_register with the same type parameter - spill_register #(.T(T)) i_spill ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .sel_i(sel_i), - .data_i(data_i), - .data_o(data_o) + spill_register #( + .T(T) + ) i_spill ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .sel_i(sel_i), + .data_i(data_i), + .data_o(data_o) ); endmodule // Another level of nesting (like axi_demux) module demux #( - parameter type T = logic + parameter type T = logic ) ( - input logic clk_i, - input logic rst_ni + input logic clk_i, + input logic rst_ni ); logic sel; T data_in; T data_out; - spill_wrapper #(.T(T)) i_spill_wrapper ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .sel_i(sel), - .data_i(data_in), - .data_o(data_out) + spill_wrapper #( + .T(T) + ) i_spill_wrapper ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .sel_i(sel), + .data_i(data_in), + .data_o(data_out) ); endmodule @@ -87,9 +92,11 @@ module top; logic rst_n; // Instantiate with default T (logic) - demux #(.T(logic)) u_demux ( - .clk_i(clk), - .rst_ni(rst_n) + demux #( + .T(logic) + ) u_demux ( + .clk_i(clk), + .rst_ni(rst_n) ); initial begin diff --git a/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v b/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v index 8e9d7d6a3..bb44797d9 100644 --- a/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v +++ b/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v @@ -27,8 +27,8 @@ package cache_pkg; endpackage interface cache_types_if #( - parameter cache_pkg::cfg_t cfg = '0 -)(); + parameter cache_pkg::cfg_t cfg = '0 +) (); localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); @@ -41,14 +41,18 @@ interface cache_types_if #( endinterface interface cache_if #( - parameter cache_pkg::cfg_t cfg = '0 -)(); - cache_types_if #(cfg) types(); + parameter cache_pkg::cfg_t cfg = '0 +) (); + cache_types_if #(cfg) types (); typedef types.tag_t tag_t; typedef types.drow_addr_t drow_addr_t; endinterface -module cache_leaf(cache_if io, output int tag_bits_o, output int drow_bits_o); +module cache_leaf ( + cache_if io, + output int tag_bits_o, + output int drow_bits_o +); typedef io.tag_t tag_t; typedef io.drow_addr_t drow_addr_t; assign tag_bits_o = $bits(tag_t); @@ -56,31 +60,48 @@ module cache_leaf(cache_if io, output int tag_bits_o, output int drow_bits_o); endmodule module cache_wrap #( - parameter cache_pkg::cfg_t cfg = '0 -)(output int tag_bits_o, output int drow_bits_o); + parameter cache_pkg::cfg_t cfg = '0 +) ( + output int tag_bits_o, + output int drow_bits_o +); localparam cache_pkg::cfg_t sc_cfg = '{ - CmdTagBits : $clog2(cfg.Capacity), - Associativity : cfg.Associativity, - Capacity : cfg.Capacity, - LineSize : cfg.LineSize, - AddrBits : cfg.AddrBits, - FgWidth : cfg.FgWidth, - MissQSize : cfg.MissQSize + CmdTagBits : $clog2(cfg.Capacity), + Associativity : cfg.Associativity, + Capacity : cfg.Capacity, + LineSize : cfg.LineSize, + AddrBits : cfg.AddrBits, + FgWidth : cfg.FgWidth, + MissQSize : cfg.MissQSize }; - cache_if #(sc_cfg) sc_io(); + cache_if #(sc_cfg) sc_io (); - cache_leaf u_leaf(.io(sc_io), .tag_bits_o(tag_bits_o), .drow_bits_o(drow_bits_o)); + cache_leaf u_leaf ( + .io(sc_io), + .tag_bits_o(tag_bits_o), + .drow_bits_o(drow_bits_o) + ); endmodule module top; localparam cache_pkg::cfg_t cfg0 = '{ - Capacity:1024, LineSize:64, Associativity:4, AddrBits:32, - FgWidth:32, MissQSize:8, CmdTagBits:0 + Capacity: 1024, + LineSize: 64, + Associativity: 4, + AddrBits: 32, + FgWidth: 32, + MissQSize: 8, + CmdTagBits: 0 }; localparam cache_pkg::cfg_t cfg1 = '{ - Capacity:2048, LineSize:32, Associativity:2, AddrBits:36, - FgWidth:16, MissQSize:16, CmdTagBits:0 + Capacity: 2048, + LineSize: 32, + Associativity: 2, + AddrBits: 36, + FgWidth: 16, + MissQSize: 16, + CmdTagBits: 0 }; int tag_bits0; @@ -88,8 +109,14 @@ module top; int tag_bits1; int drow_bits1; - cache_wrap #(cfg0) wrap0(.tag_bits_o(tag_bits0), .drow_bits_o(drow_bits0)); - cache_wrap #(cfg1) wrap1(.tag_bits_o(tag_bits1), .drow_bits_o(drow_bits1)); + cache_wrap #(cfg0) wrap0 ( + .tag_bits_o(tag_bits0), + .drow_bits_o(drow_bits0) + ); + cache_wrap #(cfg1) wrap1 ( + .tag_bits_o(tag_bits1), + .drow_bits_o(drow_bits1) + ); initial begin #1; diff --git a/test_regress/t/t_paramgraph_simple_cache_types_if.v b/test_regress/t/t_paramgraph_simple_cache_types_if.v index 7dff2292f..2370f4256 100644 --- a/test_regress/t/t_paramgraph_simple_cache_types_if.v +++ b/test_regress/t/t_paramgraph_simple_cache_types_if.v @@ -28,8 +28,8 @@ package sc_pkg; endpackage interface simple_cache_types_if #( - parameter sc_pkg::cfg_t cfg = '0 -)(); + parameter sc_pkg::cfg_t cfg = '0 +) (); localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); @@ -57,7 +57,12 @@ interface simple_cache_types_if #( } sc_tag_addr_t; endinterface -module child(simple_cache_types_if types, output int tag_bits_o, output int tag_addr_bits_o, output int drow_bits_o); +module child ( + simple_cache_types_if types, + output int tag_bits_o, + output int tag_addr_bits_o, + output int drow_bits_o +); typedef types.tag_t tag_t; typedef types.sc_tag_addr_t sc_tag_addr_t; typedef types.drow_addr_t drow_addr_t; @@ -68,16 +73,28 @@ endmodule module top; localparam sc_pkg::cfg_t cfg0 = '{ - Capacity:1024, LineSize:64, Associativity:4, AddrBits:32, - FgWidth:32, StateBits:2, CmdTagBits:5, MissQSize:8 + Capacity: 1024, + LineSize: 64, + Associativity: 4, + AddrBits: 32, + FgWidth: 32, + StateBits: 2, + CmdTagBits: 5, + MissQSize: 8 }; localparam sc_pkg::cfg_t cfg1 = '{ - Capacity:2048, LineSize:32, Associativity:2, AddrBits:36, - FgWidth:16, StateBits:3, CmdTagBits:7, MissQSize:16 + Capacity: 2048, + LineSize: 32, + Associativity: 2, + AddrBits: 36, + FgWidth: 16, + StateBits: 3, + CmdTagBits: 7, + MissQSize: 16 }; - simple_cache_types_if #(cfg0) types0(); - simple_cache_types_if #(cfg1) types1(); + simple_cache_types_if #(cfg0) types0 (); + simple_cache_types_if #(cfg1) types1 (); int tag_bits0; int tag_addr_bits0; @@ -86,10 +103,18 @@ module top; int tag_addr_bits1; int drow_bits1; - child u0(.types(types0), .tag_bits_o(tag_bits0), .tag_addr_bits_o(tag_addr_bits0), - .drow_bits_o(drow_bits0)); - child u1(.types(types1), .tag_bits_o(tag_bits1), .tag_addr_bits_o(tag_addr_bits1), - .drow_bits_o(drow_bits1)); + child u0 ( + .types(types0), + .tag_bits_o(tag_bits0), + .tag_addr_bits_o(tag_addr_bits0), + .drow_bits_o(drow_bits0) + ); + child u1 ( + .types(types1), + .tag_bits_o(tag_bits1), + .tag_addr_bits_o(tag_addr_bits1), + .drow_bits_o(drow_bits1) + ); initial begin #1; diff --git a/test_regress/t/t_pp_lib.v b/test_regress/t/t_pp_lib.v index ff79fa89d..c21188b58 100644 --- a/test_regress/t/t_pp_lib.v +++ b/test_regress/t/t_pp_lib.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 `include "t_pp_lib_inc.vh" -module t(); +module t; wire [`WIDTH-1:0] a; library_cell n1(a); endmodule diff --git a/test_regress/t/t_preproc_str_undef.v b/test_regress/t/t_preproc_str_undef.v index ef072b9b2..5910ed3cb 100644 --- a/test_regress/t/t_preproc_str_undef.v +++ b/test_regress/t/t_preproc_str_undef.v @@ -12,7 +12,7 @@ `define name3(p) ```p``_SUFFIX `define stringify(text) `"text`" -module t(); +module t; initial begin // Another simulator gives: // `PREFIX_my_suffix diff --git a/test_regress/t/t_process_propagation.v b/test_regress/t/t_process_propagation.v index 169649f36..256456a14 100644 --- a/test_regress/t/t_process_propagation.v +++ b/test_regress/t/t_process_propagation.v @@ -33,7 +33,7 @@ class Bar extends Foo; endtask endclass -module t(); +module t; initial begin process p; Foo foo; diff --git a/test_regress/t/t_process_task.v b/test_regress/t/t_process_task.v index 9e7d41ad3..1ba02cf41 100644 --- a/test_regress/t/t_process_task.v +++ b/test_regress/t/t_process_task.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; std::process proc; logic clk = 0; logic b = 0; diff --git a/test_regress/t/t_public_clk.v b/test_regress/t/t_public_clk.v index bef8056e0..cd40d635f 100644 --- a/test_regress/t/t_public_clk.v +++ b/test_regress/t/t_public_clk.v @@ -12,7 +12,7 @@ `define IMPURE_ONE (|($random | $random)) `endif -module t (); +module t; logic clk /* verilator public_flat_rw */; int count; diff --git a/test_regress/t/t_queue_insert_at_end.v b/test_regress/t/t_queue_insert_at_end.v index 9e21d4264..d65582b92 100644 --- a/test_regress/t/t_queue_insert_at_end.v +++ b/test_regress/t/t_queue_insert_at_end.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; initial begin int queue[$]; diff --git a/test_regress/t/t_randomize_std_static.v b/test_regress/t/t_randomize_std_static.v index 7d56ac592..5077fa4cf 100644 --- a/test_regress/t/t_randomize_std_static.v +++ b/test_regress/t/t_randomize_std_static.v @@ -34,9 +34,7 @@ module t; static function instr_name_t get_rand_instr(); instr_name_t name; int ok; - ok = std::randomize(name) with { - name inside {allowed_instrs}; - }; + ok = std::randomize(name) with {name inside {allowed_instrs};}; `checkd(ok, 1); return name; endfunction @@ -49,8 +47,9 @@ module t; repeat (20) begin result = instr_base::get_rand_instr(); - `checkd(result == INSTR_ADD || result == INSTR_SUB - || result == INSTR_MUL || result == INSTR_AND, 1); + `checkd( + result == INSTR_ADD || result == INSTR_SUB || result == INSTR_MUL || result == INSTR_AND, + 1); end $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_real_param.v b/test_regress/t/t_real_param.v index 8927b2436..0f86b3b3b 100644 --- a/test_regress/t/t_real_param.v +++ b/test_regress/t/t_real_param.v @@ -9,7 +9,7 @@ module foo (); endmodule -module t(); +module t; genvar m, r; generate for (m = 10; m <= 20; m+=10) begin : gen_m diff --git a/test_regress/t/t_recursive_typedef_bad.v b/test_regress/t/t_recursive_typedef_bad.v index 35811eedc..4b9f08023 100644 --- a/test_regress/t/t_recursive_typedef_bad.v +++ b/test_regress/t/t_recursive_typedef_bad.v @@ -18,7 +18,7 @@ module circ #( assign bo = ai; endmodule -module t (); +module t; logic [7:0] x, y; circ u_circ ( .ai(x), diff --git a/test_regress/t/t_select_bound3.v b/test_regress/t/t_select_bound3.v index 6cb8f05ad..8793aaa29 100644 --- a/test_regress/t/t_select_bound3.v +++ b/test_regress/t/t_select_bound3.v @@ -10,7 +10,7 @@ class cls; int m_field; endclass -module t(); +module t; cls inst[2]; initial begin diff --git a/test_regress/t/t_selrange_iface_type_param.v b/test_regress/t/t_selrange_iface_type_param.v index b9fd18340..a65dcb05b 100644 --- a/test_regress/t/t_selrange_iface_type_param.v +++ b/test_regress/t/t_selrange_iface_type_param.v @@ -30,13 +30,15 @@ package cfg_pkg; endpackage // Parameterized interface (like axi4_if) -interface my_if #(parameter cfg_pkg::cfg_t cfg = 0); - typedef logic [cfg.IdBits-1:0] id_t; - typedef logic [cfg.DataBits-1:0] data_t; +interface my_if #( + parameter cfg_pkg::cfg_t cfg = 0 +); + typedef logic [cfg.IdBits-1:0] id_t; + typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.DataBits/8-1:0] strb_t; typedef struct packed { - id_t id; + id_t id; data_t data; logic [7:0] len; logic [2:0] size; @@ -46,16 +48,16 @@ interface my_if #(parameter cfg_pkg::cfg_t cfg = 0); typedef struct packed { data_t data; strb_t strb; - logic last; + logic last; } w_chan_t; typedef struct packed { - id_t id; + id_t id; logic [1:0] resp; } b_chan_t; typedef struct packed { - id_t id; + id_t id; data_t data; logic [7:0] len; logic [2:0] size; @@ -63,33 +65,33 @@ interface my_if #(parameter cfg_pkg::cfg_t cfg = 0); } ar_chan_t; typedef struct packed { - id_t id; - data_t data; + id_t id; + data_t data; logic [1:0] resp; - logic last; + logic last; } r_chan_t; typedef struct packed { aw_chan_t aw; - logic aw_valid; - w_chan_t w; - logic w_valid; - logic b_ready; + logic aw_valid; + w_chan_t w; + logic w_valid; + logic b_ready; ar_chan_t ar; - logic ar_valid; - logic r_ready; + logic ar_valid; + logic r_ready; } req_t; typedef struct packed { - logic aw_ready; - logic w_ready; - b_chan_t b; - logic b_valid; - r_chan_t r; - logic r_valid; + logic aw_ready; + logic w_ready; + b_chan_t b; + logic b_valid; + r_chan_t r; + logic r_valid; } resp_t; - req_t req; + req_t req; resp_t resp; modport target(input req, output resp); @@ -100,17 +102,17 @@ endinterface // Leaf: axi_demux_simple skeleton //====================================================================== module axi_demux_simple #( - parameter int unsigned AxiIdWidth = 32'd0, - parameter type axi_req_t = logic, - parameter type axi_resp_t = logic, - parameter int unsigned AxiLookBits = 32'd3 -)( - input logic clk_i, - input logic rst_ni, - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, - output logic [AxiLookBits-1:0] id_out, - output int unsigned req_bits_out + parameter int unsigned AxiIdWidth = 32'd0, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, + parameter int unsigned AxiLookBits = 32'd3 +) ( + input logic clk_i, + input logic rst_ni, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + output logic [AxiLookBits-1:0] id_out, + output int unsigned req_bits_out ); // Extract ID from nested struct - triggers SELRANGE if axi_req_t // is from wrong interface clone (id field narrower than AxiLookBits) @@ -124,37 +126,37 @@ endmodule // axi_demux skeleton //====================================================================== module axi_demux #( - parameter int unsigned AxiIdWidth = 32'd0, - parameter type aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type r_chan_t = logic, - parameter type axi_req_t = logic, - parameter type axi_resp_t = logic, - parameter int unsigned NoMstPorts = 32'd0, - parameter int unsigned MaxTrans = 32'd8, - parameter int unsigned AxiLookBits = 32'd3 -)( - input logic clk_i, - input logic rst_ni, - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, - output logic [AxiLookBits-1:0] id_out, - output int unsigned req_bits_out + parameter int unsigned AxiIdWidth = 32'd0, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, + parameter int unsigned NoMstPorts = 32'd0, + parameter int unsigned MaxTrans = 32'd8, + parameter int unsigned AxiLookBits = 32'd3 +) ( + input logic clk_i, + input logic rst_ni, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + output logic [AxiLookBits-1:0] id_out, + output int unsigned req_bits_out ); axi_demux_simple #( - .AxiIdWidth ( AxiIdWidth ), - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), - .AxiLookBits ( AxiLookBits ) + .AxiIdWidth(AxiIdWidth), + .axi_req_t(axi_req_t), + .axi_resp_t(axi_resp_t), + .AxiLookBits(AxiLookBits) ) i_demux_simple ( - .clk_i, - .rst_ni, - .slv_req_i, - .slv_resp_o, - .id_out, - .req_bits_out + .clk_i, + .rst_ni, + .slv_req_i, + .slv_resp_o, + .id_out, + .req_bits_out ); endmodule @@ -162,56 +164,77 @@ endmodule // axi_burst_splitter skeleton //====================================================================== module axi_burst_splitter #( - parameter int unsigned AddrWidth = 32'd0, - parameter int unsigned DataWidth = 32'd0, - parameter int unsigned IdWidth = 32'd0, - parameter int unsigned UserWidth = 32'd0, - parameter type axi_req_t = logic, - parameter type axi_resp_t = logic -)( - input logic clk_i, - input logic rst_ni, - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, - output logic [IdWidth-1:0] id_out + parameter int unsigned AddrWidth = 32'd0, + parameter int unsigned DataWidth = 32'd0, + parameter int unsigned IdWidth = 32'd0, + parameter int unsigned UserWidth = 32'd0, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + output logic [IdWidth-1:0] id_out ); - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [IdWidth-1:0] id_t; + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [IdWidth-1:0] id_t; typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; + typedef logic [UserWidth-1:0] user_t; typedef struct packed { - id_t id; + id_t id; addr_t addr; logic [7:0] len; logic [2:0] size; logic [1:0] burst; } local_aw_chan_t; - typedef struct packed { data_t data; strb_t strb; logic last; } local_w_chan_t; - typedef struct packed { id_t id; logic [1:0] resp; } local_b_chan_t; - typedef struct packed { id_t id; addr_t addr; logic [7:0] len; logic [2:0] size; logic [1:0] burst; } local_ar_chan_t; - typedef struct packed { id_t id; data_t data; logic [1:0] resp; logic last; } local_r_chan_t; + typedef struct packed { + data_t data; + strb_t strb; + logic last; + } local_w_chan_t; + typedef struct packed { + id_t id; + logic [1:0] resp; + } local_b_chan_t; + typedef struct packed { + id_t id; + addr_t addr; + logic [7:0] len; + logic [2:0] size; + logic [1:0] burst; + } local_ar_chan_t; + typedef struct packed { + id_t id; + data_t data; + logic [1:0] resp; + logic last; + } local_r_chan_t; int unsigned req_bits_out; axi_demux #( - .AxiIdWidth ( IdWidth ), - .aw_chan_t ( local_aw_chan_t ), - .w_chan_t ( local_w_chan_t ), - .b_chan_t ( local_b_chan_t ), - .ar_chan_t ( local_ar_chan_t ), - .r_chan_t ( local_r_chan_t ), - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), - .NoMstPorts ( 2 ), - .MaxTrans ( 4 ), - .AxiLookBits ( IdWidth ) + .AxiIdWidth(IdWidth), + .aw_chan_t(local_aw_chan_t), + .w_chan_t(local_w_chan_t), + .b_chan_t(local_b_chan_t), + .ar_chan_t(local_ar_chan_t), + .r_chan_t(local_r_chan_t), + .axi_req_t(axi_req_t), + .axi_resp_t(axi_resp_t), + .NoMstPorts(2), + .MaxTrans(4), + .AxiLookBits(IdWidth) ) i_demux ( - .clk_i, .rst_ni, - .slv_req_i, .slv_resp_o, .id_out, - .req_bits_out + .clk_i, + .rst_ni, + .slv_req_i, + .slv_resp_o, + .id_out, + .req_bits_out ); endmodule @@ -219,28 +242,28 @@ endmodule // axi_dw_upsizer skeleton //====================================================================== module axi_dw_upsizer #( - parameter int unsigned AxiIdWidth = 1, - parameter int unsigned AxiAddrWidth = 1, - parameter type aw_chan_t = logic, - parameter type mst_w_chan_t = logic, - parameter type slv_w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type mst_r_chan_t = logic, - parameter type slv_r_chan_t = logic, - parameter type axi_mst_req_t = logic, - parameter type axi_mst_resp_t = logic, - parameter type axi_slv_req_t = logic, - parameter type axi_slv_resp_t = logic -)( - input logic clk_i, - input logic rst_ni, - input axi_slv_req_t slv_req_i, - output axi_slv_resp_t slv_resp_o, - output axi_mst_req_t mst_req_o, - input axi_mst_resp_t mst_resp_i + parameter int unsigned AxiIdWidth = 1, + parameter int unsigned AxiAddrWidth = 1, + parameter type aw_chan_t = logic, + parameter type mst_w_chan_t = logic, + parameter type slv_w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type mst_r_chan_t = logic, + parameter type slv_r_chan_t = logic, + parameter type axi_mst_req_t = logic, + parameter type axi_mst_resp_t = logic, + parameter type axi_slv_req_t = logic, + parameter type axi_slv_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input axi_slv_req_t slv_req_i, + output axi_slv_resp_t slv_resp_o, + output axi_mst_req_t mst_req_o, + input axi_mst_resp_t mst_resp_i ); - axi_mst_req_t mst_req; + axi_mst_req_t mst_req; axi_mst_resp_t mst_resp; logic [AxiIdWidth-1:0] id_out; int unsigned req_bits_out; @@ -250,23 +273,24 @@ module axi_dw_upsizer #( assign mst_req_o = mst_req; axi_demux #( - .AxiIdWidth ( AxiIdWidth ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( mst_w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( mst_r_chan_t ), - .axi_req_t ( axi_mst_req_t ), - .axi_resp_t ( axi_mst_resp_t ), - .NoMstPorts ( 2 ), - .MaxTrans ( 4 ), - .AxiLookBits ( AxiIdWidth ) + .AxiIdWidth(AxiIdWidth), + .aw_chan_t(aw_chan_t), + .w_chan_t(mst_w_chan_t), + .b_chan_t(b_chan_t), + .ar_chan_t(ar_chan_t), + .r_chan_t(mst_r_chan_t), + .axi_req_t(axi_mst_req_t), + .axi_resp_t(axi_mst_resp_t), + .NoMstPorts(2), + .MaxTrans(4), + .AxiLookBits(AxiIdWidth) ) i_axi_demux ( - .clk_i, .rst_ni, - .slv_req_i ( mst_req ), - .slv_resp_o ( mst_resp ), - .id_out, - .req_bits_out + .clk_i, + .rst_ni, + .slv_req_i(mst_req), + .slv_resp_o(mst_resp), + .id_out, + .req_bits_out ); endmodule @@ -274,53 +298,56 @@ endmodule // axi_dw_converter skeleton - generate if for upsize //====================================================================== module axi_dw_converter #( - parameter int unsigned AxiSlvPortDataWidth = 8, - parameter int unsigned AxiMstPortDataWidth = 8, - parameter int unsigned AxiAddrWidth = 1, - parameter int unsigned AxiIdWidth = 1, - parameter type aw_chan_t = logic, - parameter type mst_w_chan_t = logic, - parameter type slv_w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type mst_r_chan_t = logic, - parameter type slv_r_chan_t = logic, - parameter type axi_mst_req_t = logic, - parameter type axi_mst_resp_t = logic, - parameter type axi_slv_req_t = logic, - parameter type axi_slv_resp_t = logic -)( - input logic clk_i, - input logic rst_ni, - input axi_slv_req_t slv_req_i, - output axi_slv_resp_t slv_resp_o, - output axi_mst_req_t mst_req_o, - input axi_mst_resp_t mst_resp_i + parameter int unsigned AxiSlvPortDataWidth = 8, + parameter int unsigned AxiMstPortDataWidth = 8, + parameter int unsigned AxiAddrWidth = 1, + parameter int unsigned AxiIdWidth = 1, + parameter type aw_chan_t = logic, + parameter type mst_w_chan_t = logic, + parameter type slv_w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type mst_r_chan_t = logic, + parameter type slv_r_chan_t = logic, + parameter type axi_mst_req_t = logic, + parameter type axi_mst_resp_t = logic, + parameter type axi_slv_req_t = logic, + parameter type axi_slv_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input axi_slv_req_t slv_req_i, + output axi_slv_resp_t slv_resp_o, + output axi_mst_req_t mst_req_o, + input axi_mst_resp_t mst_resp_i ); if (AxiMstPortDataWidth == AxiSlvPortDataWidth) begin : gen_no_dw_conversion - assign mst_req_o = slv_req_i; + assign mst_req_o = slv_req_i; assign slv_resp_o = mst_resp_i; end if (AxiMstPortDataWidth > AxiSlvPortDataWidth) begin : gen_dw_upsize axi_dw_upsizer #( - .AxiAddrWidth ( AxiAddrWidth ), - .AxiIdWidth ( AxiIdWidth ), - .aw_chan_t ( aw_chan_t ), - .mst_w_chan_t ( mst_w_chan_t ), - .slv_w_chan_t ( slv_w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .mst_r_chan_t ( mst_r_chan_t ), - .slv_r_chan_t ( slv_r_chan_t ), - .axi_mst_req_t ( axi_mst_req_t ), - .axi_mst_resp_t ( axi_mst_resp_t ), - .axi_slv_req_t ( axi_slv_req_t ), - .axi_slv_resp_t ( axi_slv_resp_t ) + .AxiAddrWidth(AxiAddrWidth), + .AxiIdWidth(AxiIdWidth), + .aw_chan_t(aw_chan_t), + .mst_w_chan_t(mst_w_chan_t), + .slv_w_chan_t(slv_w_chan_t), + .b_chan_t(b_chan_t), + .ar_chan_t(ar_chan_t), + .mst_r_chan_t(mst_r_chan_t), + .slv_r_chan_t(slv_r_chan_t), + .axi_mst_req_t(axi_mst_req_t), + .axi_mst_resp_t(axi_mst_resp_t), + .axi_slv_req_t(axi_slv_req_t), + .axi_slv_resp_t(axi_slv_resp_t) ) i_axi_dw_upsizer ( - .clk_i, .rst_ni, - .slv_req_i, .slv_resp_o, - .mst_req_o, .mst_resp_i + .clk_i, + .rst_ni, + .slv_req_i, + .slv_resp_o, + .mst_req_o, + .mst_resp_i ); end @@ -328,7 +355,8 @@ module axi_dw_converter #( int unsigned mst_req_bits; if (AxiMstPortDataWidth > AxiSlvPortDataWidth) begin : gen_bits_up assign mst_req_bits = gen_dw_upsize.i_axi_dw_upsizer.req_bits_out; - end else begin : gen_bits_eq + end + else begin : gen_bits_eq assign mst_req_bits = 0; end endmodule @@ -337,29 +365,32 @@ endmodule // axi_to_axi_lite skeleton //====================================================================== module axi_to_axi_lite #( - parameter int unsigned AxiAddrWidth = 32'd0, - parameter int unsigned AxiDataWidth = 32'd0, - parameter int unsigned AxiIdWidth = 32'd0, - parameter int unsigned AxiUserWidth = 32'd0, - parameter type full_req_t = logic, - parameter type full_resp_t = logic -)( - input logic clk_i, - input logic rst_ni, - input full_req_t slv_req_i, - output full_resp_t slv_resp_o, - output logic [AxiIdWidth-1:0] id_out + parameter int unsigned AxiAddrWidth = 32'd0, + parameter int unsigned AxiDataWidth = 32'd0, + parameter int unsigned AxiIdWidth = 32'd0, + parameter int unsigned AxiUserWidth = 32'd0, + parameter type full_req_t = logic, + parameter type full_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input full_req_t slv_req_i, + output full_resp_t slv_resp_o, + output logic [AxiIdWidth-1:0] id_out ); axi_burst_splitter #( - .AddrWidth ( AxiAddrWidth ), - .DataWidth ( AxiDataWidth ), - .IdWidth ( AxiIdWidth ), - .UserWidth ( AxiUserWidth ), - .axi_req_t ( full_req_t ), - .axi_resp_t ( full_resp_t ) + .AddrWidth(AxiAddrWidth), + .DataWidth(AxiDataWidth), + .IdWidth(AxiIdWidth), + .UserWidth(AxiUserWidth), + .axi_req_t(full_req_t), + .axi_resp_t(full_resp_t) ) i_axi_burst_splitter ( - .clk_i, .rst_ni, - .slv_req_i, .slv_resp_o, .id_out + .clk_i, + .rst_ni, + .slv_req_i, + .slv_resp_o, + .id_out ); int unsigned req_bits_out; @@ -369,12 +400,13 @@ endmodule //====================================================================== // axi_to_axi_lite_wrap - non-parameterized wrapper (#()) with iface port //====================================================================== -module axi_to_axi_lite_wrap #()( - input logic clk_i, - input logic rst_ni, - my_if.target axi_tgt_io +module axi_to_axi_lite_wrap #( +) ( + input logic clk_i, + input logic rst_ni, + my_if.target axi_tgt_io ); - typedef axi_tgt_io.req_t tgt_req_t; + typedef axi_tgt_io.req_t tgt_req_t; typedef axi_tgt_io.resp_t tgt_resp_t; tgt_req_t tgt_req; @@ -386,17 +418,18 @@ module axi_to_axi_lite_wrap #()( int unsigned req_bits_out; axi_to_axi_lite #( - .AxiAddrWidth ( 32 ), - .AxiDataWidth ( axi_tgt_io.cfg.DataBits ), - .AxiIdWidth ( axi_tgt_io.cfg.IdBits ), - .AxiUserWidth ( 1 ), - .full_req_t ( tgt_req_t ), - .full_resp_t ( tgt_resp_t ) + .AxiAddrWidth(32), + .AxiDataWidth(axi_tgt_io.cfg.DataBits), + .AxiIdWidth(axi_tgt_io.cfg.IdBits), + .AxiUserWidth(1), + .full_req_t(tgt_req_t), + .full_resp_t(tgt_resp_t) ) axi_to_axi_lite ( - .clk_i, .rst_ni, - .slv_req_i ( tgt_req ), - .slv_resp_o ( tgt_resp ), - .id_out ( id_result ) + .clk_i, + .rst_ni, + .slv_req_i(tgt_req), + .slv_resp_o(tgt_resp), + .id_out(id_result) ); assign req_bits_out = axi_to_axi_lite.req_bits_out; @@ -405,25 +438,26 @@ endmodule //====================================================================== // axi_dw_converter_wrap - non-parameterized wrapper with TWO iface ports //====================================================================== -module axi_dw_converter_wrap #()( - input logic clk_i, - input logic rst_ni, - my_if.target tgt_io, - my_if.initiator mst_io +module axi_dw_converter_wrap #( +) ( + input logic clk_i, + input logic rst_ni, + my_if.target tgt_io, + my_if.initiator mst_io ); - typedef tgt_io.aw_chan_t tgt_aw_chan_t; - typedef tgt_io.w_chan_t tgt_w_chan_t; - typedef tgt_io.b_chan_t tgt_b_chan_t; - typedef tgt_io.ar_chan_t tgt_ar_chan_t; - typedef tgt_io.r_chan_t tgt_r_chan_t; + typedef tgt_io.aw_chan_t tgt_aw_chan_t; + typedef tgt_io.w_chan_t tgt_w_chan_t; + typedef tgt_io.b_chan_t tgt_b_chan_t; + typedef tgt_io.ar_chan_t tgt_ar_chan_t; + typedef tgt_io.r_chan_t tgt_r_chan_t; - typedef mst_io.w_chan_t mst_w_chan_t; - typedef mst_io.r_chan_t mst_r_chan_t; + typedef mst_io.w_chan_t mst_w_chan_t; + typedef mst_io.r_chan_t mst_r_chan_t; - typedef tgt_io.req_t tgt_req_t; - typedef tgt_io.resp_t tgt_resp_t; - typedef mst_io.req_t mst_req_t; - typedef mst_io.resp_t mst_resp_t; + typedef tgt_io.req_t tgt_req_t; + typedef tgt_io.resp_t tgt_resp_t; + typedef mst_io.req_t mst_req_t; + typedef mst_io.resp_t mst_resp_t; tgt_req_t tgt_req; tgt_resp_t tgt_resp; @@ -436,27 +470,28 @@ module axi_dw_converter_wrap #()( assign mst_resp = mst_io.resp; axi_dw_converter #( - .AxiSlvPortDataWidth ( tgt_io.cfg.DataBits ), - .AxiMstPortDataWidth ( mst_io.cfg.DataBits ), - .AxiAddrWidth ( 32 ), - .AxiIdWidth ( tgt_io.cfg.IdBits ), - .aw_chan_t ( tgt_aw_chan_t ), - .mst_w_chan_t ( mst_w_chan_t ), - .slv_w_chan_t ( tgt_w_chan_t ), - .b_chan_t ( tgt_b_chan_t ), - .ar_chan_t ( tgt_ar_chan_t ), - .mst_r_chan_t ( mst_r_chan_t ), - .slv_r_chan_t ( tgt_r_chan_t ), - .axi_mst_req_t ( mst_req_t ), - .axi_mst_resp_t ( mst_resp_t ), - .axi_slv_req_t ( tgt_req_t ), - .axi_slv_resp_t ( tgt_resp_t ) + .AxiSlvPortDataWidth(tgt_io.cfg.DataBits), + .AxiMstPortDataWidth(mst_io.cfg.DataBits), + .AxiAddrWidth(32), + .AxiIdWidth(tgt_io.cfg.IdBits), + .aw_chan_t(tgt_aw_chan_t), + .mst_w_chan_t(mst_w_chan_t), + .slv_w_chan_t(tgt_w_chan_t), + .b_chan_t(tgt_b_chan_t), + .ar_chan_t(tgt_ar_chan_t), + .mst_r_chan_t(mst_r_chan_t), + .slv_r_chan_t(tgt_r_chan_t), + .axi_mst_req_t(mst_req_t), + .axi_mst_resp_t(mst_resp_t), + .axi_slv_req_t(tgt_req_t), + .axi_slv_resp_t(tgt_resp_t) ) dw_converter ( - .clk_i, .rst_ni, - .slv_req_i ( tgt_req ), - .slv_resp_o ( tgt_resp ), - .mst_req_o ( mst_req ), - .mst_resp_i ( mst_resp ) + .clk_i, + .rst_ni, + .slv_req_i(tgt_req), + .slv_resp_o(tgt_resp), + .mst_req_o(mst_req), + .mst_resp_i(mst_resp) ); // Expose $bits from the mst-side leaf (through dw_converter -> upsizer -> demux) @@ -484,20 +519,23 @@ module t; // Config B: wide ID (8 bits), data 64 bits localparam cfg_pkg::cfg_t CFG_B = '{IdBits: 8, DataBits: 64}; - my_if #(.cfg(CFG_A_SLV)) bus_a_slv(); - my_if #(.cfg(CFG_A_MST)) bus_a_mst(); - my_if #(.cfg(CFG_B)) bus_b(); + my_if #(.cfg(CFG_A_SLV)) bus_a_slv (); + my_if #(.cfg(CFG_A_MST)) bus_a_mst (); + my_if #(.cfg(CFG_B)) bus_b (); // Path A: dw_converter_wrap (narrow ID, upsize 64->128) axi_dw_converter_wrap #() u_dw_conv_wrap ( - .clk_i(clk), .rst_ni(rst_n), - .tgt_io(bus_a_slv), .mst_io(bus_a_mst) + .clk_i(clk), + .rst_ni(rst_n), + .tgt_io(bus_a_slv), + .mst_io(bus_a_mst) ); // Path B: axi_to_axi_lite_wrap (wide ID) axi_to_axi_lite_wrap #() u_axi_to_lite_wrap ( - .clk_i(clk), .rst_ni(rst_n), - .axi_tgt_io(bus_b) + .clk_i(clk), + .rst_ni(rst_n), + .axi_tgt_io(bus_b) ); //====================================================================== @@ -524,11 +562,12 @@ module t; localparam int unsigned EXP_REQ_BITS_A_SLV = 236; localparam int unsigned EXP_REQ_BITS_A_MST = 436; - localparam int unsigned EXP_REQ_BITS_B = 248; + localparam int unsigned EXP_REQ_BITS_B = 248; // verilator lint_off STMTDLY initial begin - clk = 0; rst_n = 1; + clk = 0; + rst_n = 1; // Drive path A: narrow ID bus_a_slv.req = '0; @@ -583,8 +622,7 @@ module t; // axi_to_axi_lite_wrap -> ... -> axi_demux_simple extracts aw.id[0+:8] //------------------------------------------------------------------ if (u_axi_to_lite_wrap.id_result !== 8'hAB) begin - $display("%%Error: axi_to_lite id_result=%0h expected=AB", - u_axi_to_lite_wrap.id_result); + $display("%%Error: axi_to_lite id_result=%0h expected=AB", u_axi_to_lite_wrap.id_result); $stop; end diff --git a/test_regress/t/t_semaphore_concurrent.v b/test_regress/t/t_semaphore_concurrent.v index 58186867e..56342859c 100644 --- a/test_regress/t/t_semaphore_concurrent.v +++ b/test_regress/t/t_semaphore_concurrent.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2024 Liam Braun // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; semaphore s; // Stand-in for a task that should only be run by one thread at a time diff --git a/test_regress/t/t_split_var_1_bad.v b/test_regress/t/t_split_var_1_bad.v index b448b7a21..3e494d990 100644 --- a/test_regress/t/t_split_var_1_bad.v +++ b/test_regress/t/t_split_var_1_bad.v @@ -12,7 +12,7 @@ interface ifs; logic [7:0] should_show_warning_ifs1 [1:0] /* verilator split_var */; endinterface -module t(); +module t; // The following variables can not be splitted. will see warnings. real should_show_warning0 /*verilator split_var*/; string should_show_warning1 /*verilator split_var*/; diff --git a/test_regress/t/t_static_function_in_class_noparen.v b/test_regress/t/t_static_function_in_class_noparen.v index 654751306..502278131 100644 --- a/test_regress/t/t_static_function_in_class_noparen.v +++ b/test_regress/t/t_static_function_in_class_noparen.v @@ -16,7 +16,7 @@ class Foo; endfunction endclass -module t(); +module t; initial begin int v; diff --git a/test_regress/t/t_std_process_self.v b/test_regress/t/t_std_process_self.v index 9627bbaff..489a794dd 100644 --- a/test_regress/t/t_std_process_self.v +++ b/test_regress/t/t_std_process_self.v @@ -15,7 +15,7 @@ class Foo; endtask endclass -module t(); +module t; initial begin Foo::do_something(); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_struct_genfor.v b/test_regress/t/t_struct_genfor.v index c6415abac..5026862e0 100644 --- a/test_regress/t/t_struct_genfor.v +++ b/test_regress/t/t_struct_genfor.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; for (genvar g = 0; g < 2; ++g) begin : genfor typedef struct packed { diff --git a/test_regress/t/t_structu_wide.v b/test_regress/t/t_structu_wide.v index 61dca1ad7..061bc2360 100644 --- a/test_regress/t/t_structu_wide.v +++ b/test_regress/t/t_structu_wide.v @@ -8,7 +8,7 @@ `define WIDE_WIDTH 128 `endif -module t (); +module t; typedef struct { bit [`WIDE_WIDTH-1:0] data; } wide_t; diff --git a/test_regress/t/t_sys_readmem_eof.v b/test_regress/t/t_sys_readmem_eof.v index dac29b83d..0a6b604a1 100644 --- a/test_regress/t/t_sys_readmem_eof.v +++ b/test_regress/t/t_sys_readmem_eof.v @@ -8,7 +8,7 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define STRINGIFY(x) `"x`" -module t(); +module t; reg [7:0] rom [4]; initial begin $readmemh({`STRINGIFY(`TEST_OBJ_DIR), "/dat.mem"}, rom); diff --git a/test_regress/t/t_timing_dynscope.v b/test_regress/t/t_timing_dynscope.v index cc03503ea..8a8d75fe2 100644 --- a/test_regress/t/t_timing_dynscope.v +++ b/test_regress/t/t_timing_dynscope.v @@ -25,7 +25,7 @@ class Foo; endtask endclass -module t(); +module t; initial begin int desired_counts[10]; counts = '{10{0}}; diff --git a/test_regress/t/t_timing_split.v b/test_regress/t/t_timing_split.v index cd33fa6af..0850ce7c8 100644 --- a/test_regress/t/t_timing_split.v +++ b/test_regress/t/t_timing_split.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Jomit626 // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; logic clk = 0; logic data = 0; diff --git a/test_regress/t/t_trace_split_cfuncs.v b/test_regress/t/t_trace_split_cfuncs.v index be695fa88..a4adac3ac 100644 --- a/test_regress/t/t_trace_split_cfuncs.v +++ b/test_regress/t/t_trace_split_cfuncs.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2022 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; initial begin $dumpfile("dump.vcd"); diff --git a/test_regress/t/t_trace_split_cfuncs_dpi_export.v b/test_regress/t/t_trace_split_cfuncs_dpi_export.v index 2951f36e1..6bd0d4ca5 100644 --- a/test_regress/t/t_trace_split_cfuncs_dpi_export.v +++ b/test_regress/t/t_trace_split_cfuncs_dpi_export.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2022 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; function automatic void func(); endfunction diff --git a/test_regress/t/t_type_param.v b/test_regress/t/t_type_param.v index ed22d9d21..89e2b51d0 100644 --- a/test_regress/t/t_type_param.v +++ b/test_regress/t/t_type_param.v @@ -25,7 +25,7 @@ module foo_wrapper endmodule -module t(); +module t; logic [7:0] qux1; int bar_size1; diff --git a/test_regress/t/t_udp_nonsequential_x.v b/test_regress/t/t_udp_nonsequential_x.v index d415442c3..a598cc533 100644 --- a/test_regress/t/t_udp_nonsequential_x.v +++ b/test_regress/t/t_udp_nonsequential_x.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2025 Michael Bikovitsky // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; wire true1; not1 a(true1, '0); diff --git a/test_regress/t/t_var_extern_method_lifetime.v b/test_regress/t/t_var_extern_method_lifetime.v index 1b1feb3d9..efbe410fe 100644 --- a/test_regress/t/t_var_extern_method_lifetime.v +++ b/test_regress/t/t_var_extern_method_lifetime.v @@ -20,7 +20,7 @@ task automatic Foo::add_in_fork_delayed(int delay, Foo arg); join_none endtask -module t(); +module t; initial begin Foo foo1, foo2; foo1 = new(1); diff --git a/test_regress/t/t_var_in_fork.v b/test_regress/t/t_var_in_fork.v index 8406377a9..2146249f7 100644 --- a/test_regress/t/t_var_in_fork.v +++ b/test_regress/t/t_var_in_fork.v @@ -6,7 +6,7 @@ int static_var; -module t(); +module t; event evt; task send_event(); ->evt; diff --git a/test_regress/t/t_x_rand_scoped_is_random.v b/test_regress/t/t_x_rand_scoped_is_random.v index e3b4ce968..e6b6fa690 100644 --- a/test_regress/t/t_x_rand_scoped_is_random.v +++ b/test_regress/t/t_x_rand_scoped_is_random.v @@ -6,7 +6,7 @@ `define STRINGIFY(x) `"x`" -module t (); +module t; reg a0 = 'x; reg a1 = 'x; reg a2 = 'x;