Verilog format

This commit is contained in:
Veripool API Bot
2026-03-03 07:21:24 -05:00
committed by Wilson Snyder
parent 5821d0697c
commit ce4d35aa85
340 changed files with 7037 additions and 6797 deletions
+6 -6
View File
@@ -5,12 +5,12 @@
// SPDX-License-Identifier: CC0-1.0
module t;
initial begin
int q[5];
initial begin
int q[5];
q.mex;
q.mex;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule