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Verilog format
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committed by
Wilson Snyder
parent
5821d0697c
commit
ce4d35aa85
@@ -5,12 +5,12 @@
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// SPDX-License-Identifier: CC0-1.0
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module t;
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initial begin
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int q[5];
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initial begin
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int q[5];
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q.mex;
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q.mex;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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