Tests: Reformat some recent tests to mostly verilog-format standard. No test functional change.

test_regress/t/t_array_pattern_side_effect.v

@@ -15,13 +15,9 @@ module t;
   // verilator lint_off ASCRANGE
   typedef logic [0:2][7:0] triple_lv_t;
   // verilator lint_on ASCRANGE
-  typedef triple_lv_t pair_t [0:1];
+  typedef triple_lv_t pair_t[0:1];
 
-  function automatic triple_lv_t mk3(
-    input logic [7:0] a,
-    input logic [7:0] b,
-    input logic [7:0] c
-  );
+  function automatic triple_lv_t mk3(input logic [7:0] a, input logic [7:0] b, input logic [7:0] c);
     mk3 = '{0: a, 1: b, 2: c};
   endfunction
 
@@ -29,10 +25,7 @@ module t;
 
   initial begin
     // verilator lint_off SIDEEFFECT
-    pair = '{
-      0: mk3(8'd1, 8'd2, 8'd3),
-      1: mk3(8'd4, 8'd5, 8'd6)
-    };
+    pair = '{0: mk3(8'd1, 8'd2, 8'd3), 1: mk3(8'd4, 8'd5, 8'd6)};
     // verilator lint_on SIDEEFFECT
 
     `checkd(pair[0][0], 8'd1);

test_regress/t/t_assert_always_unbounded.v

@@ -26,17 +26,21 @@ module t (
   int drop_fail_q[$];
 
   // Constant-true input: never fails at any tick.
-  assert property (@(posedge clk) always [2:$] a_high) else high_fail_q.push_back(cyc);
+  assert property (@(posedge clk) always[2: $] a_high)
+  else high_fail_q.push_back(cyc);
 
   // Constant-false input, m=0: fails at every observed tick.
-  assert property (@(posedge clk) always [0:$] a_low) else low0_fail_q.push_back(cyc);
+  assert property (@(posedge clk) always[0: $] a_low)
+  else low0_fail_q.push_back(cyc);
 
   // Constant-false input, m=2: fails at every tick once the window is live.
-  assert property (@(posedge clk) always [2:$] a_low) else low2_fail_q.push_back(cyc);
+  assert property (@(posedge clk) always[2: $] a_low)
+  else low2_fail_q.push_back(cyc);
 
   // a_drop is high then drops at cyc 5 and stays low: deterministic single
   // transition, so Verilator and others agree on the failing ticks exactly.
-  assert property (@(posedge clk) always [2:$] a_drop) else drop_fail_q.push_back(cyc);
+  assert property (@(posedge clk) always[2: $] a_drop)
+  else drop_fail_q.push_back(cyc);
 
   always @(posedge clk) begin
     cyc <= cyc + 1;

test_regress/t/t_assert_procedural.v

@@ -27,19 +27,18 @@ module t (
 
   always @(negedge clk) begin
     assert property (disable iff (!rst_l) ((&req) |-> gnt))
-    else
-      assert_procedural <= 1'b1;
+    else assert_procedural <= 1'b1;
     cntneg <= cntneg + 1;  // To check unlink of above assert
   end
 
   assert property (@(negedge clk) disable iff (!rst_l) ((&req) |-> gnt))
-  else
-    assert_immediate <= 1'b1;
+  else assert_immediate <= 1'b1;
 
   // Test loop
   always @(posedge clk) begin
 `ifdef TEST_VERBOSE
-    $write("[%0t] cyc==%0d req='b%b gnt=%b  exp=%x proc=%x imm=%x\n", $time, cyc, req, gnt, assert_exp, assert_procedural, assert_immediate);
+    $write("[%0t] cyc==%0d req='b%b gnt=%b  exp=%x proc=%x imm=%x\n", $time, cyc, req, gnt,
+           assert_exp, assert_procedural, assert_immediate);
 `endif
     cyc <= cyc + 1;
     assert_procedural <= 0;  // Careful, will race unless assert is on negedge

test_regress/t/t_class_extends_param_scope.v

@@ -5,7 +5,9 @@
 // SPDX-License-Identifier: CC0-1.0
 
 // A factory-like static method, as used by UVM's type_id::create().
-class registry #(type T = int);
+class registry #(
+    type T = int
+);
   static function T create();
     T r = new;
     return r;
@@ -20,7 +22,10 @@ class item;
   endfunction
 endclass
 
-class seq_base #(type REQ = int, type RSP = REQ);
+class seq_base #(
+    type REQ = int,
+    type RSP = REQ
+);
   REQ req;
 endclass
 

test_regress/t/t_cover_fsm_nonenum_literal.v

@@ -72,8 +72,7 @@ module t (
     end
     else begin
       case (body_symbol_state)
-        BODY_ID
-            : body_symbol_state <= BODY$ID;
+        BODY_ID: body_symbol_state <= BODY$ID;
         BODY$ID: body_symbol_state <= BODY_ID;
         default: body_symbol_state <= BODY_ID;
       endcase
@@ -86,8 +85,7 @@ module t (
     end
     else begin
       case (multiline_expr_state)
-        (2'h0
-         + 2'h0): multiline_expr_state <= 2'h1;
+        (2'h0 + 2'h0): multiline_expr_state <= 2'h1;
         2'h1: multiline_expr_state <= 2'h0;
         default: multiline_expr_state <= 2'h0;
       endcase
@@ -102,8 +100,7 @@ module t (
       /* verilator lint_off CASEOVERLAP */
       case (duplicate_expr_state)
         IDLE: duplicate_expr_state <= BUSY;
-        (2'h0
-         + 2'h0): duplicate_expr_state <= BUSY;
+        (2'h0 + 2'h0): duplicate_expr_state <= BUSY;
         BUSY: duplicate_expr_state <= IDLE;
         default: duplicate_expr_state <= IDLE;
       endcase
@@ -134,8 +131,7 @@ module t (
     else begin
       /* verilator lint_off CASEOVERLAP */
       case (duplicate_expr_first_state)
-        (2'h0
-         + 2'h0): duplicate_expr_first_state <= BUSY;
+        (2'h0 + 2'h0): duplicate_expr_first_state <= BUSY;
         IDLE: duplicate_expr_first_state <= BUSY;
         BUSY: duplicate_expr_first_state <= 2'h0;
         default: duplicate_expr_first_state <= 2'h0;

test_regress/t/t_cover_fsm_reset.out

@@ -71,7 +71,8 @@
               start <= 1'b1;
               state_q <= S0;
               aux <= 1'b0;
-            end else begin
+            end
+            else begin
               state_q <= state_d;
             end
           end
@@ -101,7 +102,8 @@
           always_ff @(posedge clk) begin
             if (rst) begin
               other_q <= S0;
-            end else begin
+            end
+            else begin
 %000001       case (state_q)
         // [FSM coverage]
 %000001        // [fsm_arc t.oneblock_reset_mismatch_ok_u.state_q::S0->S1]
@@ -133,7 +135,8 @@
           always_ff @(posedge clk) begin
             if (rst) begin
               state_q <= other_q;
-            end else begin
+            end
+            else begin
 %000001       case (state_q)
         // [FSM coverage]
 %000000        // [fsm_arc t.oneblock_reset_nonconst_ok_u.state_q::S0->S1]
@@ -154,10 +157,22 @@
           logic rst;
           integer cyc;
         
-          fsm_reset_policy reset_policy_u (.clk(clk), .rst(rst));
-          fsm_reset_other_assign_ok reset_other_assign_ok_u (.clk(clk), .rst(rst));
-          fsm_oneblock_reset_mismatch_ok oneblock_reset_mismatch_ok_u (.clk(clk), .rst(rst));
-          fsm_oneblock_reset_nonconst_ok oneblock_reset_nonconst_ok_u (.clk(clk), .rst(rst));
+          fsm_reset_policy reset_policy_u (
+              .clk(clk),
+              .rst(rst)
+          );
+          fsm_reset_other_assign_ok reset_other_assign_ok_u (
+              .clk(clk),
+              .rst(rst)
+          );
+          fsm_oneblock_reset_mismatch_ok oneblock_reset_mismatch_ok_u (
+              .clk(clk),
+              .rst(rst)
+          );
+          fsm_oneblock_reset_nonconst_ok oneblock_reset_nonconst_ok_u (
+              .clk(clk),
+              .rst(rst)
+          );
         
           initial begin
             rst = 1'b1;

test_regress/t/t_cover_fsm_reset.v

@@ -60,7 +60,8 @@ module fsm_reset_other_assign_ok (
       start <= 1'b1;
       state_q <= S0;
       aux <= 1'b0;
-    end else begin
+    end
+    else begin
       state_q <= state_d;
     end
   end
@@ -90,7 +91,8 @@ module fsm_oneblock_reset_mismatch_ok (
   always_ff @(posedge clk) begin
     if (rst) begin
       other_q <= S0;
-    end else begin
+    end
+    else begin
       case (state_q)
         S0: state_q <= S1;
         default: state_q <= S2;
@@ -117,7 +119,8 @@ module fsm_oneblock_reset_nonconst_ok (
   always_ff @(posedge clk) begin
     if (rst) begin
       state_q <= other_q;
-    end else begin
+    end
+    else begin
       case (state_q)
         S0: state_q <= S1;
         default: state_q <= S2;
@@ -133,10 +136,22 @@ module t (
   logic rst;
   integer cyc;
 
-  fsm_reset_policy reset_policy_u (.clk(clk), .rst(rst));
-  fsm_reset_other_assign_ok reset_other_assign_ok_u (.clk(clk), .rst(rst));
-  fsm_oneblock_reset_mismatch_ok oneblock_reset_mismatch_ok_u (.clk(clk), .rst(rst));
-  fsm_oneblock_reset_nonconst_ok oneblock_reset_nonconst_ok_u (.clk(clk), .rst(rst));
+  fsm_reset_policy reset_policy_u (
+      .clk(clk),
+      .rst(rst)
+  );
+  fsm_reset_other_assign_ok reset_other_assign_ok_u (
+      .clk(clk),
+      .rst(rst)
+  );
+  fsm_oneblock_reset_mismatch_ok oneblock_reset_mismatch_ok_u (
+      .clk(clk),
+      .rst(rst)
+  );
+  fsm_oneblock_reset_nonconst_ok oneblock_reset_nonconst_ok_u (
+      .clk(clk),
+      .rst(rst)
+  );
 
   initial begin
     rst = 1'b1;

test_regress/t/t_cover_fsm_reset_incl.out

@@ -71,7 +71,8 @@
               start <= 1'b1;
               state_q <= S0;
               aux <= 1'b0;
-            end else begin
+            end
+            else begin
               state_q <= state_d;
             end
           end
@@ -101,7 +102,8 @@
           always_ff @(posedge clk) begin
             if (rst) begin
               other_q <= S0;
-            end else begin
+            end
+            else begin
 %000001       case (state_q)
         // [FSM coverage]
 %000001        // [fsm_arc t.oneblock_reset_mismatch_ok_u.state_q::S0->S1]
@@ -133,7 +135,8 @@
           always_ff @(posedge clk) begin
             if (rst) begin
               state_q <= other_q;
-            end else begin
+            end
+            else begin
 %000001       case (state_q)
         // [FSM coverage]
 %000000        // [fsm_arc t.oneblock_reset_nonconst_ok_u.state_q::S0->S1]
@@ -154,10 +157,22 @@
           logic rst;
           integer cyc;
         
-          fsm_reset_policy reset_policy_u (.clk(clk), .rst(rst));
-          fsm_reset_other_assign_ok reset_other_assign_ok_u (.clk(clk), .rst(rst));
-          fsm_oneblock_reset_mismatch_ok oneblock_reset_mismatch_ok_u (.clk(clk), .rst(rst));
-          fsm_oneblock_reset_nonconst_ok oneblock_reset_nonconst_ok_u (.clk(clk), .rst(rst));
+          fsm_reset_policy reset_policy_u (
+              .clk(clk),
+              .rst(rst)
+          );
+          fsm_reset_other_assign_ok reset_other_assign_ok_u (
+              .clk(clk),
+              .rst(rst)
+          );
+          fsm_oneblock_reset_mismatch_ok oneblock_reset_mismatch_ok_u (
+              .clk(clk),
+              .rst(rst)
+          );
+          fsm_oneblock_reset_nonconst_ok oneblock_reset_nonconst_ok_u (
+              .clk(clk),
+              .rst(rst)
+          );
         
           initial begin
             rst = 1'b1;

test_regress/t/t_cover_fsm_two_proc_multi.out

@@ -437,7 +437,8 @@
 %000007     if (rst) begin
 %000002       side <= 1'b0;
 %000002       state_q <= S0;
-%000007     end else begin
+            end
+%000007     else begin
 %000007       side <= ~side;
 %000007       state_q <= state_d;
             end

test_regress/t/t_cover_fsm_two_proc_multi.v

@@ -375,7 +375,8 @@ module fsm_seqmix_off (
     if (rst) begin
       side <= 1'b0;
       state_q <= S0;
-    end else begin
+    end
+    else begin
       side <= ~side;
       state_q <= state_d;
     end

test_regress/t/t_dfg_regularize_driver_of_sc_var.v

@@ -4,11 +4,20 @@
 // SPDX-FileCopyrightText: 2024 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-module sub(input in, output out);
+module sub (
+    input in,
+    output out
+);
   assign out = in;
 endmodule
 
-module top(input clk, output out);
+module top (
+    input clk,
+    output out
+);
   logic one = '1;
-  sub sub_inst(.in(one), .out(out));
+  sub sub_inst (
+      .in(one),
+      .out(out)
+  );
 endmodule

test_regress/t/t_disable_task_join.v

@@ -48,8 +48,8 @@ module t;
 
   driver c;
   task automatic progress(input string label);
-    $display("DBG:t_disable_task_join:%s t=%0t x=%0d y=%0d z=%0d w=%0d m_time=%0d",
-             label, $time, x, y, z, w, (c == null) ? -1 : c.m_time);
+    $display("DBG:t_disable_task_join:%s t=%0t x=%0d y=%0d z=%0d w=%0d m_time=%0d", label, $time,
+             x, y, z, w, (c == null) ? -1 : c.m_time);
   endtask
 
   initial begin

test_regress/t/t_gate_strength.v

@@ -5,10 +5,11 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-  input clk
-  );
+    input clk
+);
 
-  integer cyc; initial cyc=1;
+  integer cyc;
+  initial cyc = 1;
 
   logic [31:0] a;
 
@@ -28,13 +29,13 @@ module t (
   assign (weak0, weak1) nt15 = a[0];
   // verilator lint_on IMPLICIT
 
-  always @ (posedge clk) begin
-    if (cyc!=0) begin
+  always @(posedge clk) begin
+    if (cyc != 0) begin
       cyc <= cyc + 1;
-      if (cyc==1) begin
+      if (cyc == 1) begin
         a <= 32'h18f6b030;
       end
-      if (cyc==2) begin
+      if (cyc == 2) begin
         a <= 32'h18f6b03f;
         if (nt00 !== 1'b0) $stop;
         if (nt01 !== 1'b0) $stop;
@@ -49,7 +50,7 @@ module t (
         if (nt14 !== 1'b0) $stop;
         if (nt15 !== 1'b0) $stop;
       end
-      if (cyc==3) begin
+      if (cyc == 3) begin
         if (nt00 !== 1'b1) $stop;
         if (nt01 !== 1'b1) $stop;
         if (nt02 !== 1'b1) $stop;
@@ -63,7 +64,7 @@ module t (
         if (nt14 !== 1'b1) $stop;
         if (nt15 !== 1'b1) $stop;
       end
-      if (cyc==4) begin
+      if (cyc == 4) begin
         $write("*-* All Finished *-*\n");
         $finish;
       end

test_regress/t/t_inside_nonint.v

@@ -5,31 +5,23 @@
 // SPDX-License-Identifier: CC0-1.0
 
 function bit check_string(string s);
-  if (s inside {"RW", "WO"})
-    return 1'b1;
+  if (s inside {"RW", "WO"}) return 1'b1;
   return 1'b0;
 endfunction
 
 function bit check_double(real d);
-  if (d inside {0.0, 2.5})
-    return 1'b1;
+  if (d inside {0.0, 2.5}) return 1'b1;
   return 1'b0;
 endfunction
 
 module t;
   initial begin
-    if (!check_string("WO"))
-      $stop;
-    if (!check_string("RW"))
-      $stop;
-    if (check_string("ABC"))
-      $stop;
-    if (!check_double(0.0))
-      $stop;
-    if (!check_double(2.5))
-      $stop;
-    if (check_double(1.0))
-      $stop;
+    if (!check_string("WO")) $stop;
+    if (!check_string("RW")) $stop;
+    if (check_string("ABC")) $stop;
+    if (!check_double(0.0)) $stop;
+    if (!check_double(2.5)) $stop;
+    if (check_double(1.0)) $stop;
 
     $display("*-* All Finished *-*");
     $finish;

test_regress/t/t_inst_nansi.v

@@ -4,7 +4,14 @@
 // SPDX-FileCopyrightText: 2025 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-module t(b, si, i, li, w3, w4);
+module t (
+    b,
+    si,
+    i,
+    li,
+    w3,
+    w4
+);
   output b;  // Output before type
   output si;
   byte b;

test_regress/t/t_interface_input_port_assign.v

@@ -15,27 +15,27 @@
 
 // Scenario 1: bare input (defaults to net)
 interface bare_if (
-  input clk
+    input clk
 );
   logic data;
 endinterface
 
 // Scenario 2: input with explicit data type (still net for input)
 interface logic_if (
-  input logic clk
+    input logic clk
 );
   logic data;
 endinterface
 
 // Scenario 3: input with explicit net kind
 interface wire_if (
-  input wire clk
+    input wire clk
 );
   logic data;
 endinterface
 
 module consumer (
-  bare_if cif
+    bare_if cif
 );
   logic sampled;
   always @(posedge cif.clk) sampled <= cif.data;
@@ -43,22 +43,20 @@ endmodule
 
 // Scenario 4: port connection driving interface input (AstPin path)
 interface ifc_status (
-  input wire busy
+    input wire busy
 );
 endinterface
 
 module dut (
-  output logic sleep_o
+    output logic sleep_o
 );
   initial sleep_o = 1'b1;
 endmodule
 
 module dut_wrap (
-  ifc_status sif
+    ifc_status sif
 );
-  dut u_dut (
-    .sleep_o(sif.busy)
-  );
+  dut u_dut (.sleep_o(sif.busy));
 endmodule
 
 module t;

test_regress/t/t_scheduling_1.v

@@ -6,16 +6,15 @@
 // SPDX-FileCopyrightText: 2022 Geza Lore
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-module top(
-  clk
+module top (
+    clk
 );
 
   input clk;
 
   // Generate half speed 'clk_half', via blocking assignment
   reg clk_half = 0;
-  always @(posedge clk)
-    clk_half = ~clk_half;
+  always @(posedge clk) clk_half = ~clk_half;
 
   // Cycle count (+ stop condition)
   reg [31:0] cyc = 0;
@@ -29,13 +28,11 @@ module top(
 
   // Flop cycle count via `clk`
   reg [31:0] a = 0;
-  always @(posedge clk)
-    a <= cyc;
+  always @(posedge clk) a <= cyc;
 
   // Flop cycle count via `clk_half`, on both edges
   reg [31:0] b = 0;
-  always @(posedge clk_half or negedge clk_half)
-    b <= cyc;
+  always @(posedge clk_half or negedge clk_half) b <= cyc;
 
   // `a` should always equal `b`, no mater which value they actually capture
   always @(posedge clk) begin

test_regress/t/t_selextract_in_paramextends.v

@@ -6,7 +6,9 @@
 
 typedef class Foo;
 
-virtual class Bar #(type T);
+virtual class Bar #(
+    type T
+);
   T m_val;
 endclass
 
@@ -14,7 +16,7 @@ class Baz;
   rand bit [3:0] m_sus;
 endclass
 
-class Foo extends Bar#(Baz);
+class Foo extends Bar #(Baz);
   function new();
     Baz baz;
     super.new();
@@ -27,7 +29,7 @@ class Foo extends Bar#(Baz);
   endtask
 endclass
 
-module test();
+module test ();
   initial begin
     automatic Foo foo = new;
 

test_regress/t/t_sys_sformat.v

@@ -43,9 +43,7 @@ module t (
   int mem[2] = '{1, 2};
   string s;
 
-  typedef struct{
-    integer dummy;
-  } test_struct_t;
+  typedef struct {integer dummy;} test_struct_t;
 
   test_struct_t structs[1];
 

test_regress/t/t_unbounded.v

@@ -6,7 +6,7 @@
 
 module t;
 
-  parameter int UNB /*verilator public*/ = $;
+  parameter int UNB  /*verilator public*/ = $;
   localparam int UNB2 = $;
   localparam SIX = 6;
 

test_regress/t/t_unroll_stmt.v

@@ -66,7 +66,7 @@ module t;
       automatic int i = 0;
       while (i < 5) begin : loop_7
         $display("loop_7 %0d", i);
-        for (int j = 0 ; j < 4; ++j) begin : loop_8
+        for (int j = 0; j < 4; ++j) begin : loop_8
           $display("loop_8 %0d", j);
           if (j == 3) ++i;
         end

test_regress/t/t_uvm_static_func1.v

@@ -14,7 +14,7 @@
 package uvm_pkg;
 
   class uvm_tlm_extension #(
-    type T = int
+      type T = int
   );
     static function int ID();
       return 42;

test_regress/t/t_var_sc_double.v

@@ -5,12 +5,12 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-  // Outputs
-  o_z,
-  // Inputs
-  i_a
-  );
-  input real  i_a;
+    // Outputs
+    o_z,
+    // Inputs
+    i_a
+);
+  input real i_a;
   output real o_z;
 
   assign o_z = i_a;