From c3fc0d9f0ffe3ef883000361e0ff9c90147bdf49 Mon Sep 17 00:00:00 2001
From: Igor Zaworski <izaworski@antmicro.com>
Date: Fri, 20 Mar 2026 17:23:32 +0100
Subject: [PATCH] Fix coroutine trace setters (#7078 repair) (#7296)

---
 src/V3Trace.cpp                              |  6 ++--
 test_regress/t/t_trace_wide_initial_wait.out | 35 ++++++++++++++++++++
 test_regress/t/t_trace_wide_initial_wait.py  | 20 +++++++++++
 test_regress/t/t_trace_wide_initial_wait.v   | 25 ++++++++++++++
 4 files changed, 82 insertions(+), 4 deletions(-)
 create mode 100644 test_regress/t/t_trace_wide_initial_wait.out
 create mode 100755 test_regress/t/t_trace_wide_initial_wait.py
 create mode 100644 test_regress/t/t_trace_wide_initial_wait.v

diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp
index 4b532e76f..959b9ef77 100644
--- a/src/V3Trace.cpp
+++ b/src/V3Trace.cpp
@@ -467,10 +467,8 @@ class TraceVisitor final : public VNVisitor {
                     } else if (AstCFunc* const funcp = VN_CAST(insertp, CFunc)) {
                         // If there are awaits, insert the setter after each await
                         if (funcp->isCoroutine() && funcp->stmtsp()) {
-                            funcp->stmtsp()->foreachAndNext([&](AstCAwait* awaitp) {
-                                AstNode* stmtp = awaitp->backp();
-                                while (VN_IS(stmtp, NodeExpr)) stmtp = stmtp->backp();
-                                stmtp->addNextHere(setterp->cloneTree(false));
+                            funcp->stmtsp()->foreachAndNext([setterp](AstCAwait* awaitp) {
+                                awaitp->addNextHere(setterp->cloneTree(false));
                             });
                         }
                         funcp->addStmtsp(setterp);
diff --git a/test_regress/t/t_trace_wide_initial_wait.out b/test_regress/t/t_trace_wide_initial_wait.out
new file mode 100644
index 000000000..bd1b81ece
--- /dev/null
+++ b/test_regress/t/t_trace_wide_initial_wait.out
@@ -0,0 +1,35 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module t $end
+  $var wire 129 " x [128:0] $end
+ $upscope $end
+$enddefinitions $end
+
+
+#1
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "
+#6
+b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
+#10
+b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
+#20
+b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
+#30
+b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
+#40
+b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
+#50
+b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
+#60
+b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
+#70
+b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
+#80
+b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
+#90
+b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
+#100
+b101001100100110000001101101100101111011001001111100010101000110000000010101101011101011111000001101010001010101011010110010100001 "
+#110
+b010110011011001111110010010011010000100110110000011101010111001111111101010010100010100000111110010101110101010100101001101011110 "
+#111
diff --git a/test_regress/t/t_trace_wide_initial_wait.py b/test_regress/t/t_trace_wide_initial_wait.py
new file mode 100755
index 000000000..76f979879
--- /dev/null
+++ b/test_regress/t/t_trace_wide_initial_wait.py
@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary', '--trace-vcd'])
+
+test.execute()
+
+test.vcd_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_wide_initial_wait.v b/test_regress/t/t_trace_wide_initial_wait.v
new file mode 100644
index 000000000..ea4ffbccf
--- /dev/null
+++ b/test_regress/t/t_trace_wide_initial_wait.v
@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+module t;
+  logic [128:0] x = 0;
+
+  always #10 x = ~x;
+
+  initial begin
+    #1;
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+    $dumpvars();
+    #5;
+    x = 442093479423423857275364882039482723489;
+    #5;
+    #100;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule