From bd91b619adf928dd40a3a1181a15eeb5de1143b3 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 20 Aug 2025 21:19:42 -0400 Subject: [PATCH] Support `$fread` with missing start (#6125). --- Changes | 1 + src/verilog.y | 1 + test_regress/t/t_sys_fread.out | 8 +- test_regress/t/t_sys_fread.v | 150 ++++++++++++++++++--------------- 4 files changed, 87 insertions(+), 73 deletions(-) diff --git a/Changes b/Changes index c9269bce3..58c07fc5d 100644 --- a/Changes +++ b/Changes @@ -29,6 +29,7 @@ Verilator 5.039 devel * Support randomization of scope variables with 'std::randomize()' (#5438) (#6185). [Yilou Wang] * Support disabling a fork in additional contexts (#5432 partial) (#6174) (#6183). [Ryszard Rozak, Antmicro Ltd.] * Support bit queue streaming (#5830) (#6103). [Paul Swirhun] +* Support `$fread` with missing start (#6125). [Iztok Jeras] * Support unpacked array `with` methods (#6134). * Support Verilog real ports as SystemC double ports (#6136) (#6158). [George Polack] * Support `$countones` in constraints (#6144 partial) (#6235). [Ryszard Rozak, Antmicro Ltd.] diff --git a/src/verilog.y b/src/verilog.y index d2fd145c0..0befaa115 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -4500,6 +4500,7 @@ system_f_call_or_t: // IEEE: part of system_tf_call (can be task | yD_FREAD '(' expr ',' expr ')' { $$ = new AstFRead{$1, $3, $5, nullptr, nullptr}; } | yD_FREAD '(' expr ',' expr ',' expr ')' { $$ = new AstFRead{$1, $3, $5, $7, nullptr}; } | yD_FREAD '(' expr ',' expr ',' expr ',' expr ')' { $$ = new AstFRead{$1, $3, $5, $7, $9}; } + | yD_FREAD '(' expr ',' expr ',' ',' expr ')' { $$ = new AstFRead{$1, $3, $5, nullptr, $8}; } | yD_FREWIND '(' expr ')' { $$ = new AstFRewind{$1, $3}; } | yD_FLOOR '(' expr ')' { $$ = new AstFloorD{$1, $3}; } | yD_FSCANF '(' expr ',' str commaVRDListE ')' { $$ = new AstFScanF{$1, *$5, $3, $6}; } diff --git a/test_regress/t/t_sys_fread.out b/test_regress/t/t_sys_fread.out index a10cdbc6d..6b6f314a8 100644 --- a/test_regress/t/t_sys_fread.out +++ b/test_regress/t/t_sys_fread.out @@ -1,7 +1,7 @@ Dump: r_i: 00010203 r_upb: 0e 0d 0c 0b 0a 09 08 07 06 05 04 - r_dnb: 19 18 17 16 15 14 13 12 11 10 0f + r_dnb: 0f 10 11 12 13 14 15 16 17 18 19 r_ups: 2e2f 2c2d 2a2b 2829 2627 2425 2223 2021 1e1f 1c1d 1a1b r_dns: 3031 3233 3435 3637 3839 3a3b 3c3d 3e3f 0041 0243 0445 r_upi: 6e6f7071 6a6b6c6d 66676869 62636465 5e5f6061 5a5b5c5d 56575859 52535455 4e4f5051 4a4b4c4d 46474849 @@ -13,9 +13,9 @@ Dump: Dump: r_i: ffffffff - r_upb: 05 04 03 02 01 00 ff ff ff ff ff - r_dnb: ff ff ff ff ff ff ff ff ff ff ff - r_ups: 3fff 3fff 3fff 3fff 0809 0607 3fff 3fff 3fff 3fff 3fff + r_upb: 05 04 03 02 01 00 ff 0e ff ff 0c + r_dnb: 0d ff ff 0f ff 06 07 08 09 0a 0b + r_ups: 3fff 3fff 3fff 3fff 1213 1011 3fff 3fff 3fff 3fff 3fff r_dns: 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff 3fff r_upi: 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff r_dni: 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff 7fffffff diff --git a/test_regress/t/t_sys_fread.v b/test_regress/t/t_sys_fread.v index eb9d2a233..078a1be31 100644 --- a/test_regress/t/t_sys_fread.v +++ b/test_regress/t/t_sys_fread.v @@ -4,87 +4,99 @@ // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define STRINGIFY(x) `"x`" `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on //====================================================================== module t; - integer file; - integer r_i; - byte r_upb[20:10]; - byte r_dnb[20:10]; - reg [13:0] r_ups[20:10]; - reg [13:0] r_dns[10:20]; - reg [30:0] r_upi[20:10]; - reg [30:0] r_dni[10:20]; - reg [61:0] r_upq[20:10]; - reg [61:0] r_dnq[10:20]; - reg [71:0] r_upw[20:10]; - reg [71:0] r_dnw[10:20]; + integer file; + integer r_i; + byte r_upb[20:10]; + byte r_dnb[10:20]; + reg [13:0] r_ups[20:10]; + reg [13:0] r_dns[10:20]; + reg [30:0] r_upi[20:10]; + reg [30:0] r_dni[10:20]; + reg [61:0] r_upq[20:10]; + reg [61:0] r_dnq[10:20]; + reg [71:0] r_upw[20:10]; + reg [71:0] r_dnw[10:20]; - task clear; - // Initialize memories to zero, - // avoid differences between 2-state and 4-state. - r_i = ~0; - foreach (r_upb[i]) r_upb[i] = ~0; - foreach (r_dnb[i]) r_dnb[i] = ~0; - foreach (r_ups[i]) r_ups[i] = ~0; - foreach (r_dns[i]) r_dns[i] = ~0; - foreach (r_upi[i]) r_upi[i] = ~0; - foreach (r_dni[i]) r_dni[i] = ~0; - foreach (r_upq[i]) r_upq[i] = ~0; - foreach (r_dnq[i]) r_dnq[i] = ~0; - foreach (r_upw[i]) r_upw[i] = ~0; - foreach (r_dnw[i]) r_dnw[i] = ~0; + task clear; + // Initialize memories to zero, + // avoid differences between 2-state and 4-state. + r_i = ~0; + foreach (r_upb[i]) r_upb[i] = ~0; + foreach (r_dnb[i]) r_dnb[i] = ~0; + foreach (r_ups[i]) r_ups[i] = ~0; + foreach (r_dns[i]) r_dns[i] = ~0; + foreach (r_upi[i]) r_upi[i] = ~0; + foreach (r_dni[i]) r_dni[i] = ~0; + foreach (r_upq[i]) r_upq[i] = ~0; + foreach (r_dnq[i]) r_dnq[i] = ~0; + foreach (r_upw[i]) r_upw[i] = ~0; + foreach (r_dnw[i]) r_dnw[i] = ~0; - // Open file - $fclose(file); - file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_fread.mem"}, "r"); - if ($feof(file)) $stop; - endtask + // Open file + $fclose(file); + file = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_sys_fread.mem"}, "r"); + if ($feof(file)) $stop; + endtask - task dump; - $write("Dump:"); - $write("\n r_i:"); $write(" %x",r_i); - $write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]); - $write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]); - $write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]); - $write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]); - $write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]); - $write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]); - $write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]); - $write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]); - $write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]); - $write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]); - $write("\n\n"); - endtask + task dump; + // verilog_format: off + $write("Dump:"); + $write("\n r_i:"); $write(" %x",r_i); + $write("\n r_upb:"); foreach (r_upb[i]) $write(" %x", r_upb[i]); + $write("\n r_dnb:"); foreach (r_dnb[i]) $write(" %x", r_dnb[i]); + $write("\n r_ups:"); foreach (r_ups[i]) $write(" %x", r_ups[i]); + $write("\n r_dns:"); foreach (r_dns[i]) $write(" %x", r_dns[i]); + $write("\n r_upi:"); foreach (r_upi[i]) $write(" %x", r_upi[i]); + $write("\n r_dni:"); foreach (r_dni[i]) $write(" %x", r_dni[i]); + $write("\n r_upq:"); foreach (r_upq[i]) $write(" %x", r_upq[i]); + $write("\n r_dnq:"); foreach (r_dnq[i]) $write(" %x", r_dnq[i]); + $write("\n r_upw:"); foreach (r_upw[i]) $write(" %x", r_upw[i]); + $write("\n r_dnw:"); foreach (r_dnw[i]) $write(" %x", r_dnw[i]); + $write("\n\n"); + // verilog_format: on + endtask - integer code; + integer code; - initial begin - clear; - code = $fread(r_i, file); `checkd(code, 4); - code = $fread(r_upb, file); `checkd(code, 11); - code = $fread(r_dnb, file); `checkd(code, 11); - code = $fread(r_ups, file); `checkd(code, 22); - code = $fread(r_dns, file); `checkd(code, 22); - code = $fread(r_upi, file); `checkd(code, 44); - code = $fread(r_dni, file); `checkd(code, 44); - code = $fread(r_upq, file); `checkd(code, 88); - code = $fread(r_dnq, file); `checkd(code, 88); - code = $fread(r_upw, file); `checkd(code, 99); - code = $fread(r_dnw, file); `checkd(code, 99); - dump; + initial begin + // verilog_format: off + clear; + code = $fread(r_i, file); `checkd(code, 4); + code = $fread(r_upb, file); `checkd(code, 11); + code = $fread(r_dnb, file); `checkd(code, 11); + code = $fread(r_ups, file); `checkd(code, 22); + code = $fread(r_dns, file); `checkd(code, 22); + code = $fread(r_upi, file); `checkd(code, 44); + code = $fread(r_dni, file); `checkd(code, 44); + code = $fread(r_upq, file); `checkd(code, 88); + code = $fread(r_dnq, file); `checkd(code, 88); + code = $fread(r_upw, file); `checkd(code, 99); + code = $fread(r_dnw, file); `checkd(code, 99); + dump; - clear; - code = $fread(r_upb, file, 15); `checkd(code, 6); - // Bug where fread in if() broke. - if ($fread(r_ups, file, 15, 2) != 4) $stop; - dump; + clear; + code = $fread(r_upb, file, 15); `checkd(code, 6); + code = $fread(r_dnb, file, 15); `checkd(code, 6); + code = $fread(r_upb, file, , 1); `checkd(code, 1); + code = $fread(r_dnb, file, , 1); `checkd(code, 1); + code = $fread(r_upb, file, 13, 1); `checkd(code, 1); + code = $fread(r_dnb, file, 13, 1); `checkd(code, 1); + // verilog_format: on - $write("*-* All Finished *-*\n"); - $finish; - end + // Bug where fread in if() broke. + if ($fread(r_ups, file, 15, 2) != 4) $stop; + dump; + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule