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Fix handling user-botch of %d to print real.

This commit is contained in:
Wilson Snyder 2019-12-08 22:48:44 -05:00
parent 62b0d15d2e
commit bd0eadb311
3 changed files with 7 additions and 0 deletions
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2
src/V3Number.cpp
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@ -741,6 +741,7 @@ vlsint32_t V3Number::toSInt() const {
vluint64_t V3Number::toUQuad() const { vluint64_t V3Number::toUQuad() const {
UASSERT(!isFourState(), "toUQuad with 4-state "<<*this); UASSERT(!isFourState(), "toUQuad with 4-state "<<*this);
// We allow wide numbers that represent values <= 64 bits // We allow wide numbers that represent values <= 64 bits
if (isDouble()) return static_cast<vluint64_t>(toDouble());
for (int i=2; i<words(); ++i) { for (int i=2; i<words(); ++i) {
if (m_value[i]) { if (m_value[i]) {
v3error("Value too wide for 64-bits expected in this context "<<*this); v3error("Value too wide for 64-bits expected in this context "<<*this);
@ -753,6 +754,7 @@ vluint64_t V3Number::toUQuad() const {
} }
vlsint64_t V3Number::toSQuad() const { vlsint64_t V3Number::toSQuad() const {
if (isDouble()) return static_cast<vlsint64_t>(toDouble());
vluint64_t v = toUQuad(); vluint64_t v = toUQuad();
vluint64_t signExtend = (-(v & (VL_ULL(1)<<(width()-1)))); vluint64_t signExtend = (-(v & (VL_ULL(1)<<(width()-1))));
vluint64_t extended = v | signExtend; vluint64_t extended = v | signExtend;

1
test_regress/t/t_display.out
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@ -49,4 +49,5 @@ extra argument: 0000000000000000
[0] Embedded <#013> return [0] Embedded <#013> return
[0] Embedded [0] Embedded
multiline multiline
log10(2) = 2
*-* All Finished *-* *-* All Finished *-*

4
test_regress/t/t_display.v
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@ -139,6 +139,10 @@ multiline", $time);
`ifndef NC // NC-Verilog 5.3 chokes on this test `ifndef NC // NC-Verilog 5.3 chokes on this test
if (str !== 32'h00_bf_11_0a) $stop; if (str !== 32'h00_bf_11_0a) $stop;
`endif `endif
// $itord conversion bug, note a %d instead of proper float
$display("log10(2) = %d", $log10(100));
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end