From bd0eadb311664d7ea7c11b3940a20228485dbee1 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 8 Dec 2019 22:48:44 -0500 Subject: [PATCH] Fix handling user-botch of %d to print real. --- src/V3Number.cpp | 2 ++ test_regress/t/t_display.out | 1 + test_regress/t/t_display.v | 4 ++++ 3 files changed, 7 insertions(+) diff --git a/src/V3Number.cpp b/src/V3Number.cpp index 5328da054..32d78bd63 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -741,6 +741,7 @@ vlsint32_t V3Number::toSInt() const { vluint64_t V3Number::toUQuad() const { UASSERT(!isFourState(), "toUQuad with 4-state "<<*this); // We allow wide numbers that represent values <= 64 bits + if (isDouble()) return static_cast(toDouble()); for (int i=2; i(toDouble()); vluint64_t v = toUQuad(); vluint64_t signExtend = (-(v & (VL_ULL(1)<<(width()-1)))); vluint64_t extended = v | signExtend; diff --git a/test_regress/t/t_display.out b/test_regress/t/t_display.out index 5ab2b8849..10667f059 100644 --- a/test_regress/t/t_display.out +++ b/test_regress/t/t_display.out @@ -49,4 +49,5 @@ extra argument: 0000000000000000 [0] Embedded <#013> return [0] Embedded multiline +log10(2) = 2 *-* All Finished *-* diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v index 87fff05bf..da6ab3f7c 100644 --- a/test_regress/t/t_display.v +++ b/test_regress/t/t_display.v @@ -139,6 +139,10 @@ multiline", $time); `ifndef NC // NC-Verilog 5.3 chokes on this test if (str !== 32'h00_bf_11_0a) $stop; `endif + + // $itord conversion bug, note a %d instead of proper float + $display("log10(2) = %d", $log10(100)); + $write("*-* All Finished *-*\n"); $finish; end