From b71abb003207ecadc284597ea5dd1eaa021f65b6 Mon Sep 17 00:00:00 2001 From: Yilou Wang Date: Fri, 20 Mar 2026 15:25:46 +0100 Subject: [PATCH] Fix `local::` false error in randomize() with on parameterized class (#6680) (#7293)` --- src/V3LinkDot.cpp | 2 +- test_regress/t/t_randomize_local_paramed.py | 21 +++++++ test_regress/t/t_randomize_local_paramed.v | 61 +++++++++++++++++++++ 3 files changed, 83 insertions(+), 1 deletion(-) create mode 100755 test_regress/t/t_randomize_local_paramed.py create mode 100644 test_regress/t/t_randomize_local_paramed.v diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 5fd0366f9..594bf174a 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -4663,7 +4663,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } if (nodep->name() == "local::") { - if (!m_randSymp) { + if (!m_randSymp && !m_randMethodCallp) { nodep->v3error("Illegal 'local::' outside 'randomize() with'" " (IEEE 1800-2023 18.7.1)"); m_ds.m_dotErr = true; diff --git a/test_regress/t/t_randomize_local_paramed.py b/test_regress/t/t_randomize_local_paramed.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randomize_local_paramed.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_local_paramed.v b/test_regress/t/t_randomize_local_paramed.v new file mode 100644 index 000000000..3b2c64d94 --- /dev/null +++ b/test_regress/t/t_randomize_local_paramed.v @@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +class item_cls #(type T = int); + rand T value; +endclass + +class multi_param_cls #(type T = int, int WIDTH = 8); + rand T data; + rand bit [WIDTH-1:0] mask; +endclass + +class driver_cls #(type T = int); + function int do_rand(T val); + item_cls#(T) itemp; + itemp = new(); + void'(itemp.randomize() with { value == local::val; }); + return (itemp.value == val) ? 32'd1 : 32'd0; + endfunction +endclass + +class multi_driver_cls #(type T = int, int WIDTH = 8); + function int do_rand(T val, bit [WIDTH-1:0] m); + multi_param_cls#(T, WIDTH) itemp; + itemp = new(); + void'(itemp.randomize() with { + data == local::val; + mask == local::m; + }); + return (itemp.data == val && itemp.mask == m) ? 32'd1 : 32'd0; + endfunction +endclass + +module t; + initial begin + driver_cls#(int) drvp; + multi_driver_cls#(int, 8) mdrvp; + + drvp = new(); + mdrvp = new(); + + repeat (20) begin + `checkd(drvp.do_rand(32'd42), 32'd1) + end + + repeat (20) begin + `checkd(mdrvp.do_rand(32'd99, 8'hAB), 32'd1) + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule