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Tests: Prefer --binary over timing multipliers

This commit is contained in:
Wilson Snyder 2026-05-11 18:41:09 -04:00
parent d2047e5bad
commit b27e7c02ee
3 changed files with 9 additions and 10 deletions
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3
test_regress/t/t_delay_timing.py
View File

@ -11,9 +11,8 @@ import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_delay.v"
test.main_time_multiplier = 10e-7 / 10e-9
test.compile(timing_loop=True, verilator_flags2=['--timing -Wno-ZERODLY'])
test.compile(verilator_flags2=['--binary -Wno-ZERODLY'])
test.execute()

12
test_regress/t/t_gate_basic.v
View File

@ -83,14 +83,16 @@ module t (
endspecify
`endif
// verilog_format: on
always @ (posedge clk) begin
if (cyc!=0) begin
if (cyc != 0) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (cyc == 1) begin
a <= 32'h18f6b034;
b <= 32'h834bf892;
end
if (cyc==2) begin
if (cyc == 2) begin
a <= 32'h529ab56f;
b <= 32'h7835a237;
if (bf !== 3'b100) $stop;
@ -105,7 +107,7 @@ module t (
if (xn0 !== 1'b1) $stop;
if (ba != 32'h18f6b034) $stop;
end
if (cyc==3) begin
if (cyc == 3) begin
if (bf !== 3'b111) $stop;
if (bfm != 3'b111) $stop;
if (ntm != 3'b000) $stop;
@ -117,7 +119,7 @@ module t (
if (xo0 !== 1'b0) $stop;
if (xn0 !== 1'b0) $stop;
end
if (cyc==4) begin
if (cyc == 4) begin
$write("*-* All Finished *-*\n");
$finish;
end

4
test_regress/t/t_gate_basic_timing.py
View File

@ -11,10 +11,8 @@ import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_gate_basic.v"
test.main_time_multiplier = 10e-7 / 10e-9
test.compile(timing_loop=True,
verilator_flags2=["--timing --timescale 10ns/1ns -Wno-RISEFALLDLY -Wno-SPECIFYIGN"])
test.compile(verilator_flags2=["--binary --timescale 10ns/1ns -Wno-RISEFALLDLY -Wno-SPECIFYIGN"])
test.execute()