diff --git a/test_regress/t/t_delay_timing.py b/test_regress/t/t_delay_timing.py
index 859b85f99..6018fde16 100755
--- a/test_regress/t/t_delay_timing.py
+++ b/test_regress/t/t_delay_timing.py
@@ -11,9 +11,8 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 test.top_filename = "t/t_delay.v"
-test.main_time_multiplier = 10e-7 / 10e-9
 
-test.compile(timing_loop=True, verilator_flags2=['--timing -Wno-ZERODLY'])
+test.compile(verilator_flags2=['--binary -Wno-ZERODLY'])
 
 test.execute()
 
diff --git a/test_regress/t/t_gate_basic.v b/test_regress/t/t_gate_basic.v
index eda9c1b74..546c779b0 100644
--- a/test_regress/t/t_gate_basic.v
+++ b/test_regress/t/t_gate_basic.v
@@ -83,14 +83,16 @@ module t (
   endspecify
 `endif
 
+  // verilog_format: on
+
   always @ (posedge clk) begin
-    if (cyc!=0) begin
+    if (cyc != 0) begin
       cyc <= cyc + 1;
-      if (cyc==1) begin
+      if (cyc == 1) begin
         a <= 32'h18f6b034;
         b <= 32'h834bf892;
       end
-      if (cyc==2) begin
+      if (cyc == 2) begin
         a <= 32'h529ab56f;
         b <= 32'h7835a237;
         if (bf !== 3'b100) $stop;
@@ -105,7 +107,7 @@ module t (
         if (xn0 !== 1'b1) $stop;
         if (ba != 32'h18f6b034) $stop;
       end
-      if (cyc==3) begin
+      if (cyc == 3) begin
         if (bf !== 3'b111) $stop;
         if (bfm != 3'b111) $stop;
         if (ntm != 3'b000) $stop;
@@ -117,7 +119,7 @@ module t (
         if (xo0 !== 1'b0) $stop;
         if (xn0 !== 1'b0) $stop;
       end
-      if (cyc==4) begin
+      if (cyc == 4) begin
         $write("*-* All Finished *-*\n");
         $finish;
       end
diff --git a/test_regress/t/t_gate_basic_timing.py b/test_regress/t/t_gate_basic_timing.py
index eadcbdea3..d6b5b15df 100755
--- a/test_regress/t/t_gate_basic_timing.py
+++ b/test_regress/t/t_gate_basic_timing.py
@@ -11,10 +11,8 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 test.top_filename = "t/t_gate_basic.v"
-test.main_time_multiplier = 10e-7 / 10e-9
 
-test.compile(timing_loop=True,
-             verilator_flags2=["--timing --timescale 10ns/1ns -Wno-RISEFALLDLY -Wno-SPECIFYIGN"])
+test.compile(verilator_flags2=["--binary --timescale 10ns/1ns -Wno-RISEFALLDLY -Wno-SPECIFYIGN"])
 
 test.execute()