Commentary: Changes update

Changes

@@ -22,8 +22,10 @@ Verilator 5.049 devel
 * Support randsequence production function ports (#7522). [Yilou Wang]
 * Support followed-by operators `#-#` and `#=#` in properties (#7523). [Yilou Wang]
 * Support TERMUX (#7559). [Laurent CHARRIER]
+* Support SVA goto repetition with range `[->M:N]` (#7569). [Yilou Wang]
 * Add peak memory usage to `--stats`. [Geza Lore, Testorrent USA, Inc.]
-* Improve `--coverage-fsm` (#7490) (#7529). [Yogish Sekhar]
+* Add error on mixed-initialization (#7352) (#7357).
+* Improve `--coverage-fsm` (#7490) (#7529) (#7561). [Yogish Sekhar]
 * Change `+verilator+seed` to default to 1, and 0 to randomly select (#7325) (#7516). [Miguel]
 * Change JSON to include parameter constant mnemonics for FSM Coverage (#7531). [Yogish Sekhar]
 * Optimize additional DFG peephole cases (#7553). [Varun Koyyalagunta, Testorrent USA, Inc.]

docs/guide/simulating.rst

@@ -238,8 +238,8 @@ encodings in these common forms:
 Simple input guards are supported when they appear inside a recognized
 state branch, or as a top-level conjunction containing exactly one state
 comparison, such as ``(state_q == IDLE) && ready``. Directly traceable
-predecoded state aliases, such as ``assign idle_state = (state_q == IDLE)``,
-may also be used in these guarded predicates.
+pre-decoded state aliases, such as ``assign idle_state = (state_q ==
+IDLE)``, may also be used in these guarded predicates.
 
 Verilator does not claim broad support for arbitrary predicate
 decomposition, one-hot inference, helper-function next-state recovery,

docs/spelling.txt

@@ -579,6 +579,7 @@ Yujia
 Yurii
 Zaruba
 Zhang
+Zhi
 abirkmanis
 accessor
 accessors

test_regress/t/t_fuzz_mixed_initialization.out

@@ -1,10 +0,0 @@
-%Error-CONTASSINIT: t/t_fuzz_mixed_initialization.v:11:15: Continuous assignment to variable with initial value: 'a'
-                                                         : ... note: In instance 't'
-                                                         : ... Location of variable initialization
-   11 |     logic a = 1'b0;    
-      |               ^~~~
-                    t/t_fuzz_mixed_initialization.v:12:12: ... Location of continuous assignment
-   12 |     assign a = 1'b1;   
-      |            ^
-                    ... For error description see https://verilator.org/warn/CONTASSINIT?v=latest
-%Error: Exiting due to

test_regress/t/t_var_mixed_initialization_bad.out

@@ -0,0 +1,10 @@
+%Error-CONTASSINIT: t/t_var_mixed_initialization_bad.v:11:13: Continuous assignment to variable with initial value: 'a'
+                                                            : ... note: In instance 't'
+                                                            : ... Location of variable initialization
+   11 |   logic a = 1'b0;   
+      |             ^~~~
+                    t/t_var_mixed_initialization_bad.v:12:10: ... Location of continuous assignment
+   12 |   assign a = 1'b1;   
+      |          ^
+                    ... For error description see https://verilator.org/warn/CONTASSINIT?v=latest
+%Error: Exiting due to

test_regress/t/t_var_mixed_initialization_bad.v

@@ -8,9 +8,9 @@ module t (
     output wire out
 );
 
-    logic a = 1'b0;   // declaration initialization
-    assign a = 1'b1;  // continuous assignment
+  logic a = 1'b0;  // declaration initialization
+  assign a = 1'b1;  // continuous assignment
 
-    assign out = a;
+  assign out = a;
 
 endmodule