From a0446979904d0d2ca1ac4cc557ff62d9f5f3b1c5 Mon Sep 17 00:00:00 2001
From: Todd Strader <todd.strader@gmail.com>
Date: Fri, 6 Jun 2025 21:13:31 -0400
Subject: [PATCH] Fix signed cast (#6912) (#6068)

---
 src/V3Width.cpp                 |  8 +++++---
 test_regress/t/t_cast_signed.py | 18 ++++++++++++++++++
 test_regress/t/t_cast_signed.v  | 23 +++++++++++++++++++++++
 3 files changed, 46 insertions(+), 3 deletions(-)
 create mode 100755 test_regress/t/t_cast_signed.py
 create mode 100644 test_regress/t/t_cast_signed.v

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index c1eecc786..ef28884e3 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2128,9 +2128,11 @@ class WidthVisitor final : public VNVisitor {
             if (debug() >= 9) nodep->dumpTree("-  CastPre: ");
             // if (debug()) nodep->backp()->dumpTree("-  CastPreUpUp: ");
             if (AstSigned* const fromp = VN_CAST(nodep->fromp(), Signed)) {
-                AstNode* const lhsp = fromp->lhsp()->unlinkFrBack();
-                fromp->replaceWith(lhsp);
-                VL_DO_DANGLING(fromp->deleteTree(), fromp);
+                if (VN_IS(fromp->lhsp(), NodeStream)) {
+                    AstNode* const lhsp = fromp->lhsp()->unlinkFrBack();
+                    fromp->replaceWith(lhsp);
+                    VL_DO_DANGLING(fromp->deleteTree(), fromp);
+                }
             }
             userIterateAndNext(nodep->fromp(), WidthVP{SELF, PRELIM}.p());
             if (debug() >= 9) nodep->dumpTree("-  CastDit: ");
diff --git a/test_regress/t/t_cast_signed.py b/test_regress/t/t_cast_signed.py
new file mode 100755
index 000000000..c39e83d77
--- /dev/null
+++ b/test_regress/t/t_cast_signed.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios("simulator")
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_cast_signed.v b/test_regress/t/t_cast_signed.v
new file mode 100644
index 000000000..d9cc53979
--- /dev/null
+++ b/test_regress/t/t_cast_signed.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   logic [7:0] smaller;
+   logic [15:0] bigger;
+   typedef logic [15:0] bigger_t;
+
+   initial begin
+      smaller = 8'hfa;
+      bigger = bigger_t'(signed'(smaller));
+      $display("%x", bigger); // NOCOMMIT
+      if (bigger != 16'hfffa) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule