mirror of
https://github.com/verilator/verilator.git
synced 2026-10-02 16:13:34 +02:00
+5
-3
@@ -3652,6 +3652,7 @@ class RandomizeVisitor final : public VNVisitor {
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// STATE
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V3UniqueNames m_inlineUniqueNames; // For generating unique function names
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V3UniqueNames m_randArrayUniqueNames{"__Vrandarr"}; // Random array loop indices
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V3UniqueNames m_modeUniqueNames{"__Vmode"}; // For generating unique rand/constraint
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// mode state var names
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V3UniqueNames m_inlineUniqueStdName{"__VStdrand"};
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@@ -4234,15 +4235,14 @@ class RandomizeVisitor final : public VNVisitor {
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}
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AstNodeStmt* createArrayForeachLoop(FileLine* const fl, AstNodeDType* const dtypep,
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AstNodeExpr* exprp, AstVar* const outputVarp) {
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V3UniqueNames uniqueNames{"__Vrandarr"};
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AstNodeDType* tempDTypep = dtypep;
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AstVar* randLoopIndxp = nullptr;
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auto createLoopIndex = [&](AstNodeDType* tempDTypep) {
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if (VN_IS(tempDTypep, AssocArrayDType)) {
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return new AstVar{fl, VVarType::VAR, uniqueNames.get(""),
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return new AstVar{fl, VVarType::VAR, m_randArrayUniqueNames.get(""),
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VN_AS(tempDTypep, AssocArrayDType)->keyDTypep()};
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}
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return new AstVar{fl, VVarType::VAR, uniqueNames.get(""),
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return new AstVar{fl, VVarType::VAR, m_randArrayUniqueNames.get(""),
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dtypep->findBasicDType(VBasicDTypeKwd::UINT32)};
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};
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AstNodeExpr* tempElementp = nullptr;
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@@ -5675,8 +5675,10 @@ class RandomizeVisitor final : public VNVisitor {
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void visit(AstNodeModule* nodep) override {
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VL_RESTORER(m_modp);
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VL_RESTORER(m_randCaseNum);
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VL_RESTORER_COPY(m_randArrayUniqueNames);
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m_modp = nodep;
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m_randCaseNum = 0;
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m_randArrayUniqueNames.reset();
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iterateChildren(nodep);
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}
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void visit(AstNodeFTask* nodep) override {
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+18
@@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@@ -0,0 +1,24 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Verilator Authors.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {
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rand bit values[];
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} Element;
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class Container;
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rand Element elements[];
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endclass
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module t;
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initial begin
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automatic Container object = new;
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void'(object.randomize());
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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