diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index 70d931543..88550f41d 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -3652,6 +3652,7 @@ class RandomizeVisitor final : public VNVisitor { // STATE V3UniqueNames m_inlineUniqueNames; // For generating unique function names + V3UniqueNames m_randArrayUniqueNames{"__Vrandarr"}; // Random array loop indices V3UniqueNames m_modeUniqueNames{"__Vmode"}; // For generating unique rand/constraint // mode state var names V3UniqueNames m_inlineUniqueStdName{"__VStdrand"}; @@ -4234,15 +4235,14 @@ class RandomizeVisitor final : public VNVisitor { } AstNodeStmt* createArrayForeachLoop(FileLine* const fl, AstNodeDType* const dtypep, AstNodeExpr* exprp, AstVar* const outputVarp) { - V3UniqueNames uniqueNames{"__Vrandarr"}; AstNodeDType* tempDTypep = dtypep; AstVar* randLoopIndxp = nullptr; auto createLoopIndex = [&](AstNodeDType* tempDTypep) { if (VN_IS(tempDTypep, AssocArrayDType)) { - return new AstVar{fl, VVarType::VAR, uniqueNames.get(""), + return new AstVar{fl, VVarType::VAR, m_randArrayUniqueNames.get(""), VN_AS(tempDTypep, AssocArrayDType)->keyDTypep()}; } - return new AstVar{fl, VVarType::VAR, uniqueNames.get(""), + return new AstVar{fl, VVarType::VAR, m_randArrayUniqueNames.get(""), dtypep->findBasicDType(VBasicDTypeKwd::UINT32)}; }; AstNodeExpr* tempElementp = nullptr; @@ -5675,8 +5675,10 @@ class RandomizeVisitor final : public VNVisitor { void visit(AstNodeModule* nodep) override { VL_RESTORER(m_modp); VL_RESTORER(m_randCaseNum); + VL_RESTORER_COPY(m_randArrayUniqueNames); m_modp = nodep; m_randCaseNum = 0; + m_randArrayUniqueNames.reset(); iterateChildren(nodep); } void visit(AstNodeFTask* nodep) override { diff --git a/test_regress/t/t_randomize_nested_dynamic_array.py b/test_regress/t/t_randomize_nested_dynamic_array.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_randomize_nested_dynamic_array.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_nested_dynamic_array.v b/test_regress/t/t_randomize_nested_dynamic_array.v new file mode 100644 index 000000000..f91309f98 --- /dev/null +++ b/test_regress/t/t_randomize_nested_dynamic_array.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2026 by Verilator Authors. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +typedef struct { + rand bit values[]; +} Element; + +class Container; + rand Element elements[]; +endclass + +module t; + initial begin + automatic Container object = new; + void'(object.randomize()); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule