[#72179] add wip example for SAIF trace
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2025 by Antmicro. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (
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// Outputs
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state,
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// Inputs
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clk);
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input clk;
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reg rst;
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output [7:0] state;
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counter c0 (
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.clk (clk),
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.rst (rst),
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.out (state));
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int cyc;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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rst <= 1;
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end
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else if (cyc == 10) begin
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rst <= 0;
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end
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else if (cyc == 11) begin
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rst <= 1;
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end
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end
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endmodule
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module counter (
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input clk,
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input rst,
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output reg[7:0] out);
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always @ (posedge clk) begin
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if (!rst)
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out <= 0;
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else
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out <= out + 1;
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end
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endmodule
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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#include <verilated_saif_c.h>
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#include <memory>
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#include "Vcounter.h"
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int errors = 0;
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unsigned long long main_time = 0;
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double sc_time_stamp() { return static_cast<double>(main_time); }
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const char* trace_name() {
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static char name[1000];
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VL_SNPRINTF(name, 1000, "simx.saif");
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return name;
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}
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int main(int argc, char** argv) {
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Verilated::debug(0);
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Verilated::traceEverOn(true);
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Verilated::commandArgs(argc, argv);
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std::unique_ptr<Vcounter> top{new Vcounter};
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std::unique_ptr<VerilatedSaifC> tfp{new VerilatedSaifC};
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static constexpr int SIMULATION_DURATION{199};
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top->trace(tfp.get(), SIMULATION_DURATION);
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tfp->open(trace_name());
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top->clk = 0;
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while (main_time < SIMULATION_DURATION) {
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top->clk = !top->clk;
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top->eval();
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tfp->dump(static_cast<unsigned int>(main_time));
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++main_time;
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}
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tfp->close();
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top->final();
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tfp.reset();
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top.reset();
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printf("*-* All Finished *-*\n");
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return errors;
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}
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