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[#72179] add t_trace_saif test

This commit is contained in:
Mateusz Gancarz 2025-02-13 08:45:55 +01:00
parent 7ea3f83adf
commit a9700592b9
3 changed files with 204 additions and 0 deletions
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22
test_regress/t/t_trace_saif.py Executable file
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt_all')
test.top_filename = "t/t_trace_saif.v"
test.compile(v_flags2=["--trace-saif"])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()

86
test_regress/t/t_trace_saif.saif Normal file
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(SAIFILE
(SAIFVERSION "2.0")
(DIRECTION "backward")
(DESIGN "foo")
(PROGRAM_NAME "Verilator")
(VERSION "5.032")
(DIVIDER .)
(TIMESCALE 1ps)
(DURATION 1000)
(INSTANCE foo (NET
(i[1] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1))
(i[0] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(i[1] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(state_array[2][0] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48))
(state_array[2][1] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_array[2][2] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_array[2][3] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_array[2][4] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47))
(state_array[1][0] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 47))
(state_array[1][1] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_array[1][2] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_array[1][3] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
(state_array[1][4] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_array[0][0] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_array[0][1] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
(state_array[0][2] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_array[0][3] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
(state_array[0][4] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
(state_w[0] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_w[1] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_w[2] (T0 430) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46))
(state_w[3] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47))
(state_w[4] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48))
(fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
(state[0] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
(state[1] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
(state[2] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
(state[3] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
(state[4] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
(cyc[0] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
(cyc[1] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
(cyc[2] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25))
(cyc[3] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12))
(cyc[4] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6))
(cyc[5] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3))
(cyc[6] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[0] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[1] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[2] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[3] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[5] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[6] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[7] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[9] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[10] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[11] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[12] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[13] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[15] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[16] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[17] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[18] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[19] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[21] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[22] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[23] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[25] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[26] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[27] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[28] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[29] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[31] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_longint[32] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
(rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_parameter[0] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_parameter[1] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_parameter[3] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_parameter[4] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_parameter[5] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_parameter[6] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_lparam[3] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_lparam[6] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_lparam[7] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
(fst_lparam[8] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
)))

96
test_regress/t/t_trace_saif.v Normal file
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
state,
// Inputs
clk
);
input clk;
int cyc;
reg rstn;
output [4:0] state;
integer fst_integer;
bit fst_bit;
logic fst_logic;
int fst_int;
shortint fst_shortint;
reg [128:0] fst_longint;
byte fst_byte;
parameter fst_parameter = 123;
localparam fst_lparam = 456;
supply0 fst_supply0;
supply1 fst_supply1;
wire fst_wire;
Test test (/*AUTOINST*/
// Outputs
.state (state[4:0]),
// Inputs
.clk (clk),
.rstn (rstn));
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
fst_longint [ 0 +: 128 ] <= 128'hbeefbeefbeefbeef;
if (cyc==0) begin
// Setup
rstn <= ~'1;
end
else if (cyc<10) begin
rstn <= ~'1;
end
else if (cyc<90) begin
rstn <= ~'0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input clk,
input rstn,
output logic [4:0] state
);
logic [4:0] state_w;
logic [4:0] state_array [3];
assign state = state_array[0];
always_comb begin
state_w[4] = state_array[2][0];
state_w[3] = state_array[2][4];
state_w[2] = state_array[2][3] ^ state_array[2][0];
state_w[1] = state_array[2][2];
state_w[0] = state_array[2][1];
end
always_ff @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 3; i++)
state_array[i] <= 'b1;
end
else begin
for (int i = 0; i < 2; i++)
state_array[i] <= state_array[i+1];
state_array[2] <= state_w;
end
end
endmodule