52 lines
985 B
Systemverilog
52 lines
985 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2025 by Antmicro. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (
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// Outputs
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state,
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// Inputs
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clk);
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input clk;
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reg rst;
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output [7:0] state;
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counter c0 (
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.clk (clk),
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.rst (rst),
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.out (state));
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int cyc;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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rst <= 1;
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end
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else if (cyc == 10) begin
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rst <= 0;
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end
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else if (cyc == 11) begin
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rst <= 1;
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end
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end
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endmodule
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module counter (
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input clk,
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input rst,
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output reg[7:0] out);
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always @ (posedge clk) begin
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if (!rst)
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out <= 0;
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else
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out <= out + 1;
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end
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endmodule
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