luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'master' of ssh://git-verilator-wsnyder/git/verilator

This commit is contained in:
Wilson Snyder 2011-11-28 09:48:14 -05:00
parent a2490a55a9 20189f5191
commit 8ff2bf51c5
6 changed files with 18 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Changes
View File

@ -4,7 +4,12 @@ The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks! indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.825*** * Verilator 3.831****
**** Suppress VARHIDDEN on dpi import arguments. [Ruben Diez]
* Verilator 3.830 2011/11/27
** With "--language VAMS" support a touch of Verilog AMS. [Holger Waechtler] ** With "--language VAMS" support a touch of Verilog AMS. [Holger Waechtler]

2
configure.ac
View File

@ -4,7 +4,7 @@
# redistribute it and/or modify it under the terms of either the GNU Lesser # redistribute it and/or modify it under the terms of either the GNU Lesser
# General Public License Version 3 or the Perl Artistic License Version 2.0. # General Public License Version 3 or the Perl Artistic License Version 2.0.
AC_INIT([Verilator],[3.825 devel]) AC_INIT([Verilator],[3.831 devel])
AC_CONFIG_HEADER(src/config_build.h) AC_CONFIG_HEADER(src/config_build.h)
AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk) AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk)

3
src/V3Link.cpp
View File

@ -319,7 +319,8 @@ private:
} }
} else { } else {
// User can disable the message at either point // User can disable the message at either point
if (!nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN) if (!(m_ftaskp && m_ftaskp->dpiImport())
&& !nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)
&& !foundp->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)) { && !foundp->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)) {
nodep->v3warn(VARHIDDEN,"Declaration of signal hides declaration in upper scope: "<<nodep->name()); nodep->v3warn(VARHIDDEN,"Declaration of signal hides declaration in upper scope: "<<nodep->name());
foundp->v3warn(VARHIDDEN,"... Location of original declaration"); foundp->v3warn(VARHIDDEN,"... Location of original declaration");

1
src/verilog.y
View File

@ -1375,6 +1375,7 @@ non_port_module_item<nodep>: // ==IEEE: non_port_module_item
generate_region<nodep>: // ==IEEE: generate_region generate_region<nodep>: // ==IEEE: generate_region
yGENERATE genTopBlock yENDGENERATE { $$ = new AstGenerate($1, $2); } yGENERATE genTopBlock yENDGENERATE { $$ = new AstGenerate($1, $2); }
| yGENERATE yENDGENERATE { $$ = NULL; }
; ;
module_or_generate_item<nodep>: // ==IEEE: module_or_generate_item module_or_generate_item<nodep>: // ==IEEE: module_or_generate_item

3
test_regress/t/t_gen_for.v
View File

@ -93,6 +93,9 @@ module paramed (/*AUTOARG*/
for (i=0; i<3; i=i+1) begin end for (i=0; i<3; i=i+1) begin end
endgenerate endgenerate
generate
endgenerate
generate generate
if (MODE==0) begin if (MODE==0) begin
// Flip bitorder, direct assign method // Flip bitorder, direct assign method

5
test_regress/t/t_var_bad_hide2.v
View File

@ -5,6 +5,11 @@
module t; module t;
// Arguable, but we won't throw a hidden warning on tcp_port
parameter tcp_port = 5678;
import "DPI-C" function int dpii_func ( input integer tcp_port,
output longint obj );
// 't' is hidden:
integer t; integer t;
endmodule endmodule