From 4100f20a6941c01a28b8e25f8c7a3659a5629d76 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 27 Nov 2011 10:37:23 -0500 Subject: [PATCH 1/4] Version bump --- Changes | 2 +- configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Changes b/Changes index 85fb986b2..a2709644c 100644 --- a/Changes +++ b/Changes @@ -4,7 +4,7 @@ The contributors that suggested a given feature are shown in []. [by ...] indicates the contributor was also the author of the fix; Thanks! -* Verilator 3.825*** +* Verilator 3.830 2011/11/27 ** With "--language VAMS" support a touch of Verilog AMS. [Holger Waechtler] diff --git a/configure.ac b/configure.ac index 0e1d4f730..8a98b8539 100644 --- a/configure.ac +++ b/configure.ac @@ -4,7 +4,7 @@ # redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. -AC_INIT([Verilator],[3.825 devel]) +AC_INIT([Verilator],[3.830]) AC_CONFIG_HEADER(src/config_build.h) AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk) From ad4edf6c681f68dfef0ac701a7d8d5a9cd8440d3 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 27 Nov 2011 10:39:30 -0500 Subject: [PATCH 2/4] Postrelease --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 8a98b8539..63cbbb714 100644 --- a/configure.ac +++ b/configure.ac @@ -4,7 +4,7 @@ # redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. -AC_INIT([Verilator],[3.830]) +AC_INIT([Verilator],[3.831 devel]) AC_CONFIG_HEADER(src/config_build.h) AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk) From 06b796c6bdef4597049e58afc9a825bf8f5228bb Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 27 Nov 2011 12:03:22 -0500 Subject: [PATCH 3/4] Suppress VARHIDDEN on dpi import arguments. --- Changes | 5 +++++ src/V3Link.cpp | 3 ++- test_regress/t/t_var_bad_hide2.v | 5 +++++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/Changes b/Changes index a2709644c..39befa53f 100644 --- a/Changes +++ b/Changes @@ -4,6 +4,11 @@ The contributors that suggested a given feature are shown in []. [by ...] indicates the contributor was also the author of the fix; Thanks! +* Verilator 3.831**** + +**** Suppress VARHIDDEN on dpi import arguments. [Ruben Diez] + + * Verilator 3.830 2011/11/27 ** With "--language VAMS" support a touch of Verilog AMS. [Holger Waechtler] diff --git a/src/V3Link.cpp b/src/V3Link.cpp index f273b7b1c..2d85c5671 100644 --- a/src/V3Link.cpp +++ b/src/V3Link.cpp @@ -319,7 +319,8 @@ private: } } else { // User can disable the message at either point - if (!nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN) + if (!(m_ftaskp && m_ftaskp->dpiImport()) + && !nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN) && !foundp->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)) { nodep->v3warn(VARHIDDEN,"Declaration of signal hides declaration in upper scope: "<name()); foundp->v3warn(VARHIDDEN,"... Location of original declaration"); diff --git a/test_regress/t/t_var_bad_hide2.v b/test_regress/t/t_var_bad_hide2.v index b5f5d01d1..1ae2317e6 100644 --- a/test_regress/t/t_var_bad_hide2.v +++ b/test_regress/t/t_var_bad_hide2.v @@ -5,6 +5,11 @@ module t; + // Arguable, but we won't throw a hidden warning on tcp_port + parameter tcp_port = 5678; + import "DPI-C" function int dpii_func ( input integer tcp_port, + output longint obj ); + // 't' is hidden: integer t; endmodule From 20189f519176b97b0940f0c08028e05b69c68615 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 28 Nov 2011 07:49:36 -0500 Subject: [PATCH 4/4] Fix empty generate region, bug422. --- src/verilog.y | 1 + test_regress/t/t_gen_for.v | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/verilog.y b/src/verilog.y index 802f9a6fe..58c28f93e 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1375,6 +1375,7 @@ non_port_module_item: // ==IEEE: non_port_module_item generate_region: // ==IEEE: generate_region yGENERATE genTopBlock yENDGENERATE { $$ = new AstGenerate($1, $2); } + | yGENERATE yENDGENERATE { $$ = NULL; } ; module_or_generate_item: // ==IEEE: module_or_generate_item diff --git a/test_regress/t/t_gen_for.v b/test_regress/t/t_gen_for.v index 174b4b9a2..ad6d44527 100644 --- a/test_regress/t/t_gen_for.v +++ b/test_regress/t/t_gen_for.v @@ -93,6 +93,9 @@ module paramed (/*AUTOARG*/ for (i=0; i<3; i=i+1) begin end endgenerate + generate + endgenerate + generate if (MODE==0) begin // Flip bitorder, direct assign method