diff --git a/Changes b/Changes
index 85fb986b2..39befa53f 100644
--- a/Changes
+++ b/Changes
@@ -4,7 +4,12 @@ The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
 
-* Verilator 3.825***
+* Verilator 3.831****
+
+****  Suppress VARHIDDEN on dpi import arguments.  [Ruben Diez]
+
+
+* Verilator 3.830 2011/11/27
 
 **   With "--language VAMS" support a touch of Verilog AMS.  [Holger Waechtler]
 
diff --git a/configure.ac b/configure.ac
index 0e1d4f730..63cbbb714 100644
--- a/configure.ac
+++ b/configure.ac
@@ -4,7 +4,7 @@
 # redistribute it and/or modify it under the terms of either the GNU Lesser
 # General Public License Version 3 or the Perl Artistic License Version 2.0.
 
-AC_INIT([Verilator],[3.825 devel])
+AC_INIT([Verilator],[3.831 devel])
 AC_CONFIG_HEADER(src/config_build.h)
 AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk)
 
diff --git a/src/V3Link.cpp b/src/V3Link.cpp
index f273b7b1c..2d85c5671 100644
--- a/src/V3Link.cpp
+++ b/src/V3Link.cpp
@@ -319,7 +319,8 @@ private:
 		    }
 		} else {
 		    // User can disable the message at either point
-		    if (!nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)
+		    if (!(m_ftaskp && m_ftaskp->dpiImport())
+			&& !nodep->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)
 			&& !foundp->fileline()->warnIsOff(V3ErrorCode::VARHIDDEN)) {
 			nodep->v3warn(VARHIDDEN,"Declaration of signal hides declaration in upper scope: "<<nodep->name());
 			foundp->v3warn(VARHIDDEN,"... Location of original declaration");
diff --git a/src/verilog.y b/src/verilog.y
index 802f9a6fe..58c28f93e 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1375,6 +1375,7 @@ non_port_module_item<nodep>:	// ==IEEE: non_port_module_item
 
 generate_region<nodep>:		// ==IEEE: generate_region
 		yGENERATE genTopBlock yENDGENERATE	{ $$ = new AstGenerate($1, $2); }
+	|	yGENERATE yENDGENERATE			{ $$ = NULL; }
 	;
 
 module_or_generate_item<nodep>:	// ==IEEE: module_or_generate_item
diff --git a/test_regress/t/t_gen_for.v b/test_regress/t/t_gen_for.v
index 174b4b9a2..ad6d44527 100644
--- a/test_regress/t/t_gen_for.v
+++ b/test_regress/t/t_gen_for.v
@@ -93,6 +93,9 @@ module paramed (/*AUTOARG*/
       for (i=0; i<3; i=i+1) begin end
    endgenerate
 
+   generate
+   endgenerate
+
    generate
       if (MODE==0) begin
 	 // Flip bitorder, direct assign method
diff --git a/test_regress/t/t_var_bad_hide2.v b/test_regress/t/t_var_bad_hide2.v
index b5f5d01d1..1ae2317e6 100644
--- a/test_regress/t/t_var_bad_hide2.v
+++ b/test_regress/t/t_var_bad_hide2.v
@@ -5,6 +5,11 @@
 
 module t;
 
+   // Arguable, but we won't throw a hidden warning on tcp_port
+   parameter tcp_port  = 5678;
+   import "DPI-C" function int dpii_func ( input integer  tcp_port,
+                                           output longint obj );
+   // 't' is hidden:
    integer t;
 
 endmodule