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Tests: Reformat some tests to mostly verilog-format standard. No test functional change.

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This commit is contained in:
Wilson Snyder
2026-09-27 13:41:11 -04:00
parent f691cd1936
commit 6956befd29
71 changed files with 721 additions and 485 deletions
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test_regress/t/t_assert_assert.v
+2 -2
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@@ -23,11 +23,11 @@ module t (
int cnt_ff;
assert property (@(negedge clk) disable iff (value[1]) value[2]) begin
assert (value[0])++cnt_tt;
assert (value[0]) ++cnt_tt;
else ++cnt_tf;
end
else begin
assert (value[0])++cnt_ft;
assert (value[0]) ++cnt_ft;
else ++cnt_ff;
end
test_regress/t/t_assert_pre.v
+1 -1
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@@ -36,7 +36,7 @@ module t (
assert property (@(e) not toggle) begin
`checkh(inc2, 0);
inc2++;
`checkh(inc2,1);
`checkh(inc2, 1);
end
event e;
test_regress/t/t_class_member_sens.v
+1 -1
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@@ -19,7 +19,7 @@ module t (
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1)->ec.e;
if (cyc == 1) ->ec.e;
else if (cyc == 2) begin
$write("*-* All Finished *-*\n");
$finish;
test_regress/t/t_constraint_dist_weight.v
+45 -8
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@@ -12,40 +12,77 @@
class DistScalar;
rand bit [7:0] x;
constraint c { x dist { 8'd0 := 1, 8'd255 := 3 }; }
constraint c {
x dist {
8'd0 := 1,
8'd255 := 3
};
}
endclass
class DistRange;
rand bit [7:0] x;
constraint c { x dist { [8'd0:8'd9] :/ 1, [8'd10:8'd19] :/ 3 }; }
constraint c {
x dist {
[8'd0 : 8'd9] :/ 1,
[8'd10 : 8'd19] :/ 3
};
}
endclass
class DistZeroWeight;
rand bit [7:0] x;
constraint c { x dist { 8'd0 := 0, 8'd1 := 1, 8'd2 := 1 }; }
constraint c {
x dist {
8'd0 := 0,
8'd1 := 1,
8'd2 := 1
};
}
endclass
class DistAllZeroWeight;
rand bit [7:0] x;
constraint c { x dist { 8'd0 := 0, 8'd1 := 0, 8'd2 := 0 }; }
constraint c {
x dist {
8'd0 := 0,
8'd1 := 0,
8'd2 := 0
};
}
endclass
class DistVarWeight;
rand bit [7:0] x;
int w1, w2;
constraint c { x dist { 8'd0 := w1, 8'd255 := w2 }; }
constraint c {
x dist {
8'd0 := w1,
8'd255 := w2
};
}
endclass
class DistVarWeightRange;
rand bit [7:0] x;
int w1, w2;
constraint c { x dist { [8'd0:8'd9] :/ w1, [8'd10:8'd19] :/ w2 }; }
constraint c {
x dist {
[8'd0 : 8'd9] :/ w1,
[8'd10 : 8'd19] :/ w2
};
}
endclass
class DistVarWeightWithExclusion;
rand bit [7:0] x;
constraint c { x dist { 8'd13 := 10, 8'd10 := 2 }; }
constraint excl { x != 8'd13; }
constraint c {
x dist {
8'd13 := 10,
8'd10 := 2
};
}
constraint excl {x != 8'd13;}
endclass
module t;
test_regress/t/t_constraint_dynarray_randmode.v
+3 -5
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@@ -9,21 +9,19 @@
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
typedef struct {
rand int value;
} entry_t;
typedef struct {rand int value;} entry_t;
class Container;
rand entry_t items[];
constraint c_value { items[0].value == 0; }
constraint c_value {items[0].value == 0;}
endclass
module t;
initial begin
automatic Container obj = new;
automatic int randomize_result;
repeat(20) begin
repeat (20) begin
obj.items = new[1];
obj.items[0].value = 0;
obj.items.rand_mode(0);
test_regress/t/t_constraint_unq_arr.v
+21 -18
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@@ -14,28 +14,28 @@ endclass
class C extends Subclass;
rand int arr[];
function new ();
function new();
arr = new[10];
sub_arr = new[10];
endfunction
function void check_unique();
// dynamic array inside class
for (int i = 0; i < $size(arr); i++) begin
for (int j = i + 1; j < $size(arr); j++) begin
if (arr[i] == arr[j]) begin
$error("UNIQUENESS VIOLATION: arr[%0d] == arr[%0d] == 0x%h", i, j, arr[i]);
end
// dynamic array inside class
for (int i = 0; i < $size(arr); i++) begin
for (int j = i + 1; j < $size(arr); j++) begin
if (arr[i] == arr[j]) begin
$error("UNIQUENESS VIOLATION: arr[%0d] == arr[%0d] == 0x%h", i, j, arr[i]);
end
end
// dynamic array inside base class
for (int i = 0; i < $size(sub_arr); i++) begin
for (int j = i + 1; j < $size(sub_arr); j++) begin
if (sub_arr[i] == sub_arr[j]) begin
$error("UNIQUENESS VIOLATION: arr[%0d] == arr[%0d] == 0x%h", i, j, arr[i]);
end
end
// dynamic array inside base class
for (int i = 0; i < $size(sub_arr); i++) begin
for (int j = i + 1; j < $size(sub_arr); j++) begin
if (sub_arr[i] == sub_arr[j]) begin
$error("UNIQUENESS VIOLATION: arr[%0d] == arr[%0d] == 0x%h", i, j, arr[i]);
end
end
end
endfunction
constraint c {
@@ -120,7 +120,8 @@ module t;
continue;
end
if (multiarr0[i] == multiarr0[j]) begin
$error("UNIQUENESS VIOLATION: multiarr0[%0d] == multiarr0[%0d] == 0x%h", i, j, multiarr0[i]);
$error("UNIQUENESS VIOLATION: multiarr0[%0d] == multiarr0[%0d] == 0x%h", i, j,
multiarr0[i]);
end
end
end
@@ -130,14 +131,16 @@ module t;
continue;
end
if (multiarr1[i] == multiarr1[j]) begin
$error("UNIQUENESS VIOLATION: multiarr1[%0d] == multiarr1[%0d] == 0x%h", i, j, multiarr1[i]);
$error("UNIQUENESS VIOLATION: multiarr1[%0d] == multiarr1[%0d] == 0x%h", i, j,
multiarr1[i]);
end
end
end
foreach (multiarr1[i]) begin
foreach (multiarr0[j]) begin
if (multiarr0[i] == multiarr1[j]) begin
$error("UNIQUENESS VIOLATION: multiarr0[%0d] == multiarr1[%0d] == 0x%h", i, j, multiarr0[i]);
$error("UNIQUENESS VIOLATION: multiarr0[%0d] == multiarr1[%0d] == 0x%h", i, j,
multiarr0[i]);
end
end
end
@@ -152,8 +155,8 @@ module t;
cc.randomize();
a.randomize();
repeat(20) cc.check_unique();
repeat(20) a.check_unique();
repeat (20) cc.check_unique();
repeat (20) a.check_unique();
$write("*-* All Finished *-*\n");
$finish;
test_regress/t/t_cover_fsm_multi_inst.v
+19 -4
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@@ -5,8 +5,17 @@
// SPDX-License-Identifier: CC0-1.0
// SPDX-FileCopyrightText: 2026 Wilson Snyder
module fsm(input logic clk, input logic alt);
typedef enum logic [2:0] { IDLE, RUN1A, RUN1B, RUN2, DONE } state_t;
module fsm (
input logic clk,
input logic alt
);
typedef enum logic [2:0] {
IDLE,
RUN1A,
RUN1B,
RUN2,
DONE
} state_t;
state_t state;
initial state = IDLE;
always @(posedge clk) begin
@@ -25,8 +34,14 @@ module t;
logic clk = 0;
always #5 clk = ~clk;
fsm u1(.clk(clk), .alt(1'b0));
fsm u2(.clk(clk), .alt(1'b1));
fsm u1 (
.clk(clk),
.alt(1'b0)
);
fsm u2 (
.clk(clk),
.alt(1'b1)
);
initial begin
#201;
test_regress/t/t_covergroup_bin_counts.v
+10 -3
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@@ -24,7 +24,10 @@ module t;
// cg: basic bin count tracking
covergroup cg;
coverpoint data {bins zero = {0}; bins low = {[1 : 3]};}
coverpoint data {
bins zero = {0};
bins low = {[1 : 3]};
}
endgroup
// cg_mixed: mixed bin types - single values, multi-value lists, ranges
@@ -40,7 +43,10 @@ module t;
// cg_db: labeled coverpoint - verifies the coverage database records the correct hierarchy path
covergroup cg_db;
cp: coverpoint data {bins low = {[0 : 3]}; bins high = {[8 : 15]};}
cp: coverpoint data {
bins low = {[0 : 3]};
bins high = {[8 : 15]};
}
endgroup
// cg_unbounded: open-ended bin range - '$' resolves to the coverpoint domain max (15 for 4-bit)
@@ -77,7 +83,8 @@ module t;
// cg_sel: coverpoint over a struct-member part-select expression (AstSel)
covergroup cg_sel;
cp: coverpoint f1.value[3:0] { // low nibble only; upper bits ignored
bins lo = {[0 : 7]}; bins hi = {[8 : 15]};
bins lo = {[0 : 7]};
bins hi = {[8 : 15]};
}
endgroup
test_regress/t/t_covergroup_bins_fill.v
+6 -2
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@@ -23,8 +23,12 @@ module t;
bins hi = {[8'h80 : '1]};
bins lo = {['0 : 8'h7f]};
}
cp_sb: coverpoint sb {bins m1 = {'1};}
cp_mode: coverpoint mode {bins m = {3};}
cp_sb: coverpoint sb {
bins m1 = {'1};
}
cp_mode: coverpoint mode {
bins m = {3};
}
cx: cross cp_mode, cp_insn;
endgroup
test_regress/t/t_covergroup_binsof.v
+12 -3
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@@ -22,7 +22,11 @@ module t (
bins arrayed[] = {3, 4};
bins rest = default;
}
cp_b: coverpoint b {bins low = {0}; bins high = {1}; bins either = {[0 : 1]};}
cp_b: coverpoint b {
bins low = {0};
bins high = {1};
bins either = {[0 : 1]};
}
// Overlapping coverpoint bins must not count a selected cross bin twice.
all_products: cross cp_a, cp_b{
bins combined = binsof (cp_a);
@@ -52,13 +56,18 @@ module t (
endgroup
covergroup cg_transition with function sample (bit [6:0] a, bit b);
cp_a: coverpoint a {bins seq = (0 => 1); bins two = {2};}
cp_a: coverpoint a {
bins seq = (0 => 1);
bins two = {2};
}
cp_b: coverpoint b;
transitions: cross cp_a, cp_b{bins selected = binsof (cp_a.seq);}
endgroup
covergroup cg_empty with function sample (bit a, bit b);
cp_a: coverpoint a {ignore_bins ignored = {0, 1};}
cp_a: coverpoint a {
ignore_bins ignored = {0, 1};
}
cp_b: coverpoint b;
empty_product: cross cp_a, cp_b{bins selected = binsof (cp_b);}
endgroup
test_regress/t/t_covergroup_illegal_bins.v
+10 -2
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@@ -18,7 +18,12 @@ module t;
logic [3:0] data4;
covergroup cg;
coverpoint data {bins low = {0}; bins mid = {1}; bins high = {2}; illegal_bins forbidden = {3};}
coverpoint data {
bins low = {0};
bins mid = {1};
bins high = {2};
illegal_bins forbidden = {3};
}
endgroup
// cg2: illegal_bins on multi-step transitions and array notation
@@ -38,7 +43,10 @@ module t;
// cg3: all bins are ignore_bins or illegal_bins - nothing contributes to coverage
covergroup cg3;
cp: coverpoint data {ignore_bins ign = {0, 1}; illegal_bins ill = {2, 3};}
cp: coverpoint data {
ignore_bins ign = {0, 1};
illegal_bins ill = {2, 3};
}
endgroup
initial begin
test_regress/t/t_covergroup_member_event_unsup.out
+2 -2
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@@ -3,8 +3,8 @@
| ^~~~~~~
... For warning description see https://verilator.org/warn/COVERIGN?v=latest
... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message.
%Warning-COVERIGN: t/t_covergroup_member_event_unsup.v:37:5: Unsupported: 'covergroup' clocking event on complex member expression; use --timing for full support.
%Warning-COVERIGN: t/t_covergroup_member_event_unsup.v:40:5: Unsupported: 'covergroup' clocking event on complex member expression; use --timing for full support.
: ... note: In instance 't'
37 | covergroup cov_cplx @(posedge a or posedge mid.lvl.ev);
40 | covergroup cov_cplx @(posedge a or posedge mid.lvl.ev);
| ^~~~~~~~~~
%Error: Exiting due to
test_regress/t/t_covergroup_member_event_unsup.v
+8 -2
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@@ -13,7 +13,10 @@ module t;
bit [3:0] value;
covergroup cov_extclk @(posedge clk);
coverpoint value {bins lo = {[0 : 7]}; bins hi = {[8 : 15]};}
coverpoint value {
bins lo = {[0 : 7]};
bins hi = {[8 : 15]};
}
endgroup
function new();
@@ -36,7 +39,10 @@ module t;
covergroup cov_cplx @(posedge a or posedge mid.lvl.ev);
option.weight = 2; // Dropped along with the covergroup
coverpoint value {bins lo = {[0 : 7]}; bins hi = {[8 : 15]};}
coverpoint value {
bins lo = {[0 : 7]};
bins hi = {[8 : 15]};
}
endgroup
function new();
test_regress/t/t_covergroup_param_class.v
+28 -12
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@@ -4,39 +4,51 @@
// SPDX-FileCopyrightText: 2026 David Harris
// SPDX-License-Identifier: CC0-1.0
interface trace_if #(parameter int ILEN = 32, parameter int XLEN = 32) ();
interface trace_if #(
parameter int ILEN = 32,
parameter int XLEN = 32
) ();
logic clk;
logic [ILEN-1:0] insn;
endinterface
package cov_pkg;
class TraceData #(parameter int ILEN = 32, parameter int XLEN = 32);
class TraceData #(
parameter int ILEN = 32,
parameter int XLEN = 32
);
logic [ILEN-1:0] insn;
endclass
class Instr #(parameter int ILEN = 32, parameter int XLEN = 32);
class Instr #(
parameter int ILEN = 32,
parameter int XLEN = 32
);
TraceData #(ILEN, XLEN) current;
function new();
current = new();
endfunction
endclass
class CovBase #(parameter int ILEN = 32, parameter int XLEN = 32);
typedef Instr #(ILEN, XLEN) ins_t;
class CovBase #(
parameter int ILEN = 32,
parameter int XLEN = 32
);
typedef Instr#(ILEN, XLEN) ins_t;
// A virtual interface member is what puts an interface type reference
// inside this class, alongside the covergroup below.
virtual trace_if #(ILEN, XLEN) vif;
covergroup cg with function sample(ins_t ins);
covergroup cg with function sample (ins_t ins);
cp_insn: coverpoint ins.current.insn {
bins ecall = {32'h00000073};
}
endgroup
// A second covergroup, so one nested class is preceded by another
covergroup cg2 with function sample(ins_t ins);
covergroup cg2 with function sample (ins_t ins);
cp_insn: coverpoint ins.current.insn {
bins ebreak = {32'h00100073};
}
@@ -61,14 +73,18 @@ endpackage
import cov_pkg::*;
class Cov #(parameter int ILEN = 32, parameter int XLEN = 32)
extends CovBase #(ILEN, XLEN);
class Cov #(
parameter int ILEN = 32,
parameter int XLEN = 32
) extends CovBase #(ILEN, XLEN);
function new(virtual trace_if #(ILEN, XLEN) vif);
super.new(vif);
endfunction
endclass
module worker(trace_if vif);
module worker (
trace_if vif
);
// Specialized from parameters read off the interface instance
Cov #(vif.ILEN, vif.XLEN) cov;
initial begin
@@ -80,6 +96,6 @@ module worker(trace_if vif);
endmodule
module t;
trace_if #(32, 64) vif();
worker worker(vif);
trace_if #(32, 64) vif ();
worker worker (vif);
endmodule
test_regress/t/t_covergroup_ref_bind_lvalue.v
+8 -2
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@@ -19,13 +19,19 @@ module t (
covergroup cg_a(ref logic [1:0] sig);
cp_a: coverpoint sig {
bins zero = {2'b00}; bins one = {2'b01}; bins two = {2'b10}; bins three = {2'b11};
bins zero = {2'b00};
bins one = {2'b01};
bins two = {2'b10};
bins three = {2'b11};
}
endgroup
covergroup cg_b(ref logic [1:0] sig);
cp_b: coverpoint sig {
bins zero = {2'b00}; bins one = {2'b01}; bins two = {2'b10}; bins three = {2'b11};
bins zero = {2'b00};
bins one = {2'b01};
bins two = {2'b10};
bins three = {2'b11};
}
endgroup
test_regress/t/t_dfg_break_cycles.v
+1 -1
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@@ -421,7 +421,7 @@ module t (
`signal(PACKED_0_LSB, 1);
assign PACKED_0_LSB = packed_0_lsb;
logic [3:0] packed_1; // Bit 3 deliberately undriven
logic [3:0] packed_1; // Bit 3 deliberately undriven
assign packed_1[1] = rand_a[0];
always_comb begin
packed_1[2] = rand_a[1];
test_regress/t/t_display_concat.v
+1 -1
View File
@@ -9,7 +9,7 @@ module t (
);
int cyc = 0;
always @(posedge clk)++cyc;
always @(posedge clk) ++cyc;
reg [15 : 0] t2;
test_regress/t/t_dyn_assoc_anon.v
+3 -2
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@@ -14,7 +14,7 @@ module t (
);
reg [7:0] da0[*];
reg [7:0] da1[2][*];
reg [7:0] da1[2] [*];
integer cyc = 0;
@@ -24,7 +24,8 @@ module t (
da0[1] = 8'h11;
da1[0][2] = 8'h22;
da1[1][3] = 8'h33;
end else if (cyc == 1) begin
end
else if (cyc == 1) begin
`checkh(da0.size(), 1);
`checkh(da0[1], 8'h11);
`checkh(da1[0].size(), 1);
test_regress/t/t_event_array_fire.v
+4 -4
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@@ -49,11 +49,11 @@ module t;
run_traffic_per_port(i);
end
#10->e_all_xfers_monitored_tx[0];
#10->e_all_xfers_monitored_rx[0];
#10 ->e_all_xfers_monitored_tx[0];
#10 ->e_all_xfers_monitored_rx[0];
#10->e_all_xfers_monitored_tx[1];
#10->e_all_xfers_monitored_rx[1];
#10 ->e_all_xfers_monitored_tx[1];
#10 ->e_all_xfers_monitored_rx[1];
@(e_all_xfers_completed[0]);
@(e_all_xfers_completed[1]);
test_regress/t/t_event_dynamic_wait.v
+1 -1
View File
@@ -27,7 +27,7 @@ module t;
fork
begin
#10->h.ev;
#10 ->h.ev;
end
begin
h.wait_once;
test_regress/t/t_exprstmt_on_lhs_of_nba.v
+1 -1
View File
@@ -46,7 +46,7 @@ module t (
always @(posedge clk) begin
if (write_valid_i)
FIFOContent[write_front_i?(read_valid_i?read_pointer : prevPointer(
FIFOContent[write_front_i ? (read_valid_i ? read_pointer : prevPointer(
read_pointer
)) : write_pointer] <= data_i;
end
test_regress/t/t_for_loop.v
+1 -1
View File
@@ -81,7 +81,7 @@ module t (
// 1800-2017 optionals init/expr/incr
loops = 0;
i = 0;
for (; i < 10; ++i)++loops;
for (; i < 10; ++i) ++loops;
if (loops !== 10) $stop;
//
loops = 0;
test_regress/t/t_gen_assign.v
+1 -1
View File
@@ -57,7 +57,7 @@ module assigns (
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : ap
assign Output[(i>0)?i-1 : 8] = Input[(i>0)?i-1 : 8];
assign Output[(i > 0) ? i - 1 : 8] = Input[(i > 0) ? i - 1 : 8];
end
endgenerate
endmodule
test_regress/t/t_iface_typedef_param_bits.v
+10 -8
View File
@@ -8,12 +8,12 @@
// SPDX-License-Identifier: CC0-1.0
package a_pkg;
typedef struct packed {
int unsigned p_a;
} cfg_t;
typedef struct packed {int unsigned p_a;} cfg_t;
endpackage
interface sub_if #(parameter a_pkg::cfg_t cfg = 0);
interface sub_if #(
parameter a_pkg::cfg_t cfg = 0
);
typedef logic [cfg.p_a-1:0] data_t;
typedef struct packed {
logic [3:0] addr;
@@ -21,15 +21,17 @@ interface sub_if #(parameter a_pkg::cfg_t cfg = 0);
} data2_t;
endinterface
module sub (sub_if io);
module sub (
sub_if io
);
endmodule
module t();
module t ();
parameter a_pkg::cfg_t cfg = '{p_a: 16};
sub_if #(cfg) sub_io();
sub_if #(cfg) sub_io ();
sub u_sub(.io(sub_io));
sub u_sub (.io(sub_io));
typedef sub_io.data2_t data2_t;
typedef sub_io.data_t data_t;
test_regress/t/t_inline_task_name.v
+25 -5
View File
@@ -21,9 +21,21 @@ module t;
int b_out;
int c_out;
suba ua(.clk(clk), .base(32'd10), .out(a_out));
suba ub(.clk(clk), .base(32'd20), .out(b_out));
subb uc(.clk(clk), .base(32'd30), .out(c_out));
suba ua (
.clk(clk),
.base(32'd10),
.out(a_out)
);
suba ub (
.clk(clk),
.base(32'd20),
.out(b_out)
);
subb uc (
.clk(clk),
.base(32'd30),
.out(c_out)
);
function automatic int twiddle(int x);
return x + 1;
@@ -43,7 +55,11 @@ module t;
endmodule
module suba(input clk, input int base, output int out);
module suba (
input clk,
input int base,
output int out
);
/*verilator inline_module*/
int val;
@@ -62,7 +78,11 @@ module suba(input clk, input int base, output int out);
end
endmodule
module subb(input clk, input int base, output int out);
module subb (
input clk,
input int base,
output int out
);
/*verilator no_inline_module*/
int val;
test_regress/t/t_inst_array_bad.out
+12 -12
View File
@@ -1,14 +1,14 @@
%Error: t/t_inst_array_bad.v:14:27: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. (IEEE 1800-2023 23.3.3)
: ... note: In instance 't'
14 | sub sub [7:0] (allbits, onebitbad, bitout);
| ^~~~~~~~~
%Error: t/t_inst_array_bad.v:16:7: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. (IEEE 1800-2023 23.3.3)
: ... note: In instance 't'
16 | onebitbad,
| ^~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_inst_array_bad.v:24:33: Input port connection 'onebit' as part of a module instance array requires 1 or 6 bits, but connection's VARREF 'sixbitbad' generates 7 bits. (IEEE 1800-2023 23.3.3)
: ... note: In instance 't'
24 | sub sub3 [1:0][2:0] (allbits, sixbitbad, sixbitout);
| ^~~~~~~~~
%Error: t/t_inst_array_bad.v:29:33: Input port connection 'onebit' as part of a module instance array requires the connection's leading unpacked dimensions to match the instance array dimensions (IEEE 1800-2023 23.3.3.5)
: ... note: In instance 't'
29 | sub sub5 [1:0][2:0] (allbits, onebits2, sixbitout2);
| ^~~~~~~~
%Error: t/t_inst_array_bad.v:34:7: Input port connection 'onebit' as part of a module instance array requires 1 or 6 bits, but connection's VARREF 'sixbitbad' generates 7 bits. (IEEE 1800-2023 23.3.3)
: ... note: In instance 't'
34 | sixbitbad,
| ^~~~~~~~~
%Error: t/t_inst_array_bad.v:43:7: Input port connection 'onebit' as part of a module instance array requires the connection's leading unpacked dimensions to match the instance array dimensions (IEEE 1800-2023 23.3.3.5)
: ... note: In instance 't'
43 | onebits2,
| ^~~~~~~~
%Error: Exiting due to
test_regress/t/t_inst_array_bad.v
+31 -11
View File
@@ -7,29 +7,49 @@
module t;
wire [7:0] bitout;
reg [7:0] allbits;
reg [7:0] onebit;
reg [8:0] onebitbad; // Wrongly sized
reg [7:0] allbits;
reg [7:0] onebit;
reg [8:0] onebitbad; // Wrongly sized
sub sub [7:0] (allbits, onebitbad, bitout);
sub sub[7:0] (
allbits,
onebitbad,
bitout
);
// This is ok.
wire [9:8] b;
wire [1:0] c;
sub sub2 [9:8] (allbits,b,c);
sub sub2[9:8] (
allbits,
b,
c
);
// Multi-dimensional, 6 elements
reg [6:0] sixbitbad; // Wrongly sized
reg [6:0] sixbitbad; // Wrongly sized
wire [5:0] sixbitout;
sub sub3 [1:0][2:0] (allbits, sixbitbad, sixbitout);
sub sub3[1:0][2:0] (
allbits,
sixbitbad,
sixbitout
);
// Unpacked connection with fewer unpacked dimensions than the instance array
reg onebits2[1:0];
reg onebits2[1:0];
wire [5:0] sixbitout2;
sub sub5 [1:0][2:0] (allbits, onebits2, sixbitout2);
sub sub5[1:0][2:0] (
allbits,
onebits2,
sixbitout2
);
endmodule
module sub (input [7:0] allbits, input onebit, output bitout);
assign bitout = onebit ^ (^ allbits);
module sub (
input [7:0] allbits,
input onebit,
output bitout
);
assign bitout = onebit ^ (^allbits);
endmodule
test_regress/t/t_interface_modport_expr.v
+3 -1
View File
@@ -9,7 +9,9 @@
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
// verilog_format: on
interface my_if #(parameter WIDTH = 1);
interface my_if #(
parameter WIDTH = 1
);
logic [WIDTH-1:0] sig_a, sig_b, sig_c, sig_d;
logic [WIDTH-1:0] sig_e, sig_f;
// Multiple expressions same direction
test_regress/t/t_interface_paren_missing_bad.out
+16 -16
View File
@@ -1,20 +1,20 @@
%Error: t/t_interface_paren_missing_bad.v:37:8: Interface port declaration 'intf_t_not_port' doesn't have corresponding port
%Error: t/t_interface_paren_missing_bad.v:40:8: Interface port declaration 'intf_t_not_port' doesn't have corresponding port
: ... Perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
37 | intf intf_t_not_port;
40 | intf intf_t_not_port;
| ^~~~~~~~~~~~~~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: t/t_interface_paren_missing_bad.v:38:10: Interface port declaration 'intf_t_not_port_mod' doesn't have corresponding port
%Error: t/t_interface_paren_missing_bad.v:41:10: Interface port declaration 'intf_t_not_port_mod' doesn't have corresponding port
: ... Perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
38 | intf.A intf_t_not_port_mod;
41 | intf.A intf_t_not_port_mod;
| ^~~~~~~~~~~~~~~~~~~
%Error: t/t_interface_paren_missing_bad.v:39:20: Interface port declaration 'intf_no_instance_t_not_port' doesn't have corresponding port
%Error: t/t_interface_paren_missing_bad.v:42:20: Interface port declaration 'intf_no_instance_t_not_port' doesn't have corresponding port
: ... Perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
39 | intf_no_instance intf_no_instance_t_not_port;
42 | intf_no_instance intf_no_instance_t_not_port;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error: t/t_interface_paren_missing_bad.v:39:3: Interface 'intf_no_instance' not connected as parent's interface not connected
%Error: t/t_interface_paren_missing_bad.v:42:3: Interface 'intf_no_instance' not connected as parent's interface not connected
: ... Perhaps caused by another error on the parent interface that needs resolving
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
39 | intf_no_instance intf_no_instance_t_not_port;
42 | intf_no_instance intf_no_instance_t_not_port;
| ^~~~~~~~~~~~~~~~
%Error: t/t_interface_paren_missing_bad.v:23:8: Interface port declaration 'intf_b_not_port' doesn't have corresponding port
: ... Perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
@@ -33,21 +33,21 @@
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
25 | intf_no_instance intf_no_instance_b_not_port;
| ^~~~~~~~~~~~~~~~
%Error: t/t_interface_paren_missing_bad.v:30:8: Interface port declaration 'intf_d_not_port' doesn't have corresponding port
%Error: t/t_interface_paren_missing_bad.v:33:8: Interface port declaration 'intf_d_not_port' doesn't have corresponding port
: ... Perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
30 | intf intf_d_not_port;
33 | intf intf_d_not_port;
| ^~~~~~~~~~~~~~~
%Error: t/t_interface_paren_missing_bad.v:32:10: Interface port declaration 'intf_d_not_port_mod' doesn't have corresponding port
%Error: t/t_interface_paren_missing_bad.v:35:10: Interface port declaration 'intf_d_not_port_mod' doesn't have corresponding port
: ... Perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
32 | intf.A intf_d_not_port_mod;
35 | intf.A intf_d_not_port_mod;
| ^~~~~~~~~~~~~~~~~~~
%Error: t/t_interface_paren_missing_bad.v:33:20: Interface port declaration 'intf_no_instance_d_not_port' doesn't have corresponding port
%Error: t/t_interface_paren_missing_bad.v:36:20: Interface port declaration 'intf_no_instance_d_not_port' doesn't have corresponding port
: ... Perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
33 | intf_no_instance intf_no_instance_d_not_port;
36 | intf_no_instance intf_no_instance_d_not_port;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
%Error: t/t_interface_paren_missing_bad.v:33:3: Interface 'intf_no_instance' not connected as parent's interface not connected
%Error: t/t_interface_paren_missing_bad.v:36:3: Interface 'intf_no_instance' not connected as parent's interface not connected
: ... Perhaps caused by another error on the parent interface that needs resolving
: ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)?
33 | intf_no_instance intf_no_instance_d_not_port;
36 | intf_no_instance intf_no_instance_d_not_port;
| ^~~~~~~~~~~~~~~~
%Error: Exiting due to
test_regress/t/t_interface_paren_missing_bad.v
+18 -15
View File
@@ -10,22 +10,25 @@ interface intf_no_instance;
endinterface
interface intf #(
parameter int par
parameter int par
);
logic in;
modport A(input in);
endinterface
module b (
intf intf_b_port,
intf.A intf_b_port_mod
intf intf_b_port,
intf.A intf_b_port_mod
);
intf intf_b_not_port;
intf.A intf_b_not_port_mod;
intf_no_instance intf_no_instance_b_not_port;
endmodule
module d (intf_d_port, intf_d_port_mod);
module d (
intf_d_port,
intf_d_port_mod
);
intf intf_d_port;
intf intf_d_not_port;
intf.A intf_d_port_mod;
@@ -37,24 +40,24 @@ module t;
intf intf_t_not_port;
intf.A intf_t_not_port_mod;
intf_no_instance intf_no_instance_t_not_port;
intf #(.par(8)) intf_exists();
intf #(.par(8)) intf_exists ();
b b1 (
.intf_b_port(intf_exists),
.intf_b_port_mod(intf_exists.A),
.intf_b_not_port(intf_exists.A)
.intf_b_port(intf_exists),
.intf_b_port_mod(intf_exists.A),
.intf_b_not_port(intf_exists.A)
);
b b2 (
.intf_b_port(intf_exists),
.intf_b_port_mod(intf_exists.A)
.intf_b_port(intf_exists),
.intf_b_port_mod(intf_exists.A)
);
d d1 (
.intf_d_port(intf_exists),
.intf_d_port_mod(intf_exists.A),
.intf_d_not_port(intf_exists.A)
.intf_d_port(intf_exists),
.intf_d_port_mod(intf_exists.A),
.intf_d_not_port(intf_exists.A)
);
d d2 (
.intf_d_port(intf_exists),
.intf_d_port_mod(intf_exists.A)
.intf_d_port(intf_exists),
.intf_d_port_mod(intf_exists.A)
);
initial $finish;
endmodule
test_regress/t/t_lint_multidriven_ftask_def.v
+5 -1
View File
@@ -4,7 +4,11 @@
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
module t(input wire clk, input wire reset, input wire request);
module t (
input wire clk,
input wire reset,
input wire request
);
// Writes in never-called task/function definitions are not executed
// processes, so they must not count as the "other write" of MULTIDRIVEN,
// no matter how many of them there are.
test_regress/t/t_math_shift.v
+116 -107
View File
@@ -4,17 +4,23 @@
// SPDX-FileCopyrightText: 2004 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
ign, ign2, ign3, c_wright_32, c_wleft_32, ign4, ign4s,
// Inputs
clk
);
module t ( /*AUTOARG*/
// Outputs
ign,
ign2,
ign3,
c_wright_32,
c_wleft_32,
ign4,
ign4s,
// Inputs
clk
);
input clk;
output [31:0] ign;
output [3:0] ign2;
output [11:0] ign3;
output [3:0] ign2;
output [11:0] ign3;
parameter [95:0] P6 = 6;
localparam P64 = (1 << P6);
@@ -24,95 +30,97 @@ module t (/*AUTOARG*/
localparam [3:0] PBIG29 = 4'b1 << 33'h100000000;
// verilator lint_on WIDTH
reg [31:0] iright;
reg signed [31:0] irights;
reg [31:0] ileft;
reg [P64-1:0] qright;
reg [31:0] iright;
reg signed [31:0] irights;
reg [31:0] ileft;
reg [P64-1:0] qright;
reg signed [P64-1:0] qrights;
reg [P64-1:0] qleft;
reg [95:0] wright;
reg signed [95:0] wrights;
reg [95:0] wleft;
reg [P64-1:0] qleft;
reg [95:0] wright;
reg signed [95:0] wrights;
reg [95:0] wleft;
reg [31:0] q_iright;
reg signed [31:0] q_irights;
reg [31:0] q_ileft;
reg [P64-1:0] q_qright;
reg [31:0] q_iright;
reg signed [31:0] q_irights;
reg [31:0] q_ileft;
reg [P64-1:0] q_qright;
reg signed [P64-1:0] q_qrights;
reg [P64-1:0] q_qleft;
reg [95:0] q_wright;
reg signed [95:0] q_wrights;
reg [95:0] q_wleft;
reg [P64-1:0] q_qleft;
reg [95:0] q_wright;
reg signed [95:0] q_wrights;
reg [95:0] q_wleft;
reg [31:0] w_iright;
reg signed [31:0] w_irights;
reg [31:0] w_ileft;
reg [P64-1:0] w_qright;
reg [31:0] w_iright;
reg signed [31:0] w_irights;
reg [31:0] w_ileft;
reg [P64-1:0] w_qright;
reg signed [P64-1:0] w_qrights;
reg [P64-1:0] w_qleft;
reg [95:0] w_wright;
reg signed [95:0] w_wrights;
reg [95:0] w_wleft;
reg [P64-1:0] w_qleft;
reg [95:0] w_wright;
reg signed [95:0] w_wrights;
reg [95:0] w_wleft;
reg [31:0] iamt;
reg [63:0] qamt;
reg [95:0] wamt;
reg [31:0] iamt;
reg [63:0] qamt;
reg [95:0] wamt;
output reg [95:0] c_wright_32;
output reg [95:0] c_wleft_32;
output reg [95:0] c_wright_32;
output reg [95:0] c_wleft_32;
reg [63:0] crc = 64'h5aef0c8d_d70a4497;
wire [95:0] rand_96 = {crc[63:32] | crc[31:0], crc};
assign ign = {31'h0, clk} >>> 4'bx; // bug760
assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174
assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}},
iamt[1:0] >> {11{iamt[5:2]}},
$signed(iamt[1:0]) >>> {22{iamt[5:2]}},
$signed(iamt[1:0]) >>> {11{iamt[5:2]}},
iamt[1:0] << {22{iamt[5:2]}},
iamt[1:0] << {11{iamt[5:2]}}};
assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174
assign ign3 = {
iamt[1:0] >> {22{iamt[5:2]}},
iamt[1:0] >> {11{iamt[5:2]}},
$signed(iamt[1:0]) >>> {22{iamt[5:2]}},
$signed(iamt[1:0]) >>> {11{iamt[5:2]}},
iamt[1:0] << {22{iamt[5:2]}},
iamt[1:0] << {11{iamt[5:2]}}
};
wire [95:0] wamtt = {iamt,iamt,iamt};
wire [95:0] wamtt = {iamt, iamt, iamt};
output wire [95:0] ign4;
assign ign4 = wamtt >> {11{iamt[5:2]}};
output wire signed [95:0] ign4s;
assign ign4s = $signed(wamtt) >>> {11{iamt[5:2]}};
always @* begin
iright = 32'h819b018a >> iamt;
iright = 32'h819b018a >> iamt;
irights = 32'sh819b018a >>> signed'(iamt);
ileft = 32'h819b018a << iamt;
qright = 64'hf784bf8f_12734089 >> iamt;
ileft = 32'h819b018a << iamt;
qright = 64'hf784bf8f_12734089 >> iamt;
qrights = 64'shf784bf8f_12734089 >>> signed'(iamt);
qleft = 64'hf784bf8f_12734089 << iamt;
wright = 96'hf784bf8f_12734089_190abe48 >> iamt;
qleft = 64'hf784bf8f_12734089 << iamt;
wright = 96'hf784bf8f_12734089_190abe48 >> iamt;
wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(iamt);
wleft = 96'hf784bf8f_12734089_190abe48 << iamt;
wleft = 96'hf784bf8f_12734089_190abe48 << iamt;
q_iright = 32'h819b018a >> qamt;
q_iright = 32'h819b018a >> qamt;
q_irights = 32'sh819b018a >>> signed'(qamt);
q_ileft = 32'h819b018a << qamt;
q_qright = 64'hf784bf8f_12734089 >> qamt;
q_ileft = 32'h819b018a << qamt;
q_qright = 64'hf784bf8f_12734089 >> qamt;
q_qrights = 64'shf784bf8f_12734089 >>> signed'(qamt);
q_qleft = 64'hf784bf8f_12734089 << qamt;
q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt;
q_qleft = 64'hf784bf8f_12734089 << qamt;
q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt;
q_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(qamt);
q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt;
q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt;
w_iright = 32'h819b018a >> wamt;
w_iright = 32'h819b018a >> wamt;
w_irights = 32'sh819b018a >>> signed'(wamt);
w_ileft = 32'h819b018a << wamt;
w_qright = 64'hf784bf8f_12734089 >> wamt;
w_ileft = 32'h819b018a << wamt;
w_qright = 64'hf784bf8f_12734089 >> wamt;
w_qrights = 64'shf784bf8f_12734089 >>> signed'(wamt);
w_qleft = 64'hf784bf8f_12734089 << wamt;
w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt;
w_qleft = 64'hf784bf8f_12734089 << wamt;
w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt;
w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt);
w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt;
w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt;
c_wright_32 = rand_96 >> 32;
c_wleft_32 = rand_96 << 32;
c_wleft_32 = rand_96 << 32;
end
// Constant shift amount with its top bit set is still unsigned.
@@ -126,109 +134,110 @@ module t (/*AUTOARG*/
if ((qq.pop_front() >> 8'd200) != 64'h0) $stop;
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
integer cyc;
initial cyc = 1;
always @(posedge clk) begin
if (cyc != 0) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright);
`endif
if (cyc==1) begin
if (cyc == 1) begin
iamt <= 0;
qamt <= 0;
wamt <= 0;
if (P64 != 64) $stop;
if (5'b10110>>2 != 5'b00101) $stop;
if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness
if (5'b10110<<2 != 5'b11000) $stop;
if (5'b10110<<<2 != 5'b11000) $stop;
if (5'sb10110>>2 != 5'sb00101) $stop;
if (5'sb10110>>>2 != 5'sb11101) $stop;
if (5'sb10110<<2 != 5'sb11000) $stop;
if (5'sb10110<<<2 != 5'sb11000) $stop;
if (5'b10110 >> 2 != 5'b00101) $stop;
if (5'b10110 >>> 2 != 5'b00101) $stop; // Note it cares about sign-ness
if (5'b10110 << 2 != 5'b11000) $stop;
if (5'b10110 <<< 2 != 5'b11000) $stop;
if (5'sb10110 >> 2 != 5'sb00101) $stop;
if (5'sb10110 >>> 2 != 5'sb11101) $stop;
if (5'sb10110 << 2 != 5'sb11000) $stop;
if (5'sb10110 <<< 2 != 5'sb11000) $stop;
// Allow >64 bit shifts if the shift amount is a constant
if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop;
end
if (cyc==2) begin
if (cyc == 2) begin
iamt <= 28;
qamt <= 28;
wamt <= 28;
if (ileft != 32'h819b018a) $stop;
if (iright != 32'h819b018a) $stop;
if (ileft != 32'h819b018a) $stop;
if (iright != 32'h819b018a) $stop;
if (irights != 32'h819b018a) $stop;
if (qleft != 64'hf784bf8f_12734089) $stop;
if (qright != 64'hf784bf8f_12734089) $stop;
if (qleft != 64'hf784bf8f_12734089) $stop;
if (qright != 64'hf784bf8f_12734089) $stop;
if (qrights != 64'hf784bf8f_12734089) $stop;
if (wleft != 96'hf784bf8f12734089190abe48) $stop;
if (wright != 96'hf784bf8f12734089190abe48) $stop;
if (wleft != 96'hf784bf8f12734089190abe48) $stop;
if (wright != 96'hf784bf8f12734089190abe48) $stop;
if (wrights != 96'hf784bf8f12734089190abe48) $stop;
end
if (cyc==3) begin
if (cyc == 3) begin
iamt <= 31;
qamt <= 31;
wamt <= 31;
if (ileft != 32'ha0000000) $stop;
if (ileft != 32'ha0000000) $stop;
if (iright != 32'h8) $stop;
if (irights != 32'hfffffff8) $stop;
if (qleft != 64'hf127340890000000) $stop;
if (qleft != 64'hf127340890000000) $stop;
if (qright != 64'h0000000f784bf8f1) $stop;
if (qrights != 64'hffffffff784bf8f1) $stop;
if (wleft != 96'hf12734089190abe480000000) $stop;
if (wleft != 96'hf12734089190abe480000000) $stop;
if (wright != 96'h0000000f784bf8f127340891) $stop;
if (wrights != 96'hffffffff784bf8f127340891) $stop;
end
if (cyc==4) begin
if (cyc == 4) begin
iamt <= 32;
qamt <= 32;
wamt <= 32;
if (ileft != 32'h0) $stop;
if (ileft != 32'h0) $stop;
if (iright != 32'h1) $stop;
if (qleft != 64'h8939a04480000000) $stop;
if (qleft != 64'h8939a04480000000) $stop;
if (qright != 64'h00000001ef097f1e) $stop;
end
if (cyc==5) begin
if (cyc == 5) begin
iamt <= 33;
qamt <= 33;
wamt <= 33;
if (ileft != 32'h0) $stop;
if (ileft != 32'h0) $stop;
if (iright != 32'h0) $stop;
if (qleft != 64'h1273408900000000) $stop;
if (qleft != 64'h1273408900000000) $stop;
if (qright != 64'h00000000f784bf8f) $stop;
end
if (cyc==6) begin
if (cyc == 6) begin
iamt <= 64;
qamt <= 64;
wamt <= 64;
if (ileft != 32'h0) $stop;
if (ileft != 32'h0) $stop;
if (iright != 32'h0) $stop;
if (qleft != 64'h24e6811200000000) $stop;
if (qleft != 64'h24e6811200000000) $stop;
if (qright != 64'h000000007bc25fc7) $stop;
end
if (cyc==7) begin
if (cyc == 7) begin
iamt <= 128;
qamt <= 128;
wamt <= 128;
if (ileft != 32'h0) $stop;
if (ileft != 32'h0) $stop;
if (iright != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==8) begin
if (cyc == 8) begin
iamt <= 100;
qamt <= {32'h10, 32'h0};
wamt <= {32'h10, 64'h0};
if (ileft != '0) $stop;
if (iright != '0) $stop;
if (ileft != '0) $stop;
if (iright != '0) $stop;
if (irights != '1) $stop;
if (qleft != '0) $stop;
if (qright != '0) $stop;
if (qleft != '0) $stop;
if (qright != '0) $stop;
if (qrights != '1) $stop;
if (wleft != '0) $stop;
if (wright != '0) $stop;
if (wleft != '0) $stop;
if (wright != '0) $stop;
if (wrights != '1) $stop;
end
if (cyc==19) begin
if (cyc == 19) begin
$write("*-* All Finished *-*\n");
$finish;
end
test_regress/t/t_mod_interface_array3.v
+33 -8
View File
@@ -72,7 +72,10 @@ module t;
a_if iface[3:1][1:0] ();
isub i_sub[3:1][1:0] (.s(str), .i(iface));
isub i_sub[3:1][1:0] (
.s(str),
.i(iface)
);
// Hierarchical references to elements, with genvar indices
for (genvar a = 1; a < 4; ++a) begin : g_a
@@ -97,16 +100,28 @@ module t;
logic [3:0] vout[1:0][0:2];
logic [23:0] vcat;
/* verilator lint_off ASCRANGE */
pass i_vec[1:0][0:2] (.i(vin), .o(vout));
pass i_vcat[1:0][0:2] (.i(vin), .o(vcat));
pass i_vec[1:0][0:2] (
.i(vin),
.o(vout)
);
pass i_vcat[1:0][0:2] (
.i(vin),
.o(vcat)
);
struct {logic [23:0] f;} vst;
pass i_vst[1:0][0:2] (.i(vin), .o(vst.f));
pass i_vst[1:0][0:2] (
.i(vin),
.o(vst.f)
);
/* verilator lint_on ASCRANGE */
// Streaming concatenation sliced over the elements
logic [7:0] sin = 8'hca;
logic [3:0] sout[1:0];
pass i_stream[1:0] (.i({<<{sin}}), .o(sout));
pass i_stream[1:0] (
.i({<<{sin}}),
.o(sout)
);
// Instance and connection ranges in opposite directions: connect left to left
string xstr[2:1][1:3];
@@ -115,14 +130,21 @@ module t;
// Ascending instance ranges slicing a vector, leftmost element still gets the MSBs
logic [3:0] aout[0:1][0:2];
/* verilator lint_off ASCRANGE */
pass i_asc[0:1][0:2] (.i(vin), .o(aout));
pass i_asc[0:1][0:2] (
.i(vin),
.o(aout)
);
/* verilator lint_on ASCRANGE */
// Unpacked port, connection with the same unpacked dimensions is connected to every element
logic [3:0] ux[3:0] = '{4'h9, 4'h8, 4'h7, 4'h6};
logic [3:0] uo0[1:0];
logic [3:0] uo3[1:0];
usub i_u[1:0] (.a(ux), .o0(uo0), .o3(uo3));
usub i_u[1:0] (
.a(ux),
.o0(uo0),
.o3(uo3)
);
// Elements of a module instance array with an interface array port, connected to a
// two-dimensional interface array, in opposite directions: connect left to left
@@ -138,7 +160,10 @@ module t;
a_if irs[1:0][0:3] ();
awrite i_rsl (.p(irs[1][1:3]));
string elstr;
isub i_el (.s(elstr), .i(irs[0][2]));
isub i_el (
.s(elstr),
.i(irs[0][2])
);
// A slice of an interface array port passed down
a_if i4[4] ();
test_regress/t/t_notiming_off.out
+1 -1
View File
@@ -6,7 +6,7 @@
... For error description see https://verilator.org/warn/NOTIMING?v=latest
%Warning-STMTDLY: t/t_timing_off.v:34:11: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
34 | initial #2->e1;
34 | initial #2 ->e1;
| ^
... For warning description see https://verilator.org/warn/STMTDLY?v=latest
... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
test_regress/t/t_opt_const_cond_redundant.v
+2 -2
View File
@@ -36,8 +36,8 @@ module t (
$finish;
end
if (direction == UP)++ups;
else if (direction == UP)++ups;
if (direction == UP) ++ups;
else if (direction == UP) ++ups;
else ups += 1000;
case (direction)
test_regress/t/t_opt_lift_expr.v
+1 -1
View File
@@ -34,7 +34,7 @@ module t;
`checkh(C::i, 2);
`checkh(C::j, 3);
// Expr
`checkh(|$urandom_range(2,1), 1'b1);
`checkh(|$urandom_range(2, 1), 1'b1);
// LogAnd
`checkh(impure_0() && 1'b0, 1'b0);
`checkh(impure_0() && 1'b1, 1'b0);
test_regress/t/t_prop_always.v
+9 -9
View File
@@ -36,28 +36,28 @@ module t (
assert property (@(posedge clk) always 1'b1);
// A zero-lower-bound weak always remains temporal even though it starts at entry.
assert property (@(posedge clk) (always [0:$] a_low) or 1'b1);
assert property (@(posedge clk) 1'b1 or (always [0:$] a_low));
assert property (@(posedge clk) (always[0: $] a_low) or 1'b1);
assert property (@(posedge clk) 1'b1 or(always[0: $] a_low));
// Bounded weak always over constant-true input.
assert property (@(posedge clk) always [0:3] a_high) high_bounded_pass_q.push_back(cyc);
assert property (@(posedge clk) always[0: 3] a_high) high_bounded_pass_q.push_back(cyc);
// Degenerate [0:0]: equivalent to immediate sample.
assert property (@(posedge clk) always [0:0] a_high) high_degenerate_pass_q.push_back(cyc);
assert property (@(posedge clk) always[0: 0] a_high) high_degenerate_pass_q.push_back(cyc);
// Constant-false: every attempt fails.
assert property (@(posedge clk) always [0:3] a_low)
assert property (@(posedge clk) always[0: 3] a_low)
else low_bounded_fail_q.push_back(cyc);
assert property (@(posedge clk) always [0:0] a_low)
assert property (@(posedge clk) always[0: 0] a_low)
else low_degenerate_fail_q.push_back(cyc);
// CRC-driven random input: window [cyc..cyc+3] of a_rand.
assert property (@(posedge clk) always [0:3] a_rand) rand_bounded_pass_q.push_back(cyc);
assert property (@(posedge clk) always[0: 3] a_rand) rand_bounded_pass_q.push_back(cyc);
else rand_bounded_fail_q.push_back(cyc);
// disable iff suppresses attempts whose start cyc has rst_rand=1.
assert property (@(posedge clk) disable iff (rst_rand) always [0:3] a_rand)
assert property (@(posedge clk) disable iff (rst_rand) always[0: 3] a_rand)
disable_bounded_pass_q.push_back(cyc);
else disable_bounded_fail_q.push_back(cyc);
@@ -69,7 +69,7 @@ module t (
// disable iff inside named property.
property p_disable_named;
@(posedge clk) disable iff (rst_rand) always [1:2] a_high;
@(posedge clk) disable iff (rst_rand) always[1: 2] a_high;
endproperty
assert property (p_disable_named);
test_regress/t/t_pull_bitsel.v
+1 -1
View File
@@ -104,7 +104,7 @@ module t;
wire [31:0] expected = 32'hDE55_8000;
initial begin
#0; // Reading a continuously assigned net in an initial block is a time 0 race.
#0; // Reading a continuously assigned net in an initial block is a time 0 race.
$display("in_value = %h, out_value = %h, expected = %h", in_value, out_value, expected);
`checkh(out_value, expected);
$write("*-* All Finished *-*\n");
test_regress/t/t_randomize.v
+1 -1
View File
@@ -7,7 +7,7 @@
class Packet;
rand int header; // 0..7
rand int length; // 0..15
rand int sublength; // 0..15
rand int sublength; // 0..15
rand bit if_4;
rand bit iff_5_6;
test_regress/t/t_randomize_array.v
+32 -32
View File
@@ -22,26 +22,28 @@ end
class unconstrained_packed_array_test;
rand bit [3:0] [2:0] [15:0] packed_array;
function new();
packed_array = '{default: '{default: '{default: 'h0}}};
endfunction
rand bit [3:0][2:0][15:0] packed_array;
function new();
packed_array = '{default: '{default: '{default: 'h0}}};
endfunction
function void check_randomization();
`check_rand(this, this.packed_array)
endfunction
function void check_randomization();
`check_rand(this, this.packed_array)
endfunction
endclass
class unconstrained_unpacked_array_test;
rand bit [2:0] [15:0] unpacked_array [3][5];
rand int unpacked_array1 [9:3][4:8];
rand int unpacked_array2 [3:9][8:4];
rand bit [2:0][15:0] unpacked_array[3][5];
rand int unpacked_array1[9:3][4:8];
rand int unpacked_array2[3:9][8:4];
function new();
unpacked_array = '{ '{default: '{default: 'h0}},
'{default: '{default: 'h1}},
'{default: '{default: 'h2}}};
unpacked_array = '{
'{default: '{default: 'h0}},
'{default: '{default: 'h1}},
'{default: '{default: 'h2}}
};
unpacked_array1 = '{default: '{default: 0}};
unpacked_array2 = '{default: '{default: 0}};
endfunction
@@ -77,21 +79,21 @@ class unconstrained_dynamic_array_test;
function new();
// Initialize 1D dynamic array
dynamic_array_1d = new[5];
foreach(dynamic_array_1d[i]) begin
foreach (dynamic_array_1d[i]) begin
dynamic_array_1d[i] = 'h0 + i;
end
// Initialize 2D dynamic array
dynamic_array_2d = new[3];
foreach(dynamic_array_2d[i]) begin
foreach (dynamic_array_2d[i]) begin
dynamic_array_2d[i] = new[3];
foreach(dynamic_array_2d[i][j]) begin
foreach (dynamic_array_2d[i][j]) begin
dynamic_array_2d[i][j] = 'h0 + i + j;
end
end
class_dynamic_array = new[5];
foreach(class_dynamic_array[i]) begin
foreach (class_dynamic_array[i]) begin
class_dynamic_array[i] = new;
end
@@ -120,9 +122,7 @@ endclass
class unconstrained_struct_with_array_test;
typedef struct {
rand bit [7:0] byte_array[4];
} struct_with_array_t;
typedef struct {rand bit [7:0] byte_array[4];} struct_with_array_t;
rand struct_with_array_t struct_with_array;
@@ -144,7 +144,7 @@ class unconstrained_struct_array_test;
rand int field_a;
rand int field_b;
} simple_struct_t;
rand simple_struct_t struct_array_1[3]; // Unpacked array
rand simple_struct_t struct_array_1[3]; // Unpacked array
rand simple_struct_t struct_array_2[][]; // Dynamic array
function new();
@@ -196,7 +196,7 @@ class unconstrained_associative_array_test;
`check_rand(this, associative_array_1d["key1"]);
`check_rand(this, associative_array_1d["key2"]);
foreach(associative_array_3d[key1, key2, key3]) begin
foreach (associative_array_3d[key1, key2, key3]) begin
`check_rand(this, associative_array_3d[key1][key2][key3]);
end
endfunction
@@ -211,7 +211,7 @@ class unconstrained_queue_test;
function new();
queue_array_1d = {};
for (int i = 0; i < 8; i++) begin
queue_array_1d.push_back('h0 + i);
queue_array_1d.push_back('h0 + i);
end
queue_array_2d = {};
queue_array_2d[0] = '{1, 2, 3};
@@ -223,7 +223,7 @@ class unconstrained_queue_test;
foreach (queue_array_1d[i]) begin
`check_rand(this, queue_array_1d[i]);
end
foreach(queue_array_2d[i, j]) begin
foreach (queue_array_2d[i, j]) begin
`check_rand(this, queue_array_2d[i][j]);
end
endfunction
@@ -231,7 +231,7 @@ class unconstrained_queue_test;
endclass
module t_randomize_array;
unconstrained_packed_array_test packed_class;
unconstrained_packed_array_test packed_class;
unconstrained_unpacked_array_test unpacked_class;
unconstrained_dynamic_array_test dynamic_class;
unconstrained_struct_with_array_test struct_with_array_class;
@@ -242,42 +242,42 @@ module t_randomize_array;
initial begin
// Test 1: Packed Array Unconstrained Constrained Test
packed_class = new();
repeat(2) begin
repeat (2) begin
packed_class.check_randomization();
end
// Test 2: Unpacked Array Unconstrained Constrained Test
unpacked_class = new();
repeat(2) begin
repeat (2) begin
unpacked_class.check_randomization();
end
// Test 3: Dynamic Array Unconstrained Constrained Test
dynamic_class = new();
repeat(2) begin
repeat (2) begin
dynamic_class.check_randomization();
end
// Test 4: Struct Containing Array Test
struct_with_array_class = new();
repeat(2) begin
repeat (2) begin
struct_with_array_class.check_randomization();
end
struct_array_class = new();
repeat(2) begin
repeat (2) begin
struct_array_class.check_randomization();
end
// Test 5: Associative Array Unconstrained Test
associative_array_class = new();
repeat(2) begin
repeat (2) begin
associative_array_class.check_randomization();
end
// Test 6: Queue Unconstrained Test
queue_class = new();
repeat(2) begin
repeat (2) begin
queue_class.check_randomization();
end
test_regress/t/t_randomize_complex_arrays.v
+16 -11
View File
@@ -6,28 +6,31 @@
class SubClass;
rand bit [2:0] field;
function new ();
function new();
field = 0;
endfunction
endclass
class MyClass;
SubClass sc_inst2[2];
function new ();
function new();
sc_inst2[1] = new;
endfunction
endclass;
endclass
;
class Deep;
MyClass sc_inst1;
function new ();
function new();
sc_inst1 = new;
endfunction
endclass;
endclass
;
class WeNeedToGoDeeper;
Deep sc_inst;
function new ();
function new();
sc_inst = new;
endfunction
endclass;
endclass
;
module t;
initial begin
@@ -35,8 +38,10 @@ module t;
MyClass cl_inst2[2];
cl_inst[1] = new;
cl_inst2[0] = new;
repeat(10) begin
if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].randomize() with {field inside {1, 2, 3};} == 0) begin
repeat (10) begin
if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].randomize() with {
field inside {1, 2, 3};
} == 0) begin
$stop;
end
if (cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field < 1 || cl_inst[1].sc_inst.sc_inst1.sc_inst2[1].field > 3) begin
@@ -49,7 +54,7 @@ module t;
$stop;
end
end
$write("*-* All Finished *-*\n");
$finish;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
test_regress/t/t_randomize_copy_constr.v
+10 -16
View File
@@ -58,18 +58,12 @@ class Base;
pair.lo != 0;
pair.hi != 0;
foreach (fixed_arr[i]) fixed_arr[i] != 0;
foreach (pair_fixed_arr[i]) {
pair_fixed_arr[i].lo != 0;
}
queue.size() inside {[3:5]};
foreach (pair_fixed_arr[i]) {pair_fixed_arr[i].lo != 0;}
queue.size() inside {[3 : 5]};
unique {queue};
foreach (pair_queue[i]) {
pair_queue[i].lo != 0;
}
foreach (pair_queue[i]) {pair_queue[i].lo != 0;}
foreach (assoc[key]) {assoc[key] inside {[50 : 70]};}
foreach (pair_assoc[key]) {
pair_assoc[key].hi != 0;
}
foreach (pair_assoc[key]) {pair_assoc[key].hi != 0;}
}
endclass
@@ -94,9 +88,9 @@ class ClsRandC extends Empty;
endclass
module t;
Base copied;
Base base_for_copy;
Derv derv;
Base copied;
Base base_for_copy;
Derv derv;
Derv2 derv2;
task test;
@@ -140,20 +134,20 @@ module t;
copied = new base_for_copy;
test();
if(derv.z != 0) $stop;
if (derv.z != 0) $stop;
$cast(derv, copied);
void'(derv.randomize());
if (derv.z != 1) $stop;
cr1 = new;
repeat(8) begin
repeat (8) begin
cr1.randomize();
visited[cr1.x] = 1;
end
empty1 = cr1;
empty2 = new empty1;
$cast(cr2, empty2);
repeat(8) begin
repeat (8) begin
cr2.randomize();
if (visited[cr2.x]) $stop;
visited[cr2.x] = 1;
test_regress/t/t_randomize_derived_this.v
+3 -9
View File
@@ -15,22 +15,16 @@
class sub_cfg_c;
rand bit enabled;
constraint defaults {
soft enabled == 1'b0;
}
constraint defaults {soft enabled == 1'b0;}
endclass
class base_c;
rand sub_cfg_c cfg;
rand int unsigned watchdog;
constraint override_cons {
cfg.enabled == 1'b1;
}
constraint override_cons {cfg.enabled == 1'b1;}
constraint watchdog_range {
watchdog inside {[32'd50:32'd200]};
}
constraint watchdog_range {watchdog inside {[32'd50 : 32'd200]};}
function new();
cfg = new();
test_regress/t/t_randomize_dist_conditional.v
+12 -10
View File
@@ -29,16 +29,16 @@ endclass
module t;
DistScalar obj;
int mode1_zeros = 0; // Count of zeros when mode=1 (favor 255)
int mode1_maxes = 0; // Count of 255s when mode=1 (favor 255)
int mode0_zeros = 0; // Count of zeros when mode=0 (favor 0)
int mode0_maxes = 0; // Count of 255s when mode=0 (favor 0)
int mode1_trials = 0; // Total trials with mode=1
int mode0_trials = 0; // Total trials with mode=0
int mode1_zeros = 0; // Count of zeros when mode=1 (favor 255)
int mode1_maxes = 0; // Count of 255s when mode=1 (favor 255)
int mode0_zeros = 0; // Count of zeros when mode=0 (favor 0)
int mode0_maxes = 0; // Count of 255s when mode=0 (favor 0)
int mode1_trials = 0; // Total trials with mode=1
int mode0_trials = 0; // Total trials with mode=0
// Verify distribution ratio matches expected range
function void check_distribution(int trials, int match_count, string match_name,
int expected_pct, string mode_name);
function void check_distribution(int trials, int match_count, string match_name, int expected_pct,
string mode_name);
int actual_pct;
int lower_bound;
int upper_bound;
@@ -55,7 +55,8 @@ module t;
if (actual_pct >= lower_bound && actual_pct <= upper_bound) begin
$display("Distribution OK");
end else begin
end
else begin
$display("WARNING: Distribution appears off (expected %0d+/-15%%)", expected_pct);
$stop;
end
@@ -77,7 +78,8 @@ module t;
mode1_trials++;
if (obj.x == 8'd0) mode1_zeros++;
else if (obj.x == 8'd255) mode1_maxes++;
end else begin
end
else begin
mode0_trials++;
if (obj.x == 8'd0) mode0_zeros++;
else if (obj.x == 8'd255) mode0_maxes++;
test_regress/t/t_randomize_dist_implication.v
+1 -2
View File
@@ -73,8 +73,7 @@ module t;
`checkd(p, 1);
`checkd(fa.enb, 1'b1);
foreach (fa.arr[i]) begin
`checkd((fa.arr[i] == 8'd10) || (fa.arr[i] == 8'd20)
|| (fa.arr[i] == 8'd30), 1'b1);
`checkd((fa.arr[i] == 8'd10) || (fa.arr[i] == 8'd20) || (fa.arr[i] == 8'd30), 1'b1);
end
end
test_regress/t/t_randomize_member_select.v
+6 -9
View File
@@ -6,29 +6,26 @@
class B;
rand int insideB;
constraint i {
insideB inside {[0:10]};
};
constraint i {insideB inside {[0 : 10]};}
;
endclass
class A;
rand logic[31:0] rdata;
rand logic [31:0] rdata;
rand int delay;
int i = 97;
rand B b;
function new();
b = new;
endfunction
constraint delay_bounds {
delay inside {[0:2]};
}
constraint delay_bounds {delay inside {[0 : 2]};}
endclass
module t;
A a;
int i;
int delay;
logic[31:0] rdata;
logic [31:0] rdata;
int b;
initial begin
a = new;
@@ -41,7 +38,7 @@ module t;
if (a.b.randomize() with {a.b.insideB < 3;} == 0) $stop;
if (a.delay == 1 && a.rdata != 97) $stop;
if (a.b.insideB >= 3) $stop;
if (a.randomize() with {if (a.delay == 1) a.rdata == local::i;} == 0) $stop;
if (a.randomize() with {if (a.delay == 1) a.rdata == local:: i;} == 0) $stop;
if (a.delay == 1 && a.rdata != 7) $stop;
end
$write("*-* All Finished *-*\n");
test_regress/t/t_randomize_method_constraints.v
+1 -1
View File
@@ -60,7 +60,7 @@ module t;
$display("-------------------");
if (!(obj.v inside {ONE, THREE})) $stop;
if (obj.w != 5) $stop;
if (!(obj.x inside {1,2,4,5})) $stop;
if (!(obj.x inside {1, 2, 4, 5})) $stop;
if (obj.z <= 13 || obj.z >= 21) $stop;
if (obj.redor != 1) $stop;
end
test_regress/t/t_randomize_method_with.v
+11 -11
View File
@@ -97,9 +97,9 @@ class Cls2 extends Cls;
rand int c;
endclass
module mwith();
submodule sub1();
submodule sub2();
module mwith ();
submodule sub1 ();
submodule sub2 ();
function automatic int return_3();
return 3;
@@ -131,28 +131,28 @@ module mwith();
if (foo.a <= 1) $stop;
sub1.sub_var = foo.a;
end else
$display("Failed to randomize foo with inline constraints");
end
else $display("Failed to randomize foo with inline constraints");
end
if (cls.randomize() with { b == 1;} != 1) $stop;
if (cls.randomize() with {b == 1;} != 1) $stop;
if (cls.b != 1) $stop;
`check_rand(cls2, cls2.a);
`check_rand(cls2, cls2.c);
// Check randomize as a task
// verilator lint_off IGNOREDRETURN
cls.randomize() with { b == 2;};
cls.randomize() with {b == 2;};
// verilator lint_on IGNOREDRETURN
if (cls.b != 2) $stop;
// Check capture of a static variable
if (foo.randomize() with { a > sub1.sub_var; } != 1) $stop;
if (foo.randomize() with {a > sub1.sub_var;} != 1) $stop;
// Check reference to a function
if (foo.randomize() with { a > return_2(); } != 1) $stop;
if (foo.randomize() with {a > return_2();} != 1) $stop;
// Check randomization of class with no constraints
if (baz.randomize() with { v inside {[2:10]}; } != 1) $stop;
if (baz1.randomize() with { v inside {[2:10]}; } != 1) $stop;
if (baz.randomize() with {v inside {[2 : 10]};} != 1) $stop;
if (baz1.randomize() with {v inside {[2 : 10]};} != 1) $stop;
// Check randomization with captured non-static variable from different AstNodeModule
if (!bar.test_capture_of_callers_derived_var(foo)) $stop;
// Check randomization with non-captured non-static variable from different AstNodeModule
test_regress/t/t_randomize_nested_dynamic_array.v
+1 -3
View File
@@ -5,9 +5,7 @@
// SPDX-FileCopyrightText: 2026 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0
typedef struct {
rand bit values[];
} Element;
typedef struct {rand bit values[];} Element;
class Container;
rand Element elements[];
test_regress/t/t_randomize_queue_size.v
+3 -5
View File
@@ -25,7 +25,7 @@ end
class Foo;
rand int q[$];
rand int q2[$][$];
int x = 1;
int x = 1;
constraint c {
q.size() == 15;
q2.size() == 10;
@@ -72,10 +72,8 @@ module t;
void'(baz.randomize());
if (baz.foo_arr.size() != 7) $stop;
for (int i = 0; i < 4; i++)
if (baz.foo_arr[i] == null) $stop;
for (int i = 4; i < 7; i++)
if (baz.foo_arr[i] != null) $stop;
for (int i = 0; i < 4; i++) if (baz.foo_arr[i] == null) $stop;
for (int i = 4; i < 7; i++) if (baz.foo_arr[i] != null) $stop;
if (baz.foo_arr[2].x != 2) $stop;
`check_rand(baz, baz.foo_arr[1].q[5], 1'b1);
test_regress/t/t_randomize_queue_size_element.v
+4 -7
View File
@@ -60,9 +60,7 @@ module t;
automatic SizeElemDynArr obj3 = new;
`check_rand(obj, obj.q[0],
obj.q.size() > 1 && obj.q.size() < 6
&& obj.q[0] > 100
&& obj.q[1] == obj.q[0] + 1);
obj.q.size() > 1 && obj.q.size() < 6 && obj.q[0] > 100 && obj.q[1] == obj.q[0] + 1);
`check_rand(obj2, obj2.q[0],
obj2.min_sz inside {[2:4]}
@@ -71,10 +69,9 @@ module t;
&& obj2.q[obj2.q.size() - 1] inside {[10:20]}
&& obj2.q[0] != obj2.q[obj2.q.size() - 1]);
`check_rand(obj3, obj3.da[0],
obj3.da.size() inside {[3:5]}
&& obj3.da[0] < 50
&& obj3.da[obj3.da.size() - 1] > 50);
`check_rand(
obj3, obj3.da[0],
obj3.da.size() inside {[3 : 5]} && obj3.da[0] < 50 && obj3.da[obj3.da.size()-1] > 50);
$write("*-* All Finished *-*\n");
$finish;
test_regress/t/t_randomize_randmode_subobj.v
+1 -1
View File
@@ -34,7 +34,7 @@ endclass
class OuterClass;
rand InnerClass nested;
rand bit [7:0] outer_val;
constraint outer_c { outer_val inside {[8'd1 : 8'd20]}; }
constraint outer_c {outer_val inside {[8'd1 : 8'd20]};}
function new();
nested = new();
outer_val = 0;
test_regress/t/t_randomize_reseed_batch.v
+1 -1
View File
@@ -16,7 +16,7 @@
module t;
class C;
rand bit [7:0] a;
constraint c { a < 20; }
constraint c {a < 20;}
endclass
initial begin
test_regress/t/t_randomize_scoped_arg_array_randmode.v
+30 -15
View File
@@ -15,7 +15,7 @@ typedef int unsigned uint;
class Base;
rand uint delay;
rand uint guard; // gets rand_mode(0) to engage the per-var mode machinery
constraint delay_c {delay inside {[1:100]};}
constraint delay_c {delay inside {[1 : 100]};}
function int rd();
return this.randomize(delay);
endfunction
@@ -23,19 +23,25 @@ endclass
class Unpacked extends Base;
rand uint a[3];
constraint c {foreach (a[i]) a[i] inside {[1:10]};}
constraint c {
foreach (a[i])
a[i] inside {[1 : 10]};
}
endclass
class Unpacked2D extends Base;
rand uint a[2][2];
constraint c {foreach (a[i, j]) a[i][j] inside {[1:10]};}
constraint c {
foreach (a[i, j])
a[i][j] inside {[1 : 10]};
}
endclass
class Queue extends Base;
rand uint a[$];
constraint c {
a.size() == 3;
foreach (a[i]) a[i] inside {[1:10]};
foreach (a[i]) a[i] inside {[1 : 10]};
}
endclass
@@ -43,7 +49,7 @@ class Dyn extends Base;
rand uint a[];
constraint c {
a.size() == 3;
foreach (a[i]) a[i] inside {[1:10]};
foreach (a[i]) a[i] inside {[1 : 10]};
}
endclass
@@ -51,8 +57,8 @@ endclass
class AssocStr extends Base;
rand uint amap[string];
constraint c {
amap["alice"] inside {[1:10]};
amap["bob"] inside {[20:30]};
amap["alice"] inside {[1 : 10]};
amap["bob"] inside {[20 : 30]};
}
function new();
amap = '{"alice": 5, "bob": 25};
@@ -61,12 +67,15 @@ endclass
class EmptyAssoc extends Base; // never populated: frozen default 0 violates
rand uint amap[string];
constraint c {amap["alice"] inside {[1:10]};}
constraint c {amap["alice"] inside {[1 : 10]};}
endclass
class AssocInt extends Base;
rand uint imap[int];
constraint c {foreach (imap[k]) imap[k] inside {[1:10]};}
constraint c {
foreach (imap[k])
imap[k] inside {[1 : 10]};
}
/* verilator lint_on SIDEEFFECT */
function new();
imap[2] = 1;
@@ -76,14 +85,20 @@ endclass
class Leaf;
rand uint a[3];
constraint c {foreach (a[i]) a[i] inside {[1:10]};}
constraint c {
foreach (a[i])
a[i] inside {[1 : 10]};
}
endclass
class Nested;
rand uint x;
rand Leaf leaf;
constraint xc {x inside {[1:100]};}
constraint lc {foreach (leaf.a[i]) leaf.a[i] inside {[1:10]};}
constraint xc {x inside {[1 : 100]};}
constraint lc {
foreach (leaf.a[i])
leaf.a[i] inside {[1 : 10]};
}
function new();
leaf = new;
endfunction
@@ -93,9 +108,9 @@ class NoModes; // no rand_mode() call anywhere; scoped arg only
rand uint x, y;
rand uint arr[2];
constraint c {
x inside {[1:100]};
y inside {[1:100]};
foreach (arr[i]) arr[i] inside {[1:10]};
x inside {[1 : 100]};
y inside {[1 : 100]};
foreach (arr[i]) arr[i] inside {[1 : 10]};
}
function int rx();
return this.randomize(x);
test_regress/t/t_randomize_soft.v
+9 -9
View File
@@ -15,36 +15,36 @@
// Case 1: Only soft, no hard -- soft should be satisfied
class Case1;
rand int x;
constraint c_soft { soft x == 5; }
constraint c_soft {soft x == 5;}
endclass
// Case 2: Two soft on same var -- last-wins (c_b declared after c_a)
class Case2;
rand int x;
constraint c_a { soft x == 5; }
constraint c_b { soft x == 10; }
constraint c_a {soft x == 5;}
constraint c_b {soft x == 10;}
endclass
// Case 3: Soft on different vars -- both should be satisfied
class Case3;
rand int x;
rand int y;
constraint c_x { soft x == 7; }
constraint c_y { soft y == 3; }
constraint c_x {soft x == 7;}
constraint c_y {soft y == 3;}
endclass
// Case 4: Soft range partially covered by hard -- SAT at intersection
class Case4;
rand int x;
constraint c_soft { soft x inside {[1:10]}; }
constraint c_hard { x inside {[5:15]}; }
constraint c_soft {soft x inside {[1 : 10]};}
constraint c_hard {x inside {[5 : 15]};}
endclass
// Case 5: Soft completely overridden by hard -- hard wins
class Case5;
rand int x;
constraint c_soft { soft x == 5; }
constraint c_hard { x > 10; }
constraint c_soft {soft x == 5;}
constraint c_hard {x > 10;}
endclass
module t;
test_regress/t/t_randomize_soft_cross_object.v
+5 -3
View File
@@ -24,9 +24,11 @@ endclass
class parent_cfg_c;
rand bit enabled;
rand sub_cfg_c sub_a;
constraint soft_defaults { soft enabled == 0; }
constraint soft_defaults {soft enabled == 0;}
constraint propagate_cons {
if (enabled) { sub_a.enabled == 1; }
if (enabled) {
sub_a.enabled == 1;
}
}
function new();
sub_a = new();
@@ -36,7 +38,7 @@ endclass
class top_test_c;
rand parent_cfg_c cfg;
rand sub_cfg_c extra_cfg;
constraint cfg_hard_cons { cfg.enabled == 1; }
constraint cfg_hard_cons {cfg.enabled == 1;}
constraint cfg_soft_cons {
soft cfg.sub_a.timeout == 5000;
soft extra_cfg.timeout == 9999;
test_regress/t/t_randomize_soft_relaxation.v
+7 -4
View File
@@ -24,10 +24,13 @@
class SoftRelax;
rand bit [7:0] a;
rand bit [7:0] b;
constraint c_hard { a < 8'd200; b < 8'd200; }
constraint c_soft0 { soft b > 8'd100; }
constraint c_soft1 { soft a == 8'd30; }
constraint c_soft2 { soft a == 8'd80; }
constraint c_hard {
a < 8'd200;
b < 8'd200;
}
constraint c_soft0 {soft b > 8'd100;}
constraint c_soft1 {soft a == 8'd30;}
constraint c_soft2 {soft a == 8'd80;}
endclass
module t;
test_regress/t/t_randomize_solve_before_foreach.v
+4 -8
View File
@@ -32,24 +32,20 @@ module t;
rand int y;
rand int arr[4];
constraint mode_c {
mode inside {[0:3]};
}
constraint mode_c {mode inside {[0 : 3]};}
constraint data_c {
foreach (data[i]) {
solve mode before data[i];
if (mode == 0)
data[i] == 8'h00;
data[i] == 8'h00;
else
data[i] inside {[8'd1:8'd255]};
data[i] inside {[8'd1 : 8'd255]};
}
}
// Static array index in solve...before (non-foreach)
constraint arr_c {
solve arr[0] before y;
}
constraint arr_c {solve arr[0] before y;}
endclass
class Packet;
test_regress/t/t_randomize_std_array_index.v
+18 -3
View File
@@ -17,20 +17,35 @@ module t;
initial begin
repeat (30) begin
ok = std::randomize(probe, cube, i) with { i inside {[0:3]}; probe == cube[i]; };
ok = std::randomize(
probe, cube, i
) with {
i inside {[0 : 3]};
probe == cube[i];
};
if (ok != 1) $stop;
if (probe != cube[i]) $stop;
end
repeat (30) begin
ok = std::randomize(p0, cube, i) with { i inside {[0:3]}; p0 == cube[i][0]; };
ok = std::randomize(
p0, cube, i
) with {
i inside {[0 : 3]};
p0 == cube[i][0];
};
if (ok != 1) $stop;
if (p0 != cube[i][0]) $stop;
end
repeat (30) begin
q = {8'h1, 8'h2, 8'h3, 8'h4};
ok = std::randomize(p0, q, i) with { i inside {[0:3]}; p0 == q[i]; };
ok = std::randomize(
p0, q, i
) with {
i inside {[0 : 3]};
p0 == q[i];
};
if (ok != 1) $stop;
if (p0 != q[i]) $stop;
end
test_regress/t/t_randomize_std_param_extends.v
+2 -2
View File
@@ -37,7 +37,7 @@ package my_pkg;
task test_std_rand_with();
int unsigned v;
int ok;
ok = std::randomize(v) with { v inside {[1:100]}; };
ok = std::randomize(v) with {v inside {[1 : 100]};};
`checkd(ok, 1);
if (v < 1 || v > 100) begin
$write("%%Error: constraint violated: v=%0d\n", v);
@@ -49,7 +49,7 @@ package my_pkg;
// this.randomize() regression for parameterized-derived class
class rand_t extends uvm_sequence #(uvm_sequence_item);
rand int unsigned x;
constraint c_x { x inside {[1:50]}; }
constraint c_x {x inside {[1 : 50]};}
endclass
endpackage
test_regress/t/t_randomize_with_constraint.v
+1 -1
View File
@@ -22,7 +22,7 @@ class Cls;
rand int a[];
function new();
a = new [10];
a = new[10];
endfunction
// Randomize array inside class that is argument
test_regress/t/t_sarif_clean.v
+5 -4
View File
@@ -5,10 +5,11 @@
// SPDX-License-Identifier: CC0-1.0
module t (
input logic a,
input logic b,
input logic sel,
output logic c);
input logic a,
input logic b,
input logic sel,
output logic c
);
assign c = sel ? a : b;
test_regress/t/t_timing_class.v
+1 -1
View File
@@ -121,7 +121,7 @@ module t;
end
initial #20 ec.wake;
initial #40->ec.e;
initial #40 ->ec.e;
initial begin
wc.a = #50 4;
wc.b = #10 32;
test_regress/t/t_timing_fork_join.v
+6 -6
View File
@@ -38,7 +38,7 @@ module t;
$write("fork..join_any process 2\n");
join_any
$write("back in main process\n");
#1->event1;
#1 ->event1;
#1
fork
#2 $write("fork..join_any process 1\n");
@@ -49,7 +49,7 @@ module t;
end
join_any
$write("back in main process\n");
#1->event1;
#1 ->event1;
@event1;
// Order of triggering:
// p1->event2 ==> p2->event3 ==> p3->event3 ==> p2->event2 ==> p1->event3 ==> p3->event1
@@ -58,17 +58,17 @@ module t;
#1 $write("fork..join_none process 1\n");
->event2;
@event2 $write("fork..join_none process 1 again\n");
#1->event3;
#1 ->event3;
end
begin
@event2 $write("fork..join_none process 2\n");
#1->event3;
#1 ->event3;
@event3 $write("fork..join_none process 2 again\n");
#1->event2;
#1 ->event2;
end
begin
@event3 $write("fork..join_none process 3\n");
#1->event3;
#1 ->event3;
@event3 $write("fork..join_none process 3 again\n");
->event1;
end
test_regress/t/t_timing_intra_assign.v
+38 -20
View File
@@ -5,18 +5,26 @@
// SPDX-License-Identifier: CC0-1.0
module t;
logic[3:0] val[3];
wire[3:0] #5 net[2];
logic[1:0] idx1 = 0;
logic[1:0] idx2 = 0;
logic[0:0] idx3 = 0;
int not_read = 0;
logic [3:0] val[3];
wire [3:0] #5 net[2];
logic [1:0] idx1 = 0;
logic [1:0] idx2 = 0;
logic [0:0] idx3 = 0;
int not_read = 0;
event e;
always @val $write("[%0t] val[0]=%0d val[1]=%0d val[2]=%0d net[0]=%0d net[1]=%0d\n",
$time, val[0], val[1], val[2], net[0], net[1]);
always @val
$write(
"[%0t] val[0]=%0d val[1]=%0d val[2]=%0d net[0]=%0d net[1]=%0d\n",
$time,
val[0],
val[1],
val[2],
net[0],
net[1]
);
assign {net[0], net[1]} = {val[1], 4'hf-val[1]};
assign {net[0], net[1]} = {val[1], 4'hf - val[1]};
assign #4 val[1] = val[0];
assign #6 val[2] = val[0];
@@ -29,39 +37,49 @@ module t;
always #10 begin // always so we can use NBA
val[0] = 1;
#10 val[0] = 2;
fork #5 val[0] = 3; join_none
fork
#5 val[0] = 3;
join_none
val[0] = #10 val[0] + 2;
val[0] <= #10 val[idx1] + 2;
fork begin #5
val[0] = 5;
fork
begin
#5 val[0] = 5;
idx1 = 0;
idx2 = 0;
idx3 = 0;
#40 ->e;
end join_none
end
join_none
idx1 = 2;
idx2 = 3;
idx3 = 1;
val[idx1][idx2[idx3+:2]] = #20 1;
@e val[0] = 8;
fork begin
fork
begin
#1 val[0] = 9;
#2 ->e;
end join_none
end
join_none
val[0] = @e val[0] + 2;
val[0] <= @e val[0] + 2;
fork begin
fork
begin
#1 val[0] = 11;
end join_none
end
join_none
#2 ->e;
idx1 = 0;
idx2 = 0;
idx3 = 0;
fork begin #2
idx1 = 2;
fork
begin
#2 idx1 = 2;
idx2 = 3;
idx3 = 1;
end join_none
end
join_none
#1 val[idx1[idx3+:2]][idx2] <= @e 1;
#1 ->e;
#1 $write("*-* All Finished *-*\n");
test_regress/t/t_timing_off.v
+2 -2
View File
@@ -31,9 +31,9 @@ module t;
$finish;
end
initial #2->e1;
initial #2 ->e1;
// verilator timing_off
initial #2->e2;
initial #2 ->e2;
// verilator timing_on
initial #3 $stop; // timeout
initial #1 @(e1, e2) #1 $stop; // timeout
test_regress/t/t_timing_pong.v
+2 -2
View File
@@ -26,10 +26,10 @@ module t;
`ifdef TEST_VERBOSE
$write("pong\n");
`endif
if (cnt < 10)->ping;
if (cnt < 10) ->ping;
end
initial #1->ping;
initial #1 ->ping;
initial
#2
if (cnt == 10) begin
test_regress/t/t_timing_strobe.v
+3 -3
View File
@@ -23,11 +23,11 @@ module t;
initial begin
@e1 v = 1;
#1->e2;
#1 ->e2;
@e1 v = 2;
#1->e2;
#1 ->e2;
@e1 v = 3;
#1->e2;
#1 ->e2;
end
initial #5 $stop; // timeout
test_regress/t/t_timing_unset2.out
+1 -1
View File
@@ -5,7 +5,7 @@
... For error description see https://verilator.org/warn/NEEDTIMINGOPT?v=latest
%Error-NEEDTIMINGOPT: t/t_timing_off.v:34:11: Use --timing or --no-timing to specify how delays should be handled
: ... note: In instance 't'
34 | initial #2->e1;
34 | initial #2 ->e1;
| ^
%Error-NEEDTIMINGOPT: t/t_timing_off.v:38:11: Use --timing or --no-timing to specify how delays should be handled
: ... note: In instance 't'
test_regress/t/t_trace_event.v
+1 -1
View File
@@ -30,7 +30,7 @@ module t;
for (i = 0; i < 10; i++) begin
@(posedge clk);
if (i == 5)->ev_test;
if (i == 5) ->ev_test;
end
@(posedge clk);
test_regress/t/t_var_ref_port.v
+11 -4
View File
@@ -44,21 +44,28 @@ module t;
// verilator lint_on MULTIDRIVEN
int w = 15;
sub s (clk, cyc, x);
sub s (
clk,
cyc,
x
);
subtask st (.z(w));
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 2) begin
`checkd(x, 100) // Written by 's'
end else if (cyc == 3) begin
end
else if (cyc == 3) begin
x <= 200;
end else if (cyc == 4) begin
end
else if (cyc == 4) begin
`checkd(x, 200)
st.check(15);
w = 16;
st.check(16);
end else if (cyc == 5) begin
end
else if (cyc == 5) begin
`checkd(w, 16)
$write("*-* All Finished *-*\n");
$finish;