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23 lines
527 B
Systemverilog
23 lines
527 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Verilator Authors.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {rand bit values[];} Element;
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class Container;
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rand Element elements[];
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endclass
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module t;
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initial begin
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automatic Container object = new;
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void'(object.randomize());
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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