From 4e6eafd9941f49f02c3275151eb5802b51e518d3 Mon Sep 17 00:00:00 2001
From: Pawel Kojma <pkojma@internships.antmicro.com>
Date: Wed, 11 Mar 2026 11:01:33 +0100
Subject: [PATCH] Allow constant expressions without parentheses in PATHPULSE$
 declaration (#7199)

---
 src/verilog.y                | 17 ++++++++---------
 test_regress/t/t_specparam.v |  7 ++++++-
 2 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/verilog.y b/src/verilog.y
index 76ca9f54e..adf3e6df0 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3038,13 +3038,9 @@ delay_value<nodeExprp>:         // ==IEEE:delay_value
         |       y1STEP                                  { $$ = new AstConst{$<fl>1, AstConst::OneStep{}}; }
         ;
 
-delayExpr<nodeExprp>:
-                expr                                    { $$ = $1; }
-        ;
-
 minTypMax<nodeExprp>:           // IEEE: mintypmax_expression and constant_mintypmax_expression
-                delayExpr                               { $$ = $1; }
-        |       delayExpr ':' delayExpr ':' delayExpr   { $$ = $3; MINTYPMAXDLYUNSUP($3); DEL($1); DEL($5); }
+                expr                               { $$ = $1; }
+        |       expr ':' expr ':' expr { $$ = $3; MINTYPMAXDLYUNSUP($3); DEL($1); DEL($5); }
         ;
 
 minTypMaxE<nodeExprp>:
@@ -5935,10 +5931,13 @@ specparam_assignment<varp>:     // ==IEEE: specparam_assignment
                 idNotPathpulse sigAttrListE '=' minTypMax
                         { $$ = VARDONEA($<fl>1, *$1, nullptr, $2);
                           if ($4) $$->valuep($4); }
-        //                      //  IEEE: pulse_control_specparam
-        |       idPathpulse sigAttrListE '=' '(' minTypMax ')'
+        //                      // IEEE: pulse_control_specparam
+        //                      // LRM grammar requires '(' as the first token after assignment,
+        //                      // but IEEE provides an example in 30.7.1 where it is omitted.
+        //                      // Other simulators also support it.
+        |       idPathpulse sigAttrListE '=' minTypMax
                         { $$ = VARDONEA($<fl>1, *$1, nullptr, $2);
-                          if ($5) $$->valuep($5); }
+                          if ($4) $$->valuep($4); }
         |       idPathpulse sigAttrListE '=' '(' minTypMax ',' minTypMax ')'
                         { $$ = VARDONEA($<fl>1, *$1, nullptr, $2);
                           if ($5) $$->valuep($5);
diff --git a/test_regress/t/t_specparam.v b/test_regress/t/t_specparam.v
index 72ea9a930..188e7e90c 100644
--- a/test_regress/t/t_specparam.v
+++ b/test_regress/t/t_specparam.v
@@ -1,9 +1,10 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed under the Creative Commons Public Domain.
-// SPDX-FileCopyrightText: 2025 Wilson Snyder
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
+
 module t;
   specify
     specparam tdevice_PU = 3e8;
@@ -13,6 +14,10 @@ module t;
     specparam PATHPULSE$a$b = (3.0:3.1:3.2, 4.0:4.1:4.2);
     specparam PATHPULSE$a$c = (3.0:3.1:3.2);
     specparam randomize = 1;  // Special parser corner-case
+
+    // Not allowed by the grammar in LRM section 30.7.1,
+    // but used in an example at the end in the same section
+    specparam PATHPULSE$ = 0;
   endspecify
 
   // Support in other simulators is limited for module specparams