Fix skipping non-constrained enum constraining when inside object of other class (#8075)
Signed-off-by: Kornel Uriasz <kuriasz@antmicro.com>
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@ -5463,6 +5463,8 @@ class RandomizeVisitor final : public VNVisitor {
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AstEnumDType* const enumDtp
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= VN_CAST(subVarp->dtypep()->skipRefToEnump(), EnumDType);
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if (enumDtp) {
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// Do not emit when enum isn't constrained
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if (!subVarp->user3()) return;
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emitEnumConstraint(smtName, enumDtp);
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return;
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}
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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if not test.have_solver:
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test.skip("No constraint solver installed")
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,47 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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class Sub;
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typedef enum bit [1:0] {
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one,
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two,
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three,
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four
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} enum_t;
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rand bit num;
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rand enum_t en;
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constraint c {
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num == 0;
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};
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endclass
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class Top;
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rand Sub s;
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function new();
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s = new;
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endfunction
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endclass
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module t;
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Top top;
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initial begin
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top = new;
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`checkd(top.randomize(), 1);
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`checkd(top.s.num, 0);
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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