From 38259d11b6f6ab8f3615d50fe18085a82e9cd700 Mon Sep 17 00:00:00 2001
From: Kornel Uriasz <kuriasz@antmicro.com>
Date: Mon, 10 Aug 2026 12:52:14 +0200
Subject: [PATCH] Fix skipping non-constrained enum constraining when inside
 object of other class (#8075)

Signed-off-by: Kornel Uriasz <kuriasz@antmicro.com>
---
 src/V3Randomize.cpp                           |  2 +
 .../t/t_subclass_nonconstrained_enum.py       | 21 +++++++++
 .../t/t_subclass_nonconstrained_enum.v        | 47 +++++++++++++++++++
 3 files changed, 70 insertions(+)
 create mode 100755 test_regress/t/t_subclass_nonconstrained_enum.py
 create mode 100644 test_regress/t/t_subclass_nonconstrained_enum.v

diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 3880529d4..22be5fb38 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -5463,6 +5463,8 @@ class RandomizeVisitor final : public VNVisitor {
                               AstEnumDType* const enumDtp
                                   = VN_CAST(subVarp->dtypep()->skipRefToEnump(), EnumDType);
                               if (enumDtp) {
+                                  // Do not emit when enum isn't constrained
+                                  if (!subVarp->user3()) return;
                                   emitEnumConstraint(smtName, enumDtp);
                                   return;
                               }
diff --git a/test_regress/t/t_subclass_nonconstrained_enum.py b/test_regress/t/t_subclass_nonconstrained_enum.py
new file mode 100755
index 000000000..db1adb3f9
--- /dev/null
+++ b/test_regress/t/t_subclass_nonconstrained_enum.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+if not test.have_solver:
+    test.skip("No constraint solver installed")
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_subclass_nonconstrained_enum.v b/test_regress/t/t_subclass_nonconstrained_enum.v
new file mode 100644
index 000000000..a1b9f4360
--- /dev/null
+++ b/test_regress/t/t_subclass_nonconstrained_enum.v
@@ -0,0 +1,47 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
+
+class Sub;
+  typedef enum bit [1:0] {
+    one,
+    two,
+    three,
+    four
+  } enum_t;
+
+  rand bit num;
+  rand enum_t en;
+
+  constraint c {
+    num == 0;
+  };
+endclass
+
+class Top;
+  rand Sub s;
+
+  function new();
+    s = new;
+  endfunction
+endclass
+
+module t;
+  Top top;
+  initial begin
+    top = new;
+
+    `checkd(top.randomize(), 1);
+    `checkd(top.s.num, 0);
+
+    $write("*-* All Finished *-*\n");
+    $finish();
+  end
+endmodule