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Ignore gate delays in UDP cells

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This commit is contained in:
Wilson Snyder
2010-01-07 22:44:30 -05:00
parent a94f5ba200
commit 2950f77dbc
6 changed files with 36 additions and 10 deletions
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src/V3EmitV.cpp
+3 -3
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@@ -66,10 +66,10 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
virtual void visit(AstNetlist* nodep, AstNUser*) {
nodep->iterateChildren(*this);
}
virtual void visit(AstModule* nodep, AstNUser*) {
putfs(nodep, "module "+modClassName(nodep)+";\n");
virtual void visit(AstNodeModule* nodep, AstNUser*) {
putfs(nodep, nodep->verilogKwd()+" "+modClassName(nodep)+";\n");
nodep->iterateChildren(*this);
putqs(nodep, "endmodule\n");
putqs(nodep, "end"+nodep->verilogKwd()+"\n");
}
virtual void visit(AstNodeFTask* nodep, AstNUser*) {
putfs(nodep, nodep->isFunction() ? "function":"task");