diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 651a1f0f4..19aca66ae 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -873,6 +873,7 @@ struct AstModule : public AstNodeModule { AstModule(FileLine* fl, const string& name) : AstNodeModule (fl,name) {} ASTNODE_NODE_FUNCS(Module, MODULE) + virtual string verilogKwd() const { return "module"; } }; struct AstPackage : public AstNodeModule { @@ -880,10 +881,19 @@ struct AstPackage : public AstNodeModule { AstPackage(FileLine* fl, const string& name) : AstNodeModule (fl,name) {} ASTNODE_NODE_FUNCS(Package, PACKAGE) + virtual string verilogKwd() const { return "package"; } static string dollarUnitName() { return AstNode::encodeName("$unit"); } bool isDollarUnit() const { return name() == dollarUnitName(); } }; +struct AstPrimitive : public AstNodeModule { + // A primitive declaration + AstPrimitive(FileLine* fl, const string& name) + : AstNodeModule (fl,name) {} + ASTNODE_NODE_FUNCS(Primitive, PRIMITIVE) + virtual string verilogKwd() const { return "primitive"; } +}; + struct AstPackageImport : public AstNode { private: // A package import declaration diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index c99d4f3eb..181159ccf 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -66,10 +66,10 @@ class EmitVBaseVisitor : public EmitCBaseVisitor { virtual void visit(AstNetlist* nodep, AstNUser*) { nodep->iterateChildren(*this); } - virtual void visit(AstModule* nodep, AstNUser*) { - putfs(nodep, "module "+modClassName(nodep)+";\n"); + virtual void visit(AstNodeModule* nodep, AstNUser*) { + putfs(nodep, nodep->verilogKwd()+" "+modClassName(nodep)+";\n"); nodep->iterateChildren(*this); - putqs(nodep, "endmodule\n"); + putqs(nodep, "end"+nodep->verilogKwd()+"\n"); } virtual void visit(AstNodeFTask* nodep, AstNUser*) { putfs(nodep, nodep->isFunction() ? "function":"task"); diff --git a/src/V3Link.cpp b/src/V3Link.cpp index 6285d06b4..7eb85a710 100644 --- a/src/V3Link.cpp +++ b/src/V3Link.cpp @@ -67,6 +67,7 @@ private: // STATE // Below state needs to be preserved between each module call. AstPackage* m_packagep; // Current package + AstCell* m_cellp; // Current cell AstNodeModule* m_modp; // Current module AstNodeFTask* m_ftaskp; // Current function/task IdState m_idState; // Id linking mode (find or resolve) @@ -215,6 +216,7 @@ private: virtual void visit(AstNodeModule* nodep, AstNUser*) { // Module: Create sim table for entire module and iterate UINFO(2,"Link Module: "<name()); @@ -528,6 +533,7 @@ private: nodep->iterateChildren(*this); } } + m_cellp = NULL; // Parent module inherits child's publicity // This is done bottom up in the LinkBotupVisitor stage } @@ -574,12 +580,17 @@ private: } virtual void visit(AstPin* nodep, AstNUser*) { - // Pin: Link to submodule's pin + // Pin: Link to submodule's port // ONLY CALLED by AstCell during ID_RESOLVE and ID_PARAM state if (m_idState==ID_RESOLVE && !nodep->modVarp()) { if (!m_cellVarsp) nodep->v3fatalSrc("Pin not under cell?\n"); AstVar* refp = m_cellVarsp->findIdFlat(nodep->name())->castVar(); if (!refp) { + if (nodep->name() == "__paramNumber1" && m_cellp->modp()->castPrimitive()) { + // Primitive parameter is really a delay we can just ignore + nodep->unlinkFrBack()->deleteTree(); nodep=NULL; + return; + } nodep->v3error("Pin not found: "<prettyName()); } else if (!refp->isIO() && !refp->isParam()) { nodep->v3error("Pin is not an in/out/inout/param: "<prettyName()); @@ -592,6 +603,7 @@ private: if (m_idState==ID_PARAM && !nodep->svImplicit()) { // SV 19.11.3: .name pins don't allow implicit decls pinImplicitExprRecurse(nodep->exprp()); } + // Early return() above when deleted } virtual void visit(AstAssignW* nodep, AstNUser*) { @@ -617,7 +629,7 @@ private: // Unsupported gates need implicit creation pinImplicitExprRecurse(nodep); // We're done with implicit gates - nodep->unlinkFrBack()->deleteTree(); + nodep->unlinkFrBack()->deleteTree(); nodep=NULL; } virtual void visit(AstDefParam* nodep, AstNUser*) { @@ -666,6 +678,7 @@ public: LinkVisitor(AstNetlist* rootp) { m_curVarsp = NULL; m_cellVarsp = NULL; + m_cellp = NULL; m_modp = NULL; m_ftaskp = NULL; m_packagep = NULL; diff --git a/src/verilog.y b/src/verilog.y index a23fcb516..8bdd19f61 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -694,7 +694,7 @@ modFront: udpFront: yPRIMITIVE lifetimeE idAny - { $$ = new AstModule($1,*$3); $$->inLibrary(true); + { $$ = new AstPrimitive($1,*$3); $$->inLibrary(true); $$->modTrace(false); $$->addStmtp(new AstPragma($1,AstPragmaType::INLINE_MODULE)); PARSEP->fileline()->tracingOn(false); @@ -708,6 +708,7 @@ parameter_value_assignmentE: // IEEE: [ parameter_value_assignment ] | '#' '(' cellpinList ')' { $$ = $3; } // // Parentheses are optional around a single parameter | '#' yaINTNUM { $$ = new AstPin($1,1,"",new AstConst($1,*$2)); } + | '#' yaFLOATNUM { $$ = new AstPin($1,1,"",new AstConst($1,AstConst::Unsized32(),(int)(($2<0)?($2-0.5):($2+0.5)))); } | '#' idClassSel { $$ = new AstPin($1,1,"",$2); } // // Not needed in Verilator: // // Side effect of combining *_instantiations @@ -1655,6 +1656,8 @@ cellpinItemE: // IEEE: named_port_connection + named_parameter_assignment //UNSUP data_type { PINDONE($1->fileline(),"",$1); GRAMMARP->pinNumInc(); } // | expr { $$ = new AstPin($1->fileline(),PINNUMINC(),"",$1); } + // // Floatnum should only occur with UDPs, but since ports aren't floats, it's legal to round always + | yaFLOATNUM { $$ = new AstPin($1,PINNUMINC(),"",new AstConst($1,AstConst::Unsized32(),(int)(($1<0)?($1-0.5):($1+0.5)))); } ; //************************************************ diff --git a/test_regress/t/t_udp.v b/test_regress/t/t_udp.v index ab3ba677f..f39f35209 100644 --- a/test_regress/t/t_udp.v +++ b/test_regress/t/t_udp.v @@ -31,9 +31,9 @@ module t (/*AUTOARG*/ //====== Mux wire [1:0] qm; - // z a b sel - udp_mux2 m0 (qm[0], in[0], in[2], in[4]); - udp_mux2 m1 (qm[1], in[1], in[3], in[4]); + // delay z a b sel + udp_mux2 #(0.1) m0 (qm[0], in[0], in[2], in[4]); + udp_mux2 #0.1 m1 (qm[1], in[1], in[3], in[4]); `define verilatorxx `ifdef verilatorxx diff --git a/test_regress/t/t_udp_lint.pl b/test_regress/t/t_udp_lint.pl index 780526d5e..718e795a3 100755 --- a/test_regress/t/t_udp_lint.pl +++ b/test_regress/t/t_udp_lint.pl @@ -13,7 +13,7 @@ compile ( # Unsupported: UDP Tables make_top_shell => 0, make_main => 0, - v_flags2 => ["--lint-only --bbox-unsup"], + verilator_flags2 => ["--lint-only --bbox-unsup"], verilator_make_gcc => 0, );