--bbox-unsup now ignores cmos and tran gate primitives
This commit is contained in:
Wilson Snyder
parent
0c4e40102f
commit
a94f5ba200
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@ -296,8 +296,9 @@ calls.
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=item --bbox-unsup
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Black box some unsupported language features, currently UDP tables. This
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may allow linting when unsupported constructs are present.
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Black box some unsupported language features, currently UDP tables and the
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cmos and tran gate primitives. This may enable linting the rest of the
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design even when unsupported constructs are present.
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=item --bin I<filename>
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@ -689,6 +689,17 @@ public:
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string path() const { return m_path; }
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};
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struct AstImplicit : public AstNode {
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// Create implicit wires and do nothing else, for gates that are ignored
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// Parents: MODULE
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AstImplicit(FileLine* fl, AstNode* exprsp)
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: AstNode(fl) {
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addNOp1p(exprsp);
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}
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ASTNODE_NODE_FUNCS(Implicit, IMPLICIT)
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AstNode* exprsp() const { return op1p()->castNode(); } // op1 = Assign from
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};
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struct AstScope : public AstNode {
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// A particular usage of a cell
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// Parents: MODULE
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@ -603,6 +603,22 @@ private:
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}
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstAssignAlias* nodep, AstNUser*) {
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// tran gates need implicit creation
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if (AstVarRef* forrefp = nodep->lhsp()->castVarRef()) {
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createImplicitVar(forrefp, false);
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}
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if (AstVarRef* forrefp = nodep->rhsp()->castVarRef()) {
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createImplicitVar(forrefp, false);
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}
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstImplicit* nodep, AstNUser*) {
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// Unsupported gates need implicit creation
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pinImplicitExprRecurse(nodep);
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// We're done with implicit gates
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nodep->unlinkFrBack()->deleteTree();
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}
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virtual void visit(AstDefParam* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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@ -76,6 +76,7 @@ struct V3ParseBisonYYSType {
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AstRange* rangep;
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AstSenTree* sentreep;
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AstVar* varp;
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AstVarRef* varrefp;
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};
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};
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@ -203,6 +203,7 @@ escid \\[^ \t\f\r\n]+
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"case" { FL; return yCASE; }
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"casex" { FL; return yCASEX; }
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"casez" { FL; return yCASEZ; }
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"cmos" { FL; return yCMOS; }
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"default" { FL; return yDEFAULT; }
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"defparam" { FL; return yDEFPARAM; }
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"disable" { FL; return yDISABLE; }
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@ -228,6 +229,7 @@ escid \\[^ \t\f\r\n]+
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"module" { FL; return yMODULE; }
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"nand" { FL; return yNAND; }
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"negedge" { FL; return yNEGEDGE; }
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"nmos" { FL; return yNMOS; }
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"nor" { FL; return yNOR; }
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"not" { FL; return yNOT; }
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"notif0" { FL; return yNOTIF0; }
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@ -235,12 +237,19 @@ escid \\[^ \t\f\r\n]+
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"or" { FL; return yOR; }
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"output" { FL; return yOUTPUT; }
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"parameter" { FL; return yPARAMETER; }
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"pmos" { FL; return yPMOS; }
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"posedge" { FL; return yPOSEDGE; }
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"primitive" { FL; return yPRIMITIVE; }
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"pulldown" { FL; return yPULLDOWN; }
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"pullup" { FL; return yPULLUP; }
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"rcmos" { FL; return yRCMOS; }
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"reg" { FL; return yREG; }
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"repeat" { FL; return yREPEAT; }
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"rnmos" { FL; return yRNMOS; }
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"rpmos" { FL; return yRPMOS; }
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"rtran" { FL; return yRTRAN; }
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"rtranif0" { FL; return yRTRANIF0; }
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"rtranif1" { FL; return yRTRANIF1; }
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"scalared" { FL; return ySCALARED; }
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"specify" { FL; return ySPECIFY; }
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"specparam" { FL; return ySPECPARAM; }
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@ -249,6 +258,9 @@ escid \\[^ \t\f\r\n]+
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"table" { yy_push_state(TABLE); FL; return yTABLE; }
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"task" { FL; return yTASK; }
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"time" { FL; return yTIME; }
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"tran" { FL; return yTRAN; }
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"tranif0" { FL; return yTRANIF0; }
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"tranif1" { FL; return yTRANIF1; }
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"tri" { FL; return yTRI; }
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"vectored" { FL; return yVECTORED; }
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"while" { FL; return yWHILE; }
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@ -269,7 +281,6 @@ escid \\[^ \t\f\r\n]+
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"$writeh" { FL; RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%x format instead: %s",yytext); }
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"$writeo" { FL; RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%o format instead: %s",yytext); }
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/* Generic unsupported warnings */
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"cmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"deassign" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"event" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"force" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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@ -279,25 +290,14 @@ escid \\[^ \t\f\r\n]+
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"join" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"large" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"medium" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"nmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"pmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"pull0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"pull1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"rcmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"real" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"realtime" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"release" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"rnmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"rpmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"rtran" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"rtranif0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"rtranif1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"small" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"strong0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"strong1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"tran" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"tranif0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"tranif1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"triand" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"trior" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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"trireg" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
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@ -36,7 +36,7 @@
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// Pick up new lexer
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#define yylex PARSEP->lexToBison
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#define PSLUNSUP(what) NULL; yyerrorf("Unsupported: PSL language feature not implemented");
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#define GATEUNSUP(fl,tok) { if (!v3Global.opt.bboxUnsup()) { (fl)->v3error("Unsupported: Verilog 1995 gate primitive: "<<(tok)); } }
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extern void yyerror(const char* errmsg);
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extern void yyerrorf(const char* format, ...);
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@ -264,6 +264,7 @@ class AstSenTree;
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%token<fl> yCASEZ "casez"
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%token<fl> yCHANDLE "chandle"
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%token<fl> yCLOCKING "clocking"
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%token<fl> yCMOS "cmos"
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%token<fl> yCONTEXT "context"
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%token<fl> yCOVER "cover"
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%token<fl> yDEFAULT "default"
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@ -307,6 +308,7 @@ class AstSenTree;
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%token<fl> yMODULE "module"
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%token<fl> yNAND "nand"
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%token<fl> yNEGEDGE "negedge"
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%token<fl> yNMOS "nmos"
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%token<fl> yNOR "nor"
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%token<fl> yNOT "not"
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%token<fl> yNOTIF0 "notif0"
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@ -315,6 +317,7 @@ class AstSenTree;
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%token<fl> yOUTPUT "output"
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%token<fl> yPACKAGE "package"
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%token<fl> yPARAMETER "parameter"
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%token<fl> yPMOS "pmos"
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%token<fl> yPOSEDGE "posedge"
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%token<fl> yPRIMITIVE "primitive"
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%token<fl> yPRIORITY "priority"
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@ -323,8 +326,14 @@ class AstSenTree;
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%token<fl> yPULLDOWN "pulldown"
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%token<fl> yPULLUP "pullup"
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%token<fl> yPURE "pure"
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%token<fl> yRCMOS "rcmos"
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%token<fl> yREG "reg"
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%token<fl> yREPEAT "repeat"
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%token<fl> yRNMOS "rnmos"
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%token<fl> yRPMOS "rpmos"
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%token<fl> yRTRAN "rtran"
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%token<fl> yRTRANIF0 "rtranif0"
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%token<fl> yRTRANIF1 "rtranif1"
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%token<fl> ySCALARED "scalared"
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%token<fl> ySHORTINT "shortint"
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%token<fl> ySIGNED "signed"
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@ -339,6 +348,9 @@ class AstSenTree;
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%token<fl> yTIME "time"
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%token<fl> yTIMEPRECISION "timeprecision"
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%token<fl> yTIMEUNIT "timeunit"
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%token<fl> yTRAN "tran"
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%token<fl> yTRANIF0 "tranif0"
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%token<fl> yTRANIF1 "tranif1"
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%token<fl> yTRI "tri"
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%token<fl> yTRUE "true"
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%token<fl> yTYPEDEF "typedef"
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@ -2524,6 +2536,19 @@ gateDecl<nodep>:
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| yXNOR delayE gateXnorList ';' { $$ = $3; }
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| yPULLUP delayE gatePullupList ';' { $$ = $3; }
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| yPULLDOWN delayE gatePulldownList ';' { $$ = $3; }
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//
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| yTRAN delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"tran"); } // Unsupported
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| yNMOS delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"nmos"); } // Unsupported
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| yPMOS delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"pmos"); } // Unsupported
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| yRCMOS delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"rcmos"); } // Unsupported
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| yCMOS delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"cmos"); } // Unsupported
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| yRNMOS delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"rmos"); } // Unsupported
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| yRPMOS delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"pmos"); } // Unsupported
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| yRTRAN delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"rtran"); } // Unsupported
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| yRTRANIF0 delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"rtranif0"); } // Unsupported
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| yRTRANIF1 delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"rtranif1"); } // Unsupported
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| yTRANIF0 delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"tranif0"); } // Unsupported
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| yTRANIF1 delayE gateUnsupList ';' { $$ = $3; GATEUNSUP($3,"tranif1"); } // Unsupported
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;
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gateBufList<nodep>:
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@ -2582,6 +2607,10 @@ gatePulldownList<nodep>:
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gatePulldown { $$ = $1; }
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| gatePulldownList ',' gatePulldown { $$ = $1->addNext($3); }
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;
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gateUnsupList<nodep>:
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gateUnsup { $$ = $1; }
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| gateUnsupList ',' gateUnsup { $$ = $1->addNext($3); }
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;
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gateBuf<nodep>:
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gateIdE instRangeE '(' idClassSel ',' expr ')' { $$ = new AstAssignW ($3,$4,$6); }
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@ -2625,6 +2654,10 @@ gatePullup<nodep>:
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gatePulldown<nodep>:
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gateIdE instRangeE '(' idClassSel ')' { $$ = new AstPull ($3, $4, false); }
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;
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gateUnsup<nodep>:
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gateIdE instRangeE '(' gateUnsupPinList ')' { $$ = new AstImplicit ($3,$4); }
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;
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gateIdE:
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/*empty*/ {}
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| id {}
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@ -2642,6 +2675,10 @@ gateXorPinList<nodep>:
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expr { $$ = $1; }
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| gateXorPinList ',' expr { $$ = new AstXor($2,$1,$3); }
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;
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gateUnsupPinList<nodep>:
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expr { $$ = $1; }
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| gateUnsupPinList ',' expr { $$ = $1->addNext($3); }
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;
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strengthSpecE: // IEEE: drive_strength + pullup_strength + pulldown_strength + charge_strength - plus empty
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/* empty */ { }
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@ -2773,7 +2810,7 @@ idArrayed<nodep>: // IEEE: id + select
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;
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// VarRef without any dots or vectorizaion
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varRefBase<nodep>:
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varRefBase<varrefp>:
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id { $$ = new AstVarRef(CRELINE(),*$1,false);}
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;
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@ -19,7 +19,7 @@ module t (/*AUTOARG*/
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BF2 (bf[2], a[2]);
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// verilator lint_off IMPLICIT
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not NT0 (nt0, a[0]);
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not #(0.108) NT0 (nt0, a[0]);
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and #1 AN0 (an0, a[0], b[0]);
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nand #(2,3) ND0 (nd0, a[0], b[0], b[1]);
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or OR0 (or0, a[0], b[0]);
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@ -0,0 +1,19 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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# Unsupported: UDP Tables
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make_top_shell => 0,
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make_main => 0,
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verilator_flags2 => ["--lint-only --bbox-unsup"],
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verilator_make_gcc => 0,
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);
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ok(1);
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1;
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@ -0,0 +1,33 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Wilson Snyder.
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module t (/*AUTOARG*/);
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wire d, en, nc, pc;
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// verilator lint_off IMPLICIT
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cmos (cm0, d, nc, pc);
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rcmos (rc0, d, nc, pc);
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nmos (nm0, d, en);
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pmos (pm0, d, en);
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rnmos (rn0, d, en);
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rpmos (rp0, d, en);
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rtran (rt0, d);
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tran (tr0, d);
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rtranif0 (r00, d, en);
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rtranif1 (r10, d, en);
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tranif0 (t00, d, en);
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tranif1 (t10, d, en);
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// verilator lint_on IMPLICIT
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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