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[#72179] wip: add t_interface_ref_trace_saif test

This commit is contained in:
Mateusz Gancarz 2025-02-17 09:15:50 +01:00
parent 0d07c94d14
commit 2812f33348
2 changed files with 130 additions and 0 deletions
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109
test_regress/t/t_interface_ref_trace_saif.out Normal file
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(SAIFILE
(SAIFVERSION "2.0")
(DIRECTION "backward")
(DESIGN "foo")
(PROGRAM_NAME "Verilator")
(VERSION "5.032")
(DIVIDER .)
(TIMESCALE 1ps)
(DURATION 210)
(INSTANCE foo (NET
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(val200[10] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
)))

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test_regress/t/t_interface_ref_trace_saif.py Executable file
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_interface_ref_trace.v"
test.compile(verilator_flags2=['--trace-structs --trace-saif'])
test.execute()
test.saif_identical(test.trace_filename, test.golden_filename)
test.passes()