[#72179] wip: add t_hier_block_trace_saif test
This commit is contained in:
Mateusz Gancarz
parent
51edcdf956
commit
0d07c94d14
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@ -0,0 +1,901 @@
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(SAIFILE
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(SAIFVERSION "2.0")
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(DIRECTION "backward")
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(DESIGN "foo")
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(PROGRAM_NAME "Verilator")
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(VERSION "5.032")
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(DIVIDER .)
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(TIMESCALE 1ps)
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(DURATION 170)
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(INSTANCE foo (NET
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(exp[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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(exp[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
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(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
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(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
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(P1[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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(P0[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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(val3[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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(val3[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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(val2[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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(val1[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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(val1[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val0[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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(out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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(out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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(out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
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||||
(P1[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P1[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P1[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val2[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val1[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val1[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val0[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||||
(exp[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P1[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P1[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P1[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val2[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
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||||
(exp[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P1[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P1[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(P1[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val3[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val3[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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(val3[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val2[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val2[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val1[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val1[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val0[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val0[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
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||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
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||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
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||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
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||||
(exp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(exp[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val3[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val2[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val2[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val1[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val1[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val0[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(val0[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
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(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
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(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
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(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
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(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
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(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
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(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
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||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(sub5_out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(sub5_out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(sub5_out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(sub5_out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(sub5_in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(sub5_in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(sub5_in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(sub5_in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(sub5_in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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(sub5_in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(sub5_in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out4_2[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
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||||
(out4_2[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
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||||
(out4_2[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
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||||
(out4_2[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
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||||
(out4_2[4] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(UNPACKED_ARRAY[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(sub5_in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(sub5_in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
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||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
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(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
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||||
(out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
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||||
(P0[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(P1[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P1[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(UNUSED[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[2] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[3] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[4] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[5] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[6] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[7] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[8] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[9] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[10] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[11] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[12] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[13] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[14] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[15] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||||
(out[2] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out[4] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[0] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(in[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(in[2] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(in[3] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(in[4] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val2[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(val0[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(P0[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(ff[0] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(ff[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||||
(ff[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(ff[3] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(ff[4] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(val3[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out4_2[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out4_2[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(out4_2[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(out4_2[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out4_2[4] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(ff[0] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(ff[1] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(ff[2] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(ff[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(ff[4] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val2[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(exp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||||
(val2[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val1[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val1[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||||
(in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(exp[98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(exp[99] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(exp[100] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val0[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(val2[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(tmp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(tmp[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 9))
|
||||
(tmp[2] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(tmp[3] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(tmp[4] (T0 130) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(out2[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out2[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||||
(out2[2] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out2[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out2[4] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(tmp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(tmp[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(tmp[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(tmp[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(tmp[4] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(ff[0] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(ff[1] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(ff[2] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(ff[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(ff[4] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(WIDTH[3] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(P0[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(out[0] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(out[2] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(out[3] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out[4] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(N[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(N[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val1[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(exp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||||
(out[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(out[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(out[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out[4] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(exp[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||||
(out0[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out0[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(out0[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(out0[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out0[4] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[2] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[3] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[4] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[5] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[6] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[7] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[8] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[9] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[10] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[11] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[12] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[13] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[14] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNUSED[15] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(N[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val2[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ff[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(ff[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(ff[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(ff[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(ff[4] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out1[0] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out1[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(out1[2] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(out1[3] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out1[4] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P0[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(val0[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out3_2[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out3_2[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(out3_2[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(out3_2[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out3_2[4] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(N[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P1[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P1[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(tmp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(tmp[1] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 9))
|
||||
(tmp[2] (T0 130) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(tmp[3] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(tmp[4] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(UNPACKED_ARRAY[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(P0[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P0[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out3[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out3[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(out3[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(out3[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out3[4] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out5[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(out5[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(out5[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(out5[3] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out5[4] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P0[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(out6[0] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(out6[1] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(out6[2] (T0 140) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(out6[3] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(out6[4] (T0 150) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(P1[1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(UNPACKED_ARRAY[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(P0[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(val2[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(val0[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(P0[0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(val0[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(val2[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||||
(in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(val0[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val0[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||||
(UNPACKED_ARRAY[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val1[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(in[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(in[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(in[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(in[4] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(exp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||||
(in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(exp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||||
(exp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||||
(clk (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 33))
|
||||
(in[4] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(in[5] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(in[6] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(in[7] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(in[8] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ff[0] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(ff[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(ff[2] (T0 70) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(ff[3] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(ff[4] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ff[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(ff[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(ff[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(ff[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(ff[4] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(data[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(data[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||||
(data[2] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(data[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(data[4] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out_2[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out_2[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||||
(out_2[2] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out_2[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out_2[4] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out4_2[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out4_2[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||||
(out4_2[2] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out4_2[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out4_2[4] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val0[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val1[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val1[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val2[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_in[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][1][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][2][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[0][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][0][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][1][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(sub5_in[1][2][97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][104] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][106] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][114] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][120] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_in[1][2][121] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][0][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][1][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val0[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val1[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val1[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val2[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val3[1][1] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(exp[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(exp[98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(exp[99] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(exp[100] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(exp[0] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 15))
|
||||
(ff[0] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(ff[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||||
(ff[2] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(ff[3] (T0 110) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(ff[4] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(out4_2[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out4_2[1] (T0 80) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||||
(out4_2[2] (T0 120) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(out4_2[3] (T0 100) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(out4_2[4] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(sub5_out[0][1][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][1][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[0][2][2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][0][1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(sub5_out[1][2][0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(count[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 17))
|
||||
(count[1] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(count[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(count[3] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(count[4] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(val0[0][0] (T0 0) (T1 170) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(exp[0] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[2] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 16))
|
||||
(exp[97] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 8))
|
||||
(exp[98] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(exp[99] (T0 90) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(exp[100] (T0 160) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[0] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(j[1] (T0 20) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
)))
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#!/usr/bin/env python3
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2024 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
import vltest_bootstrap
|
||||
|
||||
test.scenarios('vlt_all')
|
||||
test.top_filename = "t/t_hier_block.v"
|
||||
|
||||
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
|
||||
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
|
||||
# So use 6 threads here though it's not optimal in performance, but ok.
|
||||
|
||||
test.compile(
|
||||
v_flags2=['t/t_hier_block.cpp'],
|
||||
verilator_flags2=[
|
||||
'--hierarchical',
|
||||
'--Wno-TIMESCALEMOD',
|
||||
'--trace-saif',
|
||||
'--no-trace-underscore', # To avoid handle mismatches
|
||||
],
|
||||
threads=(6 if test.vltmt else 1))
|
||||
|
||||
test.execute()
|
||||
|
||||
test.saif_identical(test.trace_filename, test.golden_filename)
|
||||
|
||||
test.passes()
|
||||
Loading…
Reference in New Issue