Fix randomize missing simple class rand members.
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76f5de6e54
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@ -47,6 +47,7 @@ private:
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using BaseToDerivedMap = std::unordered_map<AstClass*, DerivedSet>;
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BaseToDerivedMap m_baseToDerivedMap; // Mapping from base classes to classes that extend them
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AstClass* m_classp = nullptr; // Current class
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// METHODS
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void markMembers(AstClass* nodep) {
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@ -87,6 +88,8 @@ private:
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// VISITORS
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void visit(AstClass* nodep) override {
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VL_RESTORER(m_classp);
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m_classp = nodep;
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iterateChildrenConst(nodep);
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if (nodep->extendsp()) {
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// Save pointer to derived class
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@ -104,6 +107,11 @@ private:
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markMembers(classp);
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}
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}
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void visit(AstNodeFTaskRef* nodep) override {
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iterateChildrenConst(nodep);
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if (nodep->name() != "randomize") return;
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if (m_classp) m_classp->user1(true);
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}
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void visit(AstNode* nodep) override { iterateChildrenConst(nodep); }
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@ -0,0 +1,20 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2020 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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);
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ok(1);
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1;
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@ -0,0 +1,29 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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rand int m_val;
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function void test;
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automatic int rand_result;
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rand_result = randomize();
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if (rand_result != 1) $stop;
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endfunction
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endclass
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module t(/*AUTOARG*/);
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initial begin
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Cls c;
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c = new;
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c.test;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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