diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 409f09740..6f88a2372 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -47,6 +47,7 @@ private:
     using BaseToDerivedMap = std::unordered_map<AstClass*, DerivedSet>;
 
     BaseToDerivedMap m_baseToDerivedMap;  // Mapping from base classes to classes that extend them
+    AstClass* m_classp = nullptr;  // Current class
 
     // METHODS
     void markMembers(AstClass* nodep) {
@@ -87,6 +88,8 @@ private:
 
     // VISITORS
     void visit(AstClass* nodep) override {
+        VL_RESTORER(m_classp);
+        m_classp = nodep;
         iterateChildrenConst(nodep);
         if (nodep->extendsp()) {
             // Save pointer to derived class
@@ -104,6 +107,11 @@ private:
             markMembers(classp);
         }
     }
+    void visit(AstNodeFTaskRef* nodep) override {
+        iterateChildrenConst(nodep);
+        if (nodep->name() != "randomize") return;
+        if (m_classp) m_classp->user1(true);
+    }
 
     void visit(AstNode* nodep) override { iterateChildrenConst(nodep); }
 
diff --git a/test_regress/t/t_randomize_small.pl b/test_regress/t/t_randomize_small.pl
new file mode 100755
index 000000000..49330a5fe
--- /dev/null
+++ b/test_regress/t/t_randomize_small.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_randomize_small.v b/test_regress/t/t_randomize_small.v
new file mode 100644
index 000000000..1b91feab4
--- /dev/null
+++ b/test_regress/t/t_randomize_small.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+   rand int m_val;
+
+   function void test;
+      automatic int rand_result;
+
+      rand_result = randomize();
+      if (rand_result != 1) $stop;
+   endfunction
+endclass
+
+module t(/*AUTOARG*/);
+
+   initial begin
+      Cls c;
+      c = new;
+
+      c.test;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule