47 lines
851 B
Systemverilog
47 lines
851 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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class Sub;
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typedef enum bit [1:0] {
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ONE,
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TWO,
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THREE,
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FOUR
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} enum_t;
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rand bit num;
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rand enum_t en;
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constraint c {num == 0;}
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endclass
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class Top;
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rand Sub s;
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function new();
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s = new;
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endfunction
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endclass
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module t;
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Top top;
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initial begin
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top = new;
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`checkd(top.randomize(), 1);
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`checkd(top.s.num, 0);
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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