luke/verilator
1
0
Fork 0
mirror of https://github.com/verilator/verilator.git synced 2026-10-05 17:43:31 +02:00
Code Issues Packages Projects Releases Wiki Activity

Tests: Restore Antmicro copyright on test files accidentally overwritten (#7786)

Browse Source
This commit is contained in:
Yilou Wang
2026-06-15 08:56:34 -04:00
committed by GitHub
parent 709c444df3
commit 0233e5044c
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
test_regress/t/t_constraint_unsup.v
+1 -1
View File
@@ -1,7 +1,7 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 PlanV GmbH
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
class Packet;
test_regress/t/t_property_sexpr_multi.v
+1 -1
View File
@@ -1,7 +1,7 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 PlanV GmbH
// SPDX-FileCopyrightText: 2025 Antmicro
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off