diff --git a/test_regress/t/t_constraint_unsup.v b/test_regress/t/t_constraint_unsup.v
index 4b1c95031..84f67e5ce 100644
--- a/test_regress/t/t_constraint_unsup.v
+++ b/test_regress/t/t_constraint_unsup.v
@@ -1,7 +1,7 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed under the Creative Commons Public Domain.
-// SPDX-FileCopyrightText: 2026 PlanV GmbH
+// SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
 class Packet;
diff --git a/test_regress/t/t_property_sexpr_multi.v b/test_regress/t/t_property_sexpr_multi.v
index 9a99739e5..ff126810f 100644
--- a/test_regress/t/t_property_sexpr_multi.v
+++ b/test_regress/t/t_property_sexpr_multi.v
@@ -1,7 +1,7 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed under the Creative Commons Public Domain.
-// SPDX-FileCopyrightText: 2026 PlanV GmbH
+// SPDX-FileCopyrightText: 2025 Antmicro
 // SPDX-License-Identifier: CC0-1.0
 
 // verilog_format: off