2025-07-10 19:46:45 +02:00
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Converting cyclic DFGs into acyclic DFGs
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//
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// Code available from: https://verilator.org
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//
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//*************************************************************************
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//
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2026-01-27 02:24:34 +01:00
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
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2025-07-10 19:46:45 +02:00
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT
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#include "V3Dfg.h"
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#include "V3DfgPasses.h"
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2025-11-29 20:01:22 +01:00
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#include "V3Error.h"
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2025-07-10 19:46:45 +02:00
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#include "V3Hash.h"
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Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
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#include <algorithm>
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2025-07-10 19:46:45 +02:00
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#include <fstream>
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2026-04-19 20:48:02 +02:00
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#include <queue>
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2025-07-10 19:46:45 +02:00
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#include <unordered_map>
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#include <vector>
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VL_DEFINE_DEBUG_FUNCTIONS;
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2025-12-08 19:43:21 +01:00
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namespace V3DfgBreakCycles {
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2026-06-19 23:28:50 +02:00
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// Mutable map from vertices to the SCC index they belong to. Initialized
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// from a proper analysis, then updated as we break cycles. After updates
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// the information is consertvative, meaning a vertex that is marked as
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// cyclic might not actually be if an SCC split into multple SCCs after a
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// fixup. However it should always be true that if a vertex is thought to
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// be non-cyclic based on this datastructure, then it indeed is not cyclic.
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class SccInfo final {
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DfgGraph& m_dfg; // The annotated graph
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// The map from vertices to their SCC index (0 if trivial SCC - non cyclic)
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std::unordered_map<const DfgVertex*, uint64_t> m_vtx2Scc;
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size_t m_nCyclicVertices = 0; // Number of vertices in non-trivial SCCs
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public:
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SccInfo(DfgGraph& dfg)
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: m_dfg{dfg} {
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// Initialize m_vtx2Scc for the graph from a proper analysis
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DfgUserMap<uint64_t> vtx2Scc = dfg.makeUserMap<uint64_t>();
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V3DfgPasses::colorStronglyConnectedComponents(dfg, vtx2Scc);
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m_dfg.forEachVertex([&](const DfgVertex& vtx) {
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const uint64_t sccIdx = vtx2Scc[vtx];
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m_vtx2Scc[&vtx] = sccIdx;
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if (sccIdx) ++m_nCyclicVertices;
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});
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}
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// Is the graph cyclic still?
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bool isCyclic() const { return m_nCyclicVertices; }
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// Returns the index of the SCC the given vertex is a part of
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// This is 0 iff the vertex is in a trivial SCC (no cycles through vertex)
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uint64_t get(const DfgVertex& vtx) const { return m_vtx2Scc.at(&vtx); }
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// Add a new vertex to graph that is part of the given SCC
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void add(const DfgVertex& vtx, uint64_t sccIdx) {
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const bool newEntry = m_vtx2Scc.emplace(&vtx, sccIdx).second;
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UASSERT_OBJ(newEntry, &vtx, "Vertex already inserted");
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if (sccIdx) ++m_nCyclicVertices;
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}
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bool stillCyclicFwd(const DfgVertex& vtx) const {
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// If it only reads non-cyclic vertices, it has also become acyclic
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return vtx.foreachSource([&](const DfgVertex& src) { //
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return m_vtx2Scc.at(&src);
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});
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}
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bool stillCyclicBwd(const DfgVertex& vtx) const {
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// If itonly drives non-cyclic vertices, it has also become acyclic
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return vtx.foreachSink([&](const DfgVertex& dst) { //
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return m_vtx2Scc.at(&dst);
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});
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}
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// The given vertex is known to have become acyclic after some edits,
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// propagate through graph to mark connected vertices as well.
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void updateAcyclic(const DfgVertex& vtx) {
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// Mark as acyclic
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uint64_t& sccIdxr = m_vtx2Scc.at(&vtx);
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UASSERT_OBJ(sccIdxr, &vtx, "Vertex should be cyclic");
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sccIdxr = 0;
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--m_nCyclicVertices;
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// Propagate the update through the graph forward
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vtx.foreachSink([&](const DfgVertex& dst) {
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// Sink was known to be acyclic, stop
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if (!m_vtx2Scc.at(&dst)) return false;
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if (!stillCyclicFwd(dst)) updateAcyclic(dst);
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return false;
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});
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// Propagate the update through the graph backward
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vtx.foreachSource([&](const DfgVertex& src) {
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// Source was known to be acyclic, stop
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if (!m_vtx2Scc.at(&src)) return false;
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if (!stillCyclicBwd(src)) updateAcyclic(src);
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return false;
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});
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}
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/*
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Check stored information is consistent with actual SCCs. Note we
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can't detect during updates if an SCC has split into multiple SCCs.
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Consider:
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A -- E -- G
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/ \ / \
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B C H I
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\ / \ /
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D -- F -- J
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If we fixed up E, the original SCC would split into two, (A,B,C,D)
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and (G,H,I,J), but also F would no longer be cyclic. For this reason,
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we can only assert that anything that we think is not cyclic based
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on the SccInfo must indeed be not cyclic, but might still think a
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vertex is cyclic based on the SccInfo but it actually isn't.
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*/
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void validate() const {
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// Re-compute the actual SCCs
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DfgUserMap<uint64_t> actual = m_dfg.makeUserMap<uint64_t>();
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V3DfgPasses::colorStronglyConnectedComponents(m_dfg, actual);
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// Assert that if we think a vertex is not cyclic, it indeed is not
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m_dfg.forEachVertex([&](const DfgVertex& vtx) {
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// 'think not cyclic' implies 'actually not cyclic'
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UASSERT_OBJ(m_vtx2Scc.at(&vtx) || !actual.at(vtx), &vtx, "Inconsisten SccInfo");
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});
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}
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};
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2025-09-02 23:21:24 +02:00
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2025-07-10 19:46:45 +02:00
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class TraceDriver final : public DfgVisitor {
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// TYPES
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2025-12-08 19:43:21 +01:00
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// Key for caching the result of a trace
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struct CacheKey final {
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2025-07-10 19:46:45 +02:00
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DfgVertex* m_vtxp;
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uint32_t m_lsb;
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uint32_t m_msb;
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2025-12-08 19:43:21 +01:00
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CacheKey() = delete;
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CacheKey(DfgVertex* vtxp, uint32_t lsb, uint32_t msb)
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: m_vtxp{vtxp}
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, m_lsb{lsb}
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, m_msb{msb} {}
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struct Hash final {
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2025-12-08 19:43:21 +01:00
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size_t operator()(const CacheKey& item) const {
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2025-08-20 19:21:24 +02:00
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// cppcheck-suppress unreadVariable
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V3Hash hash{item.m_vtxp};
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2025-07-10 19:46:45 +02:00
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hash += item.m_lsb;
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hash += item.m_msb;
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return hash.value();
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}
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};
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struct Equal final {
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2025-12-08 19:43:21 +01:00
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bool operator()(const CacheKey& a, const CacheKey& b) const {
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2025-08-05 15:47:51 +02:00
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return a.m_vtxp == b.m_vtxp && a.m_lsb == b.m_lsb && a.m_msb == b.m_msb;
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2025-07-10 19:46:45 +02:00
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}
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};
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};
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// STATE
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DfgGraph& m_dfg; // The graph being processed
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2026-06-19 23:28:50 +02:00
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SccInfo& m_sccInfo; // The SccInfo instance
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2025-12-08 19:43:21 +01:00
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// The strongly connected component we are currently trying to escape
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uint64_t m_component = 0;
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2025-07-10 19:46:45 +02:00
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uint32_t m_lsb = 0; // LSB to extract from the currently visited Vertex
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uint32_t m_msb = 0; // MSB to extract from the currently visited Vertex
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2026-07-05 12:40:08 +02:00
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std::vector<uint32_t> m_idxs; // Indices to extract from the currently visited Vertex
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2025-07-10 19:46:45 +02:00
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// Result of tracing the currently visited Vertex. Use SET_RESULT below!
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DfgVertex* m_resp = nullptr;
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2025-12-08 19:43:21 +01:00
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DfgVertex* m_defaultp = nullptr; // When tracing a variable, this is its 'defaultp', if any
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// Result cache for reusing already traced vertices
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std::unordered_map<CacheKey, DfgVertex*, CacheKey::Hash, CacheKey::Equal> m_cache;
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2025-07-10 19:46:45 +02:00
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2025-08-10 19:14:02 +02:00
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#ifdef VL_DEBUG
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2025-07-11 20:19:09 +02:00
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std::ofstream m_lineCoverageFile; // Line coverage file, just for testing
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2025-08-10 19:14:02 +02:00
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#endif
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2025-07-11 20:19:09 +02:00
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2025-07-10 19:46:45 +02:00
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// METHODS
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2025-12-08 19:43:21 +01:00
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// Create and return a new Vertex. Always use this to create new vertices.
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// Fileline is taken from 'refp', but 'refp' is otherwise not used.
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2026-06-19 23:28:50 +02:00
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// Also adds the vertex to m_sccInfo with scc index 0, indicating the new
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// vertex is not part of a strongly connected component. This should always
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// be true, as all the vertices we create here are driven from outside the
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// component we are trying to escape, and will sink into that component.
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// Given those are separate SCCs, these new vertices must be acyclic.
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template <typename Vertex>
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Vertex* make(const DfgVertex* refp, uint32_t width) {
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2025-07-10 19:46:45 +02:00
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static_assert(std::is_base_of<DfgVertex, Vertex>::value //
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2025-07-11 20:19:09 +02:00
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&& !std::is_base_of<DfgVertexVar, Vertex>::value,
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"Should only make operation vertices and constants");
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if VL_CONSTEXPR_CXX17 (std::is_same<DfgConst, Vertex>::value) {
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2025-09-02 17:50:40 +02:00
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DfgConst* const vtxp = new DfgConst{m_dfg, refp->fileline(), width, 0};
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2026-06-19 23:28:50 +02:00
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m_sccInfo.add(*vtxp, 0);
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2025-07-11 20:19:09 +02:00
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return reinterpret_cast<Vertex*>(vtxp);
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} else {
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// TODO: this is a gross hack around lack of C++17 'if constexpr' Vtx is always Vertex
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// when this code is actually executed, but needs a fudged type to type check when
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// Vertex is DfgConst, in which case this code is unreachable ...
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using Vtx = typename std::conditional<std::is_same<DfgConst, Vertex>::value, DfgSel,
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Vertex>::type;
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2025-09-07 21:38:50 +02:00
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Vtx* const vtxp = new Vtx{m_dfg, refp->fileline(), DfgDataType::packed(width)};
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2026-06-19 23:28:50 +02:00
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m_sccInfo.add(*vtxp, 0);
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2025-07-11 20:19:09 +02:00
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return reinterpret_cast<Vertex*>(vtxp);
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}
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2025-07-10 19:46:45 +02:00
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}
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2025-09-04 16:02:33 +02:00
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// Create temporary capable of holding the result of 'vtxp'
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DfgVertexVar* createTmp(const char* prefix, DfgVertex* vtxp) {
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2026-04-09 14:31:12 +02:00
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AstNode* nodep = v3Global.rootp();
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2025-09-04 16:02:33 +02:00
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const std::string name = m_dfg.makeUniqueName(prefix, nodep->user2Inc());
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FileLine* const flp = vtxp->fileline();
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DfgVertex::ScopeCache scopeCache;
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2026-04-09 14:31:12 +02:00
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AstScope* const scopep = vtxp->scopep(scopeCache);
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2025-09-07 21:38:50 +02:00
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DfgVertexVar* const varp = m_dfg.makeNewVar(flp, name, vtxp->dtype(), scopep);
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2026-04-09 14:31:12 +02:00
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varp->vscp()->varp()->isInternal(true);
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varp->tmpForp(varp->vscp());
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2026-06-19 23:28:50 +02:00
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m_sccInfo.add(*varp, 0);
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2025-09-04 16:02:33 +02:00
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return varp;
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}
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2026-07-05 12:40:08 +02:00
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// Trace drivers of the given packed vertex, at the given bit range.
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2025-07-10 19:46:45 +02:00
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DfgVertex* trace(DfgVertex* const vtxp, const uint32_t msb, const uint32_t lsb) {
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2025-09-07 21:38:50 +02:00
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UASSERT_OBJ(vtxp->isPacked(), vtxp, "Can only trace packed type vertices");
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UASSERT_OBJ(vtxp->size() > msb, vtxp, "Traced Vertex too narrow");
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2025-07-10 19:46:45 +02:00
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2025-12-08 19:43:21 +01:00
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// Get the cache entry, which is the resulting driver that is not part of
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// the same component as vtxp
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DfgVertex*& respr = m_cache
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.emplace(std::piecewise_construct, //
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std::forward_as_tuple(vtxp, msb, lsb), //
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std::forward_as_tuple(nullptr))
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.first->second;
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2025-07-10 19:46:45 +02:00
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2025-10-25 16:07:22 +02:00
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|
|
// Trace the vertex
|
2025-12-08 19:43:21 +01:00
|
|
|
if (respr) {
|
2025-10-25 16:07:22 +02:00
|
|
|
// If already traced this vtxp/msb/lsb, just use the result.
|
|
|
|
|
// This is important to avoid combinatorial explosion when the
|
|
|
|
|
// same sub-expression is needed multiple times.
|
2026-06-19 23:28:50 +02:00
|
|
|
} else if (m_sccInfo.get(*vtxp) != m_component) {
|
2025-10-25 16:07:22 +02:00
|
|
|
// If the currently traced vertex is in a different component,
|
|
|
|
|
// then we found what we were looking for.
|
2025-12-08 19:43:21 +01:00
|
|
|
respr = vtxp;
|
2025-09-04 16:02:33 +02:00
|
|
|
// If the result is a splice, we need to insert a temporary for it
|
|
|
|
|
// as a splice cannot be fed into arbitray logic
|
2025-12-08 19:43:21 +01:00
|
|
|
if (DfgVertexSplice* const splicep = respr->cast<DfgVertexSplice>()) {
|
2025-09-04 16:02:33 +02:00
|
|
|
DfgVertexVar* const tmpp = createTmp("TraceDriver", splicep);
|
2025-10-09 10:25:39 +02:00
|
|
|
// Note: we can't do 'splicep->replaceWith(tmpp)', as other
|
|
|
|
|
// variable sinks of the splice might have a defaultp driver.
|
2025-09-04 16:02:33 +02:00
|
|
|
tmpp->srcp(splicep);
|
2025-12-08 19:43:21 +01:00
|
|
|
respr = tmpp;
|
2025-09-04 16:02:33 +02:00
|
|
|
}
|
|
|
|
|
// Apply a Sel to extract the relevant bits if only a part is needed
|
2025-12-08 19:43:21 +01:00
|
|
|
if (msb != respr->width() - 1 || lsb != 0) {
|
|
|
|
|
DfgSel* const selp = make<DfgSel>(respr, msb - lsb + 1);
|
|
|
|
|
selp->fromp(respr);
|
2025-07-10 19:46:45 +02:00
|
|
|
selp->lsb(lsb);
|
2025-12-08 19:43:21 +01:00
|
|
|
respr = selp;
|
2025-07-10 19:46:45 +02:00
|
|
|
}
|
|
|
|
|
} else {
|
2025-12-08 19:43:21 +01:00
|
|
|
// Otherwise visit the vertex to trace it
|
2025-07-10 19:46:45 +02:00
|
|
|
VL_RESTORER(m_msb);
|
|
|
|
|
VL_RESTORER(m_lsb);
|
2026-07-05 12:40:08 +02:00
|
|
|
VL_RESTORER_CLEAR(m_idxs);
|
2025-09-19 14:31:07 +02:00
|
|
|
VL_RESTORER(m_resp);
|
2025-07-10 19:46:45 +02:00
|
|
|
m_msb = msb;
|
|
|
|
|
m_lsb = lsb;
|
|
|
|
|
m_resp = nullptr;
|
|
|
|
|
iterate(vtxp);
|
2025-12-08 19:43:21 +01:00
|
|
|
respr = m_resp;
|
2025-07-10 19:46:45 +02:00
|
|
|
}
|
2025-12-08 19:43:21 +01:00
|
|
|
// We only ever trace drivers of bits that are known to be independent
|
|
|
|
|
// of the cycles, so we should always be able to find an acyclic driver.
|
|
|
|
|
UASSERT_OBJ(respr, vtxp, "Tracing driver failed for " << vtxp->typeName());
|
|
|
|
|
UASSERT_OBJ(respr->width() == (msb - lsb + 1), vtxp, "Wrong result width");
|
|
|
|
|
return respr;
|
2025-07-10 19:46:45 +02:00
|
|
|
}
|
|
|
|
|
|
2026-07-05 12:40:08 +02:00
|
|
|
// Trace drivers of the given array vertex, at the current m_idxs, m_msb, m_lsb.
|
|
|
|
|
DfgVertex* traceSameIdx(DfgVertex* const vtxp) {
|
|
|
|
|
UASSERT_OBJ(vtxp->isArray(), vtxp, "Should be an array vertex");
|
|
|
|
|
UASSERT_OBJ(!m_idxs.empty(), vtxp, "Should have a pending index");
|
|
|
|
|
VL_RESTORER(m_resp);
|
|
|
|
|
m_resp = nullptr;
|
|
|
|
|
iterate(vtxp); // Resolve the element, the array visitors set 'm_resp'
|
|
|
|
|
UASSERT_OBJ(m_resp, vtxp, "Tracing driver failed for " << vtxp->typeName());
|
|
|
|
|
UASSERT_OBJ(m_resp->width() == (m_msb - m_lsb + 1), vtxp, "Wrong result width");
|
|
|
|
|
return m_resp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Trace drivers of the given array vertex, pushing the given index, at current m_msb, m_lsb.
|
|
|
|
|
DfgVertex* tracePushIdx(DfgVertex* const vtxp, const uint32_t idx) {
|
|
|
|
|
const size_t nIdxs = m_idxs.size();
|
|
|
|
|
m_idxs.push_back(idx);
|
|
|
|
|
DfgVertex* const resp = traceSameIdx(vtxp);
|
|
|
|
|
m_idxs.pop_back();
|
|
|
|
|
UASSERT_OBJ(m_idxs.size() == nIdxs, vtxp, "Index stack size mismatch");
|
|
|
|
|
return resp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Trace drivers of the given vertex, popping the innermost index, at current m_msb, m_lsb.
|
|
|
|
|
DfgVertex* tracePopIdx(DfgVertex* const vtxp) {
|
|
|
|
|
UASSERT_OBJ(!m_idxs.empty(), vtxp, "Should have a pending index");
|
|
|
|
|
const size_t nIdxs = m_idxs.size();
|
|
|
|
|
const uint32_t idx = m_idxs.back();
|
|
|
|
|
m_idxs.pop_back();
|
|
|
|
|
DfgVertex* const resp = m_idxs.empty() ? trace(vtxp, m_msb, m_lsb) : traceSameIdx(vtxp);
|
|
|
|
|
m_idxs.push_back(idx);
|
|
|
|
|
UASSERT_OBJ(m_idxs.size() == nIdxs, vtxp, "Index stack size mismatch");
|
|
|
|
|
return resp;
|
|
|
|
|
}
|
|
|
|
|
|
2025-07-11 20:19:09 +02:00
|
|
|
template <typename Vertex>
|
2025-08-15 09:20:36 +02:00
|
|
|
Vertex* traceBitwiseBinary(Vertex* vtxp) {
|
2025-07-11 20:19:09 +02:00
|
|
|
static_assert(std::is_base_of<DfgVertexBinary, Vertex>::value,
|
|
|
|
|
"Should only call on DfgVertexBinary");
|
2025-12-08 19:43:21 +01:00
|
|
|
Vertex* const resp = make<Vertex>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->rhsp(trace(vtxp->rhsp(), m_msb, m_lsb));
|
|
|
|
|
resp->lhsp(trace(vtxp->lhsp(), m_msb, m_lsb));
|
|
|
|
|
return resp;
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
2025-08-15 09:20:36 +02:00
|
|
|
template <typename Vertex>
|
|
|
|
|
DfgVertex* traceAddSub(Vertex* vtxp) {
|
|
|
|
|
static_assert(std::is_base_of<DfgVertexBinary, Vertex>::value,
|
|
|
|
|
"Should only call on DfgVertexBinary");
|
2025-12-08 19:43:21 +01:00
|
|
|
Vertex* const opp = make<Vertex>(vtxp, m_msb + 1);
|
|
|
|
|
opp->rhsp(trace(vtxp->rhsp(), m_msb, 0));
|
|
|
|
|
opp->lhsp(trace(vtxp->lhsp(), m_msb, 0));
|
|
|
|
|
DfgSel* const selp = make<DfgSel>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
selp->fromp(opp);
|
|
|
|
|
selp->lsb(m_lsb);
|
|
|
|
|
return selp;
|
2025-08-15 09:20:36 +02:00
|
|
|
}
|
|
|
|
|
|
2025-11-29 20:01:22 +01:00
|
|
|
template <typename Vertex>
|
|
|
|
|
Vertex* traceReduction(Vertex* vtxp) {
|
|
|
|
|
static_assert(std::is_base_of<DfgVertexUnary, Vertex>::value,
|
|
|
|
|
"Should only call on DfgVertexUnary");
|
2025-12-08 19:43:21 +01:00
|
|
|
Vertex* const resp = make<Vertex>(vtxp, 1);
|
|
|
|
|
resp->srcp(trace(vtxp->srcp(), vtxp->srcp()->width() - 1, 0));
|
|
|
|
|
return resp;
|
2025-11-29 20:01:22 +01:00
|
|
|
}
|
|
|
|
|
|
2025-08-15 09:20:36 +02:00
|
|
|
template <typename Vertex>
|
|
|
|
|
Vertex* traceCmp(Vertex* vtxp) {
|
|
|
|
|
static_assert(std::is_base_of<DfgVertexBinary, Vertex>::value,
|
|
|
|
|
"Should only call on DfgVertexBinary");
|
2025-12-08 19:43:21 +01:00
|
|
|
Vertex* const resp = make<Vertex>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->rhsp(trace(vtxp->rhsp(), vtxp->rhsp()->width() - 1, 0));
|
|
|
|
|
resp->lhsp(trace(vtxp->lhsp(), vtxp->lhsp()->width() - 1, 0));
|
|
|
|
|
return resp;
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
2025-07-10 19:46:45 +02:00
|
|
|
// Use this macro to set the result in 'visit' methods. This also emits
|
|
|
|
|
// a line to m_lineCoverageFile for testing.
|
|
|
|
|
// TODO: Use C++20 std::source_location instead of a macro
|
2025-08-10 19:14:02 +02:00
|
|
|
#ifdef VL_DEBUG
|
2025-07-10 19:46:45 +02:00
|
|
|
#define SET_RESULT(vtxp) \
|
|
|
|
|
do { \
|
|
|
|
|
m_resp = vtxp; \
|
|
|
|
|
if (VL_UNLIKELY(m_lineCoverageFile.is_open())) m_lineCoverageFile << __LINE__ << '\n'; \
|
|
|
|
|
} while (false)
|
2025-08-10 19:14:02 +02:00
|
|
|
#else
|
|
|
|
|
#define SET_RESULT(vtxp) m_resp = vtxp;
|
|
|
|
|
#endif
|
2025-07-10 19:46:45 +02:00
|
|
|
|
|
|
|
|
// VISITORS
|
2025-11-29 20:01:22 +01:00
|
|
|
void visit(DfgVertex* vtxp) override { // LCOV_EXCL_START
|
2025-12-08 19:43:21 +01:00
|
|
|
vtxp->v3fatalSrc("TraceDriver - Unhandled vertex type: " << vtxp->typeName());
|
2025-11-29 20:01:22 +01:00
|
|
|
} // LCOV_EXCL_STOP
|
2025-07-10 19:46:45 +02:00
|
|
|
|
2025-07-14 23:09:34 +02:00
|
|
|
void visit(DfgSplicePacked* vtxp) override {
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
struct Driver final {
|
|
|
|
|
DfgVertex* m_vtxp;
|
|
|
|
|
uint32_t m_lsb; // LSB of driven range (internal, not Verilog)
|
|
|
|
|
uint32_t m_msb; // MSB of driven range (internal, not Verilog)
|
|
|
|
|
Driver() = delete;
|
|
|
|
|
Driver(DfgVertex* vtxp, uint32_t lsb, uint32_t msb)
|
|
|
|
|
: m_vtxp{vtxp}
|
|
|
|
|
, m_lsb{lsb}
|
|
|
|
|
, m_msb{msb} {}
|
|
|
|
|
};
|
|
|
|
|
std::vector<Driver> drivers;
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
// Look at all the drivers, one might cover the whole range, but also gather all drivers
|
2025-09-02 17:50:40 +02:00
|
|
|
bool tryWholeDefault = m_defaultp;
|
|
|
|
|
const bool done = vtxp->foreachDriver([&](DfgVertex& src, uint32_t lsb) {
|
|
|
|
|
const uint32_t msb = lsb + src.width() - 1;
|
|
|
|
|
drivers.emplace_back(&src, lsb, msb);
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
// Check if this driver covers any of the bits, then we can't use whole default
|
|
|
|
|
if (m_msb >= lsb && msb >= m_lsb) tryWholeDefault = false;
|
|
|
|
|
// If it does not cover the whole searched bit range, move on
|
2025-09-02 17:50:40 +02:00
|
|
|
if (m_lsb < lsb || msb < m_msb) return false;
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
// Driver covers whole search range, trace that and we are done
|
2025-09-02 17:50:40 +02:00
|
|
|
SET_RESULT(trace(&src, m_msb - lsb, m_lsb - lsb));
|
|
|
|
|
return true;
|
|
|
|
|
});
|
|
|
|
|
if (done) return;
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
|
|
|
|
|
// Trace the default driver if no other drivers cover the searched range
|
2025-09-02 17:50:40 +02:00
|
|
|
if (tryWholeDefault) {
|
|
|
|
|
SET_RESULT(trace(m_defaultp, m_msb, m_lsb));
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Hard case: We need to combine multiple drivers to produce the searched bit range
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
// Sort drivers (they are non-overlapping)
|
|
|
|
|
std::sort(drivers.begin(), drivers.end(), [](const Driver& a, const Driver& b) { //
|
|
|
|
|
return a.m_lsb < b.m_lsb;
|
|
|
|
|
});
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
|
|
|
|
|
// Gather terms
|
|
|
|
|
std::vector<DfgVertex*> termps;
|
2026-07-05 12:40:08 +02:00
|
|
|
uint32_t lsb = m_lsb;
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
for (const Driver& driver : drivers) {
|
|
|
|
|
// Driver is below the searched LSB, move on
|
2026-07-05 12:40:08 +02:00
|
|
|
if (lsb > driver.m_msb) continue;
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
// Driver is above the searched MSB, done
|
|
|
|
|
if (driver.m_lsb > m_msb) break;
|
|
|
|
|
// Gap below this driver, trace default to fill it
|
2026-07-05 12:40:08 +02:00
|
|
|
if (driver.m_lsb > lsb) {
|
2025-12-08 19:43:21 +01:00
|
|
|
UASSERT_OBJ(m_defaultp, vtxp, "Should have a default driver if needs tracing");
|
2026-07-05 12:40:08 +02:00
|
|
|
termps.emplace_back(trace(m_defaultp, driver.m_lsb - 1, lsb));
|
|
|
|
|
lsb = driver.m_lsb;
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
}
|
|
|
|
|
// Driver covers searched range, pick the needed/available bits
|
2026-03-28 04:14:18 +01:00
|
|
|
const uint32_t lim = std::min(m_msb, driver.m_msb);
|
2026-07-05 12:40:08 +02:00
|
|
|
termps.emplace_back(trace(driver.m_vtxp, lim - driver.m_lsb, lsb - driver.m_lsb));
|
|
|
|
|
lsb = lim + 1;
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
}
|
2026-07-05 12:40:08 +02:00
|
|
|
if (m_msb >= lsb) {
|
2025-12-08 19:43:21 +01:00
|
|
|
UASSERT_OBJ(m_defaultp, vtxp, "Should have a default driver if needs tracing");
|
2026-07-05 12:40:08 +02:00
|
|
|
termps.emplace_back(trace(m_defaultp, m_msb, lsb));
|
Optimize complex combinational logic in DFG (#6298)
This patch adds DfgLogic, which is a vertex that represents a whole,
arbitrarily complex combinational AstAlways or AstAssignW in the
DfgGraph.
Implementing this requires computing the variables live at entry to the
AstAlways (variables read by the block), so there is a new
ControlFlowGraph data structure and a classical data-flow analysis based
live variable analysis to do that at the variable level (as opposed to
bit/element level).
The actual CFG construction and live variable analysis is best effort,
and might fail for currently unhandled constructs or data types. This
can be extended later.
V3DfgAstToDfg is changed to convert the Ast into an initial DfgGraph
containing only DfgLogic, DfgVertexSplice and DfgVertexVar vertices.
The DfgLogic are then subsequently synthesized into primitive operations
by the new V3DfgSynthesize pass, which is a combination of the old
V3DfgAstToDfg conversion and new code to handle AstAlways blocks with
complex flow control.
V3DfgSynthesize by default will synthesize roughly the same constructs
as V3DfgAstToDfg used to handle before, plus any logic that is part of a
combinational cycle within the DfgGraph. This enables breaking up these
cycles, for which there are extensions to V3DfgBreakCycles in this patch
as well. V3DfgSynthesize will then delete all non synthesized or non
synthesizable DfgLogic vertices and the rest of the Dfg pipeline is
identical, with minor changes to adjust for the changed representation.
Because with this change we can now eliminate many more UNOPTFLAT, DFG
has been disabled in all the tests that specifically target testing the
scheduling and reporting of circular combinational logic.
2025-08-19 16:06:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// The earlier cheks cover the case when either a whole driver or the default covers
|
|
|
|
|
// the whole range, so there should be at least 2 terms required here.
|
|
|
|
|
UASSERT_OBJ(termps.size() >= 2, vtxp, "Should have returned in special cases");
|
|
|
|
|
|
|
|
|
|
// Concatenate all terms and set result
|
|
|
|
|
DfgVertex* resp = termps.front();
|
|
|
|
|
for (size_t i = 1; i < termps.size(); ++i) {
|
|
|
|
|
DfgVertex* const termp = termps[i];
|
|
|
|
|
DfgConcat* const catp = make<DfgConcat>(termp, resp->width() + termp->width());
|
|
|
|
|
catp->rhsp(resp);
|
|
|
|
|
catp->lhsp(termp);
|
|
|
|
|
resp = catp;
|
|
|
|
|
}
|
|
|
|
|
SET_RESULT(resp);
|
2025-07-10 19:46:45 +02:00
|
|
|
}
|
|
|
|
|
|
2026-07-05 12:40:08 +02:00
|
|
|
void visit(DfgSpliceArray* vtxp) override {
|
|
|
|
|
// Explicit per-element driver (a UnitArray wrapping the element value)
|
|
|
|
|
if (DfgVertex* const driverp = vtxp->driverAt(m_idxs.back())) {
|
|
|
|
|
// Consume this index, then trace the element value
|
|
|
|
|
SET_RESULT(tracePopIdx(driverp->as<DfgUnitArray>()->srcp()));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// TODO: this is unreachable, as syntheis can't create it today.
|
|
|
|
|
// // Element not driven explicitly, so it comes from the default array. Keep the
|
|
|
|
|
// // index pending (the default is the whole array, indexed the same way) and
|
|
|
|
|
// // continue tracing it.
|
|
|
|
|
// UASSERT_OBJ(m_defaultp, vtxp, "Independent array element should have a driver or
|
|
|
|
|
// default"); SET RESULT(traceSameIdx(m_defaultp));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgVertexVar* vtxp) override {
|
|
|
|
|
UASSERT_OBJ(!vtxp->isVolatile(), vtxp, "Should not trace through volatile variable");
|
2025-09-02 17:50:40 +02:00
|
|
|
VL_RESTORER(m_defaultp);
|
|
|
|
|
m_defaultp = vtxp->defaultp();
|
2026-07-05 12:40:08 +02:00
|
|
|
DfgVertex* const drvp = vtxp->srcp() ? vtxp->srcp() : m_defaultp;
|
|
|
|
|
UASSERT_OBJ(drvp, vtxp, "Should not have to trace undriven variable");
|
|
|
|
|
// Packed variable: trace the driver. Array variable: continue navigating it at
|
|
|
|
|
// the pending element (both at the same bit range).
|
|
|
|
|
SET_RESULT(m_idxs.empty() ? trace(drvp, m_msb, m_lsb) : traceSameIdx(drvp));
|
2025-07-14 23:09:34 +02:00
|
|
|
}
|
|
|
|
|
|
2025-07-22 09:23:45 +02:00
|
|
|
void visit(DfgArraySel* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
// If constant index, push it and trace the selected element through the array
|
|
|
|
|
// structure of 'fromp'. This handles arbitrarily nested (multi-dimensional)
|
|
|
|
|
// arrays, as each nested ArraySel pushes a further index.
|
|
|
|
|
if (const DfgConst* const idxp = vtxp->bitp()->cast<DfgConst>()) {
|
|
|
|
|
SET_RESULT(tracePushIdx(vtxp->fromp(), idxp->toU32()));
|
2026-06-19 20:46:13 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2026-07-05 12:40:08 +02:00
|
|
|
// If index is not constant, independence was proven only if the 'fromp' is
|
|
|
|
|
// independent, so no need to trace that, just reference it with the traced
|
|
|
|
|
// index. This only happens at the packed ArraySel leaf.
|
|
|
|
|
UASSERT_OBJ(m_idxs.empty(), vtxp, "Non-constant index below an outer array index");
|
|
|
|
|
DfgArraySel* const resp = make<DfgArraySel>(vtxp, vtxp->width());
|
|
|
|
|
resp->fromp(vtxp->fromp());
|
|
|
|
|
resp->bitp(trace(vtxp->bitp(), vtxp->bitp()->width() - 1, 0));
|
|
|
|
|
DfgSel* const selp = make<DfgSel>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
selp->fromp(resp);
|
|
|
|
|
selp->lsb(m_lsb);
|
|
|
|
|
SET_RESULT(selp);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgUnitArray* vtxp) override {
|
|
|
|
|
// Single-element array adapter, the pending index must be 0, unwrap the element
|
|
|
|
|
UASSERT_OBJ(m_idxs.back() == 0, vtxp, "UnitArray element index should be 0");
|
|
|
|
|
SET_RESULT(tracePopIdx(vtxp->srcp()));
|
2025-07-22 09:23:45 +02:00
|
|
|
}
|
|
|
|
|
|
2025-07-10 19:46:45 +02:00
|
|
|
void visit(DfgConcat* vtxp) override {
|
|
|
|
|
DfgVertex* const rhsp = vtxp->rhsp();
|
|
|
|
|
DfgVertex* const lhsp = vtxp->lhsp();
|
|
|
|
|
const uint32_t rWidth = rhsp->width();
|
|
|
|
|
// If the traced bits are wholly in the RHS
|
|
|
|
|
if (rWidth > m_msb) {
|
|
|
|
|
SET_RESULT(trace(rhsp, m_msb, m_lsb));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// If the traced bits are wholly in the LHS
|
|
|
|
|
if (m_lsb >= rWidth) {
|
|
|
|
|
SET_RESULT(trace(lhsp, m_msb - rWidth, m_lsb - rWidth));
|
|
|
|
|
return;
|
|
|
|
|
}
|
2025-12-08 19:43:21 +01:00
|
|
|
// The traced bit spans both sides, trace both
|
|
|
|
|
DfgConcat* const resp = make<DfgConcat>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->rhsp(trace(rhsp, rWidth - 1, m_lsb));
|
|
|
|
|
resp->lhsp(trace(lhsp, m_msb - rWidth, 0));
|
|
|
|
|
SET_RESULT(resp);
|
|
|
|
|
}
|
|
|
|
|
|
2026-04-23 11:14:27 +02:00
|
|
|
void visit(DfgRep* vtxp) override {
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgVertex* const srcp = vtxp->srcp();
|
|
|
|
|
const uint32_t sWidth = srcp->width();
|
|
|
|
|
// If we need more bits than the source, then we need the whole source
|
|
|
|
|
if (m_msb - m_lsb + 1 > sWidth) {
|
2026-04-23 11:14:27 +02:00
|
|
|
DfgRep* const repp = make<DfgRep>(vtxp, vtxp->width());
|
2025-12-08 19:43:21 +01:00
|
|
|
repp->srcp(trace(srcp, sWidth - 1, 0));
|
|
|
|
|
DfgSel* const resp = make<DfgSel>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->fromp(repp);
|
|
|
|
|
resp->lsb(m_lsb);
|
|
|
|
|
SET_RESULT(resp);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// If the requested bits are within the same repliacted word
|
|
|
|
|
if (m_msb / sWidth == m_lsb / sWidth) {
|
|
|
|
|
SET_RESULT(trace(srcp, m_msb % sWidth, m_lsb % sWidth));
|
|
|
|
|
return;
|
2025-07-10 19:46:45 +02:00
|
|
|
}
|
2025-12-08 19:43:21 +01:00
|
|
|
// The requested bits span two replicated words
|
|
|
|
|
DfgConcat* const resp = make<DfgConcat>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->rhsp(trace(srcp, sWidth - 1, m_lsb % sWidth));
|
|
|
|
|
resp->lhsp(trace(srcp, m_msb % sWidth, 0));
|
|
|
|
|
SET_RESULT(resp);
|
2025-07-10 19:46:45 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgExtend* vtxp) override {
|
|
|
|
|
DfgVertex* const srcp = vtxp->srcp();
|
2025-07-11 20:19:09 +02:00
|
|
|
const uint32_t sWidth = srcp->width();
|
|
|
|
|
// If the traced bits are wholly in the input
|
|
|
|
|
if (sWidth > m_msb) {
|
2025-07-10 19:46:45 +02:00
|
|
|
SET_RESULT(trace(srcp, m_msb, m_lsb));
|
|
|
|
|
return;
|
|
|
|
|
}
|
2025-07-11 20:19:09 +02:00
|
|
|
// If the traced bits are wholly in the extension
|
|
|
|
|
if (m_lsb >= sWidth) {
|
|
|
|
|
SET_RESULT(make<DfgConst>(vtxp, m_msb - m_lsb + 1));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// The traced bits span both sides
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgExtend* const resp = make<DfgExtend>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->srcp(trace(srcp, sWidth - 1, m_lsb));
|
|
|
|
|
SET_RESULT(resp);
|
2025-07-10 19:46:45 +02:00
|
|
|
}
|
|
|
|
|
|
2025-11-23 20:26:51 +01:00
|
|
|
void visit(DfgExtendS* vtxp) override {
|
|
|
|
|
DfgVertex* const srcp = vtxp->srcp();
|
|
|
|
|
const uint32_t sWidth = srcp->width();
|
|
|
|
|
// If the traced bits are wholly in the input
|
|
|
|
|
if (sWidth > m_msb) {
|
|
|
|
|
SET_RESULT(trace(srcp, m_msb, m_lsb));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// If the traced bits are wholly in the extension
|
|
|
|
|
if (m_lsb >= sWidth) {
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgVertex* const sp = trace(srcp, sWidth - 1, sWidth - 1);
|
|
|
|
|
if (m_msb == m_lsb) {
|
|
|
|
|
SET_RESULT(sp);
|
|
|
|
|
} else {
|
2025-11-23 20:26:51 +01:00
|
|
|
DfgExtendS* const resp = make<DfgExtendS>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->srcp(sp);
|
|
|
|
|
SET_RESULT(resp);
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// The traced bits span both sides
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgExtendS* const resp = make<DfgExtendS>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->srcp(trace(srcp, sWidth - 1, m_lsb));
|
|
|
|
|
SET_RESULT(resp);
|
2025-11-23 20:26:51 +01:00
|
|
|
}
|
|
|
|
|
|
2025-07-10 19:46:45 +02:00
|
|
|
void visit(DfgSel* vtxp) override {
|
|
|
|
|
const uint32_t lsb = vtxp->lsb();
|
|
|
|
|
SET_RESULT(trace(vtxp->srcp(), m_msb + lsb, m_lsb + lsb));
|
|
|
|
|
}
|
|
|
|
|
|
2025-07-11 20:19:09 +02:00
|
|
|
void visit(DfgNot* vtxp) override {
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgNot* const resp = make<DfgNot>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->srcp(trace(vtxp->srcp(), m_msb, m_lsb));
|
|
|
|
|
SET_RESULT(resp);
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
void visit(DfgAnd* vtxp) override { SET_RESULT(traceBitwiseBinary(vtxp)); }
|
|
|
|
|
void visit(DfgOr* vtxp) override { SET_RESULT(traceBitwiseBinary(vtxp)); }
|
|
|
|
|
void visit(DfgXor* vtxp) override { SET_RESULT(traceBitwiseBinary(vtxp)); }
|
|
|
|
|
void visit(DfgAdd* vtxp) override { SET_RESULT(traceAddSub(vtxp)); }
|
|
|
|
|
void visit(DfgSub* vtxp) override { SET_RESULT(traceAddSub(vtxp)); }
|
|
|
|
|
void visit(DfgRedAnd* vtxp) override { SET_RESULT(traceReduction(vtxp)); }
|
|
|
|
|
void visit(DfgRedOr* vtxp) override { SET_RESULT(traceReduction(vtxp)); }
|
|
|
|
|
void visit(DfgRedXor* vtxp) override { SET_RESULT(traceReduction(vtxp)); }
|
|
|
|
|
void visit(DfgEq* vtxp) override { SET_RESULT(traceCmp(vtxp)); }
|
|
|
|
|
void visit(DfgNeq* vtxp) override { SET_RESULT(traceCmp(vtxp)); }
|
|
|
|
|
void visit(DfgLt* vtxp) override { SET_RESULT(traceCmp(vtxp)); }
|
|
|
|
|
void visit(DfgLte* vtxp) override { SET_RESULT(traceCmp(vtxp)); }
|
|
|
|
|
void visit(DfgGt* vtxp) override { SET_RESULT(traceCmp(vtxp)); }
|
|
|
|
|
void visit(DfgGte* vtxp) override { SET_RESULT(traceCmp(vtxp)); }
|
2025-07-11 20:19:09 +02:00
|
|
|
|
2026-04-19 21:28:17 +02:00
|
|
|
void visit(DfgShiftRS* vtxp) override {
|
|
|
|
|
DfgVertex* const lhsp = vtxp->lhsp();
|
|
|
|
|
if (const DfgConst* const rConstp = vtxp->rhsp()->cast<DfgConst>()) {
|
|
|
|
|
const uint32_t shiftAmnt = rConstp->toU32();
|
|
|
|
|
// Width of lower half of result
|
|
|
|
|
const uint32_t lowerWidth = shiftAmnt > vtxp->width() ? 0 : vtxp->width() - shiftAmnt;
|
|
|
|
|
// If the traced bits are wholly in the input
|
|
|
|
|
if (lowerWidth > m_msb) {
|
|
|
|
|
SET_RESULT(trace(lhsp, m_msb + shiftAmnt, m_lsb + shiftAmnt));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// If the traced bits are wholly in the extension
|
|
|
|
|
if (m_lsb >= lowerWidth) {
|
|
|
|
|
DfgExtendS* const resp = make<DfgExtendS>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->srcp(trace(lhsp, lhsp->width() - 1, lhsp->width() - 1));
|
|
|
|
|
SET_RESULT(resp);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// The traced bits span both sides
|
|
|
|
|
DfgExtendS* const resp = make<DfgExtendS>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->srcp(trace(lhsp, lowerWidth - 1 + shiftAmnt, m_lsb + shiftAmnt));
|
|
|
|
|
SET_RESULT(resp);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DfgShiftRS* const shiftrsp = make<DfgShiftRS>(vtxp, vtxp->lhsp()->width() - m_lsb);
|
|
|
|
|
shiftrsp->rhsp(trace(vtxp->rhsp(), vtxp->rhsp()->width() - 1, 0));
|
|
|
|
|
shiftrsp->lhsp(trace(vtxp->lhsp(), vtxp->lhsp()->width() - 1, m_lsb));
|
|
|
|
|
if (m_msb == vtxp->lhsp()->width() - 1) {
|
|
|
|
|
SET_RESULT(shiftrsp);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
DfgSel* const selp = make<DfgSel>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
selp->fromp(shiftrsp);
|
|
|
|
|
selp->lsb(0);
|
|
|
|
|
SET_RESULT(selp);
|
|
|
|
|
}
|
|
|
|
|
|
2025-07-11 20:19:09 +02:00
|
|
|
void visit(DfgShiftR* vtxp) override {
|
|
|
|
|
DfgVertex* const lhsp = vtxp->lhsp();
|
2025-08-20 19:21:24 +02:00
|
|
|
if (const DfgConst* const rConstp = vtxp->rhsp()->cast<DfgConst>()) {
|
2025-07-11 20:19:09 +02:00
|
|
|
const uint32_t shiftAmnt = rConstp->toU32();
|
|
|
|
|
// Width of lower half of result
|
|
|
|
|
const uint32_t lowerWidth = shiftAmnt > vtxp->width() ? 0 : vtxp->width() - shiftAmnt;
|
|
|
|
|
// If the traced bits are wholly in the input
|
|
|
|
|
if (lowerWidth > m_msb) {
|
|
|
|
|
SET_RESULT(trace(lhsp, m_msb + shiftAmnt, m_lsb + shiftAmnt));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// If the traced bits are wholly in the extension
|
|
|
|
|
if (m_lsb >= lowerWidth) {
|
|
|
|
|
SET_RESULT(make<DfgConst>(vtxp, m_msb - m_lsb + 1));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// The traced bits span both sides
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgExtend* const resp = make<DfgExtend>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->srcp(trace(lhsp, lowerWidth - 1 + shiftAmnt, m_lsb + shiftAmnt));
|
|
|
|
|
SET_RESULT(resp);
|
2025-07-11 20:19:09 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgShiftR* const shiftrp = make<DfgShiftR>(vtxp, vtxp->lhsp()->width() - m_lsb);
|
|
|
|
|
shiftrp->rhsp(trace(vtxp->rhsp(), vtxp->rhsp()->width() - 1, 0));
|
|
|
|
|
shiftrp->lhsp(trace(vtxp->lhsp(), vtxp->lhsp()->width() - 1, m_lsb));
|
|
|
|
|
if (m_msb == vtxp->lhsp()->width() - 1) {
|
|
|
|
|
SET_RESULT(shiftrp);
|
2025-07-11 20:19:09 +02:00
|
|
|
return;
|
|
|
|
|
}
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgSel* const selp = make<DfgSel>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
selp->fromp(shiftrp);
|
|
|
|
|
selp->lsb(0);
|
|
|
|
|
SET_RESULT(selp);
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgShiftL* vtxp) override {
|
|
|
|
|
DfgVertex* const lhsp = vtxp->lhsp();
|
2025-08-20 19:21:24 +02:00
|
|
|
if (const DfgConst* const rConstp = vtxp->rhsp()->cast<DfgConst>()) {
|
2025-07-11 20:19:09 +02:00
|
|
|
const uint32_t shiftAmnt = rConstp->toU32();
|
|
|
|
|
// Width of lower half of result
|
|
|
|
|
const uint32_t lowerWidth = shiftAmnt > vtxp->width() ? vtxp->width() : shiftAmnt;
|
|
|
|
|
// If the traced bits are wholly in the input
|
|
|
|
|
if (m_lsb >= lowerWidth) {
|
|
|
|
|
SET_RESULT(trace(lhsp, m_msb - shiftAmnt, m_lsb - shiftAmnt));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// If the traced bits are wholly in the extension
|
|
|
|
|
if (lowerWidth > m_msb) {
|
|
|
|
|
SET_RESULT(make<DfgConst>(vtxp, m_msb - m_lsb + 1));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
// The traced bits span both sides
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgConcat* const resp = make<DfgConcat>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->rhsp(make<DfgConst>(vtxp, resp->width() - (m_msb - lowerWidth + 1)));
|
|
|
|
|
resp->lhsp(trace(lhsp, m_msb - shiftAmnt, lowerWidth - shiftAmnt));
|
|
|
|
|
SET_RESULT(resp);
|
2025-07-11 20:19:09 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgShiftL* const shiftlp = make<DfgShiftL>(vtxp, m_msb + 1);
|
|
|
|
|
shiftlp->rhsp(trace(vtxp->rhsp(), vtxp->rhsp()->width() - 1, 0));
|
|
|
|
|
shiftlp->lhsp(trace(vtxp->lhsp(), m_msb, 0));
|
|
|
|
|
if (m_lsb == 0) {
|
|
|
|
|
SET_RESULT(shiftlp);
|
2025-07-11 20:19:09 +02:00
|
|
|
return;
|
|
|
|
|
}
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgSel* const selp = make<DfgSel>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
selp->fromp(shiftlp);
|
|
|
|
|
selp->lsb(m_lsb);
|
|
|
|
|
SET_RESULT(selp);
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
2025-08-10 19:14:02 +02:00
|
|
|
void visit(DfgCond* vtxp) override {
|
2025-12-08 19:43:21 +01:00
|
|
|
DfgCond* const resp = make<DfgCond>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
resp->condp(trace(vtxp->condp(), vtxp->condp()->width() - 1, 0));
|
|
|
|
|
resp->thenp(trace(vtxp->thenp(), m_msb, m_lsb));
|
|
|
|
|
resp->elsep(trace(vtxp->elsep(), m_msb, m_lsb));
|
|
|
|
|
SET_RESULT(resp);
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
|
|
|
|
|
2026-06-19 20:46:13 +02:00
|
|
|
void visit(DfgMatchMasked* vtxp) override {
|
|
|
|
|
DfgMatchMasked* const resp = make<DfgMatchMasked>(vtxp, vtxp->width());
|
|
|
|
|
resp->lhsp(trace(vtxp->lhsp(), vtxp->lhsp()->width() - 1, 0));
|
|
|
|
|
resp->matchp(trace(vtxp->matchp(), vtxp->matchp()->width() - 1, 0));
|
|
|
|
|
DfgSel* const selp = make<DfgSel>(vtxp, m_msb - m_lsb + 1);
|
|
|
|
|
selp->fromp(resp);
|
|
|
|
|
selp->lsb(m_lsb);
|
2026-07-05 12:40:08 +02:00
|
|
|
SET_RESULT(selp);
|
2026-06-19 20:46:13 +02:00
|
|
|
}
|
|
|
|
|
|
2025-07-10 19:46:45 +02:00
|
|
|
#undef SET_RESULT
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
public:
|
2025-07-10 19:46:45 +02:00
|
|
|
// CONSTRUCTOR
|
2026-06-19 23:28:50 +02:00
|
|
|
TraceDriver(DfgGraph& dfg, SccInfo& sccInfo)
|
2025-07-10 19:46:45 +02:00
|
|
|
: m_dfg{dfg}
|
2026-06-19 23:28:50 +02:00
|
|
|
, m_sccInfo{sccInfo} {
|
2025-08-10 19:14:02 +02:00
|
|
|
#ifdef VL_DEBUG
|
2025-07-10 19:46:45 +02:00
|
|
|
if (v3Global.opt.debugCheck()) {
|
|
|
|
|
m_lineCoverageFile.open( //
|
|
|
|
|
v3Global.opt.makeDir() + "/" + v3Global.opt.prefix()
|
|
|
|
|
+ "__V3DfgBreakCycles-TraceDriver-line-coverage.txt", //
|
|
|
|
|
std::ios_base::out | std::ios_base::app);
|
|
|
|
|
}
|
2025-08-10 19:14:02 +02:00
|
|
|
#endif
|
2025-07-10 19:46:45 +02:00
|
|
|
}
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
// Given a Vertex that is part of an SCC, return a vertex that is equivalent
|
|
|
|
|
// to 'vtxp[lsb +: width]', but is not part of the same SCC. This should only
|
|
|
|
|
// be called if the bit range is known to be independent of the SCC, so the
|
|
|
|
|
// trace can always succeed.
|
|
|
|
|
DfgVertex* apply(DfgVertex& vtx, uint32_t lsb, uint32_t width) {
|
|
|
|
|
VL_RESTORER(m_component);
|
2026-06-19 23:28:50 +02:00
|
|
|
m_component = m_sccInfo.get(vtx);
|
2025-12-08 19:43:21 +01:00
|
|
|
return trace(&vtx, lsb + width - 1, lsb);
|
2025-07-10 19:46:45 +02:00
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
2026-07-05 12:40:08 +02:00
|
|
|
// A bit mask for each bit in a value, which can be either packed or aggregate type
|
|
|
|
|
class BitMask final {
|
|
|
|
|
// TYPES
|
|
|
|
|
const DfgDataType& m_dtype;
|
|
|
|
|
union {
|
|
|
|
|
V3Number m_num; // The bits, if packed
|
|
|
|
|
std::vector<BitMask> m_sub; // The per element masks, if aggregate
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
public:
|
|
|
|
|
// CONSTRUCTOR
|
|
|
|
|
BitMask(FileLine* flp, const DfgDataType& dtype)
|
|
|
|
|
: m_dtype{dtype} {
|
|
|
|
|
UASSERT_OBJ(!m_dtype.isNull(), flp, "Expected non-null data type");
|
|
|
|
|
if (m_dtype.isPacked()) {
|
|
|
|
|
new (&m_num) V3Number{flp, static_cast<int>(m_dtype.size()), 0};
|
|
|
|
|
} else {
|
|
|
|
|
new (&m_sub) std::vector<BitMask>{};
|
|
|
|
|
m_sub.reserve(m_dtype.size());
|
|
|
|
|
for (uint32_t i = 0; i < m_dtype.size(); ++i)
|
|
|
|
|
m_sub.emplace_back(flp, m_dtype.elemDtype());
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
BitMask(const DfgVertex& vtx)
|
|
|
|
|
: BitMask{vtx.fileline(), vtx.dtype()} {}
|
|
|
|
|
BitMask(const BitMask& other)
|
|
|
|
|
: m_dtype{other.m_dtype} {
|
|
|
|
|
if (m_dtype.isPacked()) {
|
|
|
|
|
new (&m_num) V3Number{other.m_num};
|
|
|
|
|
} else {
|
|
|
|
|
new (&m_sub) std::vector<BitMask>{other.m_sub};
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
BitMask& operator=(const BitMask& other) {
|
|
|
|
|
if (this != &other) {
|
|
|
|
|
UASSERT(m_dtype == other.m_dtype, "Expected same data type");
|
|
|
|
|
if (other.m_dtype.isPacked()) {
|
|
|
|
|
m_num = other.m_num;
|
|
|
|
|
} else {
|
|
|
|
|
m_sub = other.m_sub;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return *this;
|
|
|
|
|
}
|
|
|
|
|
~BitMask() {
|
|
|
|
|
if (m_dtype.isPacked()) {
|
|
|
|
|
m_num.~V3Number();
|
|
|
|
|
} else {
|
|
|
|
|
m_sub.~vector<BitMask>();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// METHODS
|
|
|
|
|
V3Number& num() {
|
|
|
|
|
UASSERT(m_dtype.isPacked(), "Expected packed data type");
|
|
|
|
|
return m_num;
|
|
|
|
|
}
|
|
|
|
|
const V3Number& num() const {
|
|
|
|
|
UASSERT(m_dtype.isPacked(), "Expected packed data type");
|
|
|
|
|
return m_num;
|
|
|
|
|
}
|
|
|
|
|
std::vector<BitMask>& sub() {
|
|
|
|
|
UASSERT(m_dtype.isArray(), "Expected array data type");
|
|
|
|
|
return m_sub;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool isZero() const {
|
|
|
|
|
if (m_dtype.isPacked()) return m_num.isEqZero();
|
|
|
|
|
|
|
|
|
|
for (const BitMask& sub : m_sub) {
|
|
|
|
|
if (!sub.isZero()) return false;
|
|
|
|
|
}
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
bool isOnes() const {
|
|
|
|
|
if (m_dtype.isPacked()) return m_num.isEqAllOnes();
|
|
|
|
|
|
|
|
|
|
for (const BitMask& sub : m_sub) {
|
|
|
|
|
if (!sub.isOnes()) return false;
|
|
|
|
|
}
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
void setZero() {
|
|
|
|
|
if (m_dtype.isPacked()) {
|
|
|
|
|
m_num.setAllBits0();
|
|
|
|
|
} else {
|
|
|
|
|
for (BitMask& sub : m_sub) sub.setZero();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
void setOnes() {
|
|
|
|
|
if (m_dtype.isPacked()) {
|
|
|
|
|
m_num.setAllBits1();
|
|
|
|
|
} else {
|
|
|
|
|
for (BitMask& sub : m_sub) sub.setOnes();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool operator==(const BitMask& other) const {
|
|
|
|
|
UASSERT(m_dtype == other.m_dtype, "Expected same data type");
|
|
|
|
|
if (m_dtype.isPacked()) return m_num.isCaseEq(other.m_num);
|
|
|
|
|
return m_sub == other.m_sub;
|
|
|
|
|
}
|
|
|
|
|
bool operator!=(const BitMask& other) const { return !(*this == other); }
|
|
|
|
|
|
|
|
|
|
// 'this' has a clear bit where 'that' has a set bit, that is,
|
|
|
|
|
// 'this' has a proper subset of bits set compared to 'that'.
|
|
|
|
|
bool isContractionOf(const BitMask& that) const {
|
|
|
|
|
UASSERT(m_dtype == that.m_dtype, "Expected same data type");
|
|
|
|
|
if (m_dtype.isPacked()) {
|
|
|
|
|
const size_t words = VL_WORDS_I(m_dtype.size());
|
|
|
|
|
for (size_t i = 0; i < words; ++i) {
|
|
|
|
|
if (~m_num.edataWord(i) & that.m_num.edataWord(i)) return true;
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
UASSERT(m_dtype.isArray(), "Expected array data type");
|
|
|
|
|
for (size_t i = 0; i < m_sub.size(); ++i) {
|
|
|
|
|
if (m_sub[i].isContractionOf(that.m_sub[i])) return true;
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
std::string toString() const {
|
|
|
|
|
if (m_dtype.isPacked()) return "0x" + m_num.displayed(m_num.fileline(), "%x");
|
|
|
|
|
std::string result;
|
|
|
|
|
result += "{";
|
|
|
|
|
for (const BitMask& sub : m_sub) {
|
|
|
|
|
if (&sub != &m_sub.front()) result += ", ";
|
|
|
|
|
result += sub.toString();
|
|
|
|
|
}
|
|
|
|
|
result += "}";
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
2025-07-11 20:19:09 +02:00
|
|
|
class IndependentBits final : public DfgVisitor {
|
2026-04-19 20:48:02 +02:00
|
|
|
// TYPES
|
|
|
|
|
struct VertexState final {
|
|
|
|
|
size_t m_rpoNumber = 0; // Reverse Postorder Number of vertex
|
|
|
|
|
bool m_isOnWorkList = false; // Whether the vertex is on the work list
|
|
|
|
|
};
|
|
|
|
|
|
2025-07-11 20:19:09 +02:00
|
|
|
// STATE
|
2026-06-19 23:28:50 +02:00
|
|
|
const SccInfo& m_sccInfo; // The SccInfo instance
|
2025-11-29 20:01:22 +01:00
|
|
|
// Vertex to current bit mask map. The mask is set for the bits that are independent of the SCC
|
2026-07-05 12:40:08 +02:00
|
|
|
std::unordered_map<const DfgVertex*, BitMask> m_vtxp2Mask;
|
2026-04-19 20:48:02 +02:00
|
|
|
// Work list for the traversal (min-queue of vertex RPO numbers)
|
|
|
|
|
std::priority_queue<size_t, std::vector<size_t>, std::greater<size_t>> m_workQueue;
|
|
|
|
|
std::unordered_map<const DfgVertex*, VertexState> m_vtxp2State; // State of each vertex
|
2025-12-08 19:43:21 +01:00
|
|
|
|
|
|
|
|
#ifdef VL_DEBUG
|
2025-07-11 20:19:09 +02:00
|
|
|
std::ofstream m_lineCoverageFile; // Line coverage file, just for testing
|
2025-12-08 19:43:21 +01:00
|
|
|
#endif
|
2025-07-11 20:19:09 +02:00
|
|
|
|
|
|
|
|
// METHODS
|
2025-11-29 20:01:22 +01:00
|
|
|
|
2025-07-11 20:19:09 +02:00
|
|
|
// Retrieve the mask for the given vertex (create it with value 0 if needed)
|
2026-07-05 12:40:08 +02:00
|
|
|
BitMask& mask(const DfgVertex& vtx) {
|
|
|
|
|
// Look up (or create) mask for 'vtx'
|
2025-11-29 20:01:22 +01:00
|
|
|
return m_vtxp2Mask
|
|
|
|
|
.emplace(std::piecewise_construct, //
|
2026-07-05 12:40:08 +02:00
|
|
|
std::forward_as_tuple(&vtx), std::forward_as_tuple(vtx))
|
2025-11-29 20:01:22 +01:00
|
|
|
.first->second;
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Use this macro to call 'mask' in 'visit' methods. This also emits
|
|
|
|
|
// a line to m_lineCoverageFile for testing.
|
|
|
|
|
// TODO: Use C++20 std::source_location instead of a macro
|
2025-08-10 19:14:02 +02:00
|
|
|
#ifdef VL_DEBUG
|
2025-07-11 20:19:09 +02:00
|
|
|
#define MASK(vtxp) \
|
2026-07-05 12:40:08 +02:00
|
|
|
([this](const DfgVertex& vtx) -> BitMask& { \
|
2025-07-11 20:19:09 +02:00
|
|
|
if (VL_UNLIKELY(m_lineCoverageFile.is_open())) m_lineCoverageFile << __LINE__ << '\n'; \
|
2025-11-29 20:01:22 +01:00
|
|
|
return mask(vtx); \
|
|
|
|
|
}(*vtxp))
|
2025-08-10 19:14:02 +02:00
|
|
|
#else
|
2025-11-29 20:01:22 +01:00
|
|
|
#define MASK(vtxp) mask(*vtxp)
|
2025-08-10 19:14:02 +02:00
|
|
|
#endif
|
|
|
|
|
|
2025-11-29 20:01:22 +01:00
|
|
|
// Clear all bits at or below the most significant clear bit
|
2025-08-10 19:14:02 +02:00
|
|
|
void floodTowardsLsb(V3Number& num) {
|
|
|
|
|
for (int i = num.width() - 1; i >= 0; --i) {
|
2025-11-29 20:01:22 +01:00
|
|
|
if (num.bitIs1(i)) continue;
|
|
|
|
|
num.opSetRange(0, i + 1, '0');
|
|
|
|
|
break;
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2025-11-29 20:01:22 +01:00
|
|
|
// Clear all bits at or above the least significant clear bit
|
2025-08-10 19:14:02 +02:00
|
|
|
void floodTowardsMsb(V3Number& num) {
|
|
|
|
|
for (int i = 0; i < num.width(); ++i) {
|
2025-11-29 20:01:22 +01:00
|
|
|
if (num.bitIs1(i)) continue;
|
|
|
|
|
num.opSetRange(i, num.width() - i, '0');
|
|
|
|
|
break;
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
|
|
|
|
}
|
2025-07-11 20:19:09 +02:00
|
|
|
|
2026-07-05 12:40:08 +02:00
|
|
|
void propagateFromDriver(BitMask& m, const DfgVertex* srcp) {
|
2025-11-29 20:01:22 +01:00
|
|
|
// If there is no driver, we are done
|
2025-09-02 17:50:40 +02:00
|
|
|
if (!srcp) return;
|
2025-11-29 20:01:22 +01:00
|
|
|
// If it is driven by a splice, we need to combine the masks of the drivers
|
2025-12-08 19:43:21 +01:00
|
|
|
if (const DfgSplicePacked* const splicep = srcp->cast<DfgSplicePacked>()) {
|
|
|
|
|
splicep->foreachDriver([&](const DfgVertex& src, uint32_t lo) {
|
2026-07-05 12:40:08 +02:00
|
|
|
m.num().opSelInto(MASK(&src).num(), lo, src.width());
|
|
|
|
|
return false;
|
|
|
|
|
});
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (const DfgSpliceArray* const splicep = srcp->cast<DfgSpliceArray>()) {
|
|
|
|
|
splicep->foreachDriver([&](const DfgVertex& src, uint32_t lo) {
|
|
|
|
|
if (const DfgUnitArray* const uap = src.cast<DfgUnitArray>()) {
|
|
|
|
|
m.sub().at(lo) = MASK(uap->srcp());
|
|
|
|
|
} else {
|
|
|
|
|
// m.sub().at(lo) = Can't happen MASK(&src);
|
|
|
|
|
}
|
2025-09-02 17:50:40 +02:00
|
|
|
return false;
|
|
|
|
|
});
|
|
|
|
|
return;
|
|
|
|
|
}
|
2025-11-29 20:01:22 +01:00
|
|
|
// Otherwise, we just use the mask of the single driver
|
2025-09-02 17:50:40 +02:00
|
|
|
m = MASK(srcp);
|
2025-07-14 23:09:34 +02:00
|
|
|
}
|
|
|
|
|
|
2025-11-29 20:01:22 +01:00
|
|
|
// VISITORS
|
|
|
|
|
void visit(DfgVertex* vtxp) override { // LCOV_EXCL_START
|
|
|
|
|
UINFO(9, "IndependentBits - Unhandled vertex type: " << vtxp->typeName());
|
|
|
|
|
// Conservative assumption about all bits being dependent prevails
|
|
|
|
|
} // LCOV_EXCL_STOP
|
|
|
|
|
|
2026-07-05 12:40:08 +02:00
|
|
|
void visit(DfgVertexVar* vtxp) override {
|
2025-12-08 19:43:21 +01:00
|
|
|
// We cannot trace through a volatile variable, so pretend all bits are dependent
|
|
|
|
|
if (vtxp->isVolatile()) return;
|
2026-07-05 12:40:08 +02:00
|
|
|
|
|
|
|
|
BitMask& m = MASK(vtxp);
|
2025-11-29 20:01:22 +01:00
|
|
|
DfgVertex* const srcp = vtxp->srcp();
|
|
|
|
|
DfgVertex* const defaultp = vtxp->defaultp();
|
|
|
|
|
// If there is a default driver, we start from that
|
|
|
|
|
if (defaultp) m = MASK(defaultp);
|
|
|
|
|
// Then propagate mask from the driver
|
|
|
|
|
propagateFromDriver(m, srcp);
|
|
|
|
|
}
|
|
|
|
|
|
2026-07-05 12:40:08 +02:00
|
|
|
void visit(DfgVertexSplice* vtxp) override {
|
|
|
|
|
propagateFromDriver(MASK(vtxp), vtxp); // Needed to continue traversal
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgUnitArray* vtxp) override { MASK(vtxp).sub().at(0) = MASK(vtxp->srcp()); }
|
|
|
|
|
|
2025-07-22 09:23:45 +02:00
|
|
|
void visit(DfgArraySel* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
DfgVertex* const fromp = vtxp->fromp();
|
|
|
|
|
|
|
|
|
|
// If constant index, copy mask of relevant element
|
|
|
|
|
if (const DfgConst* const idxp = vtxp->bitp()->cast<DfgConst>()) {
|
|
|
|
|
MASK(vtxp) = MASK(vtxp->fromp()).sub().at(idxp->toSizeT());
|
2026-06-19 20:46:13 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2026-07-05 12:40:08 +02:00
|
|
|
// If index is not constant, independent only if the index is indenpendent, and the array
|
|
|
|
|
// is independent. TODO: could relax by '&' reducing, not sure if worth it.
|
|
|
|
|
if (MASK(vtxp->bitp()).isOnes() && MASK(fromp).isOnes()) MASK(vtxp).setOnes();
|
2025-07-22 09:23:45 +02:00
|
|
|
}
|
|
|
|
|
|
2025-07-11 20:19:09 +02:00
|
|
|
void visit(DfgConcat* vtxp) override {
|
|
|
|
|
const DfgVertex* const rhsp = vtxp->rhsp();
|
|
|
|
|
const DfgVertex* const lhsp = vtxp->lhsp();
|
2026-07-05 12:40:08 +02:00
|
|
|
V3Number& m = MASK(vtxp).num();
|
|
|
|
|
m.opSelInto(MASK(rhsp).num(), 0, rhsp->width());
|
|
|
|
|
m.opSelInto(MASK(lhsp).num(), rhsp->width(), lhsp->width());
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
2026-04-23 11:14:27 +02:00
|
|
|
void visit(DfgRep* vtxp) override {
|
|
|
|
|
const uint32_t count = vtxp->count();
|
2025-07-11 20:19:09 +02:00
|
|
|
const DfgVertex* const srcp = vtxp->srcp();
|
|
|
|
|
const uint32_t sWidth = srcp->width();
|
2026-07-05 12:40:08 +02:00
|
|
|
V3Number& vMask = MASK(vtxp).num();
|
|
|
|
|
V3Number& sMask = MASK(srcp).num();
|
2025-07-11 20:19:09 +02:00
|
|
|
for (uint32_t i = 0; i < count; ++i) vMask.opSelInto(sMask, i * sWidth, sWidth);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgSel* vtxp) override {
|
|
|
|
|
const uint32_t lsb = vtxp->lsb();
|
|
|
|
|
const uint32_t msb = lsb + vtxp->width() - 1;
|
2026-07-05 12:40:08 +02:00
|
|
|
MASK(vtxp).num().opSel(MASK(vtxp->fromp()).num(), msb, lsb);
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgExtend* vtxp) override {
|
|
|
|
|
const DfgVertex* const srcp = vtxp->srcp();
|
2025-07-21 20:57:02 +02:00
|
|
|
const uint32_t sWidth = srcp->width();
|
2026-07-05 12:40:08 +02:00
|
|
|
V3Number& s = MASK(srcp).num();
|
|
|
|
|
V3Number& m = MASK(vtxp).num();
|
2025-11-29 20:01:22 +01:00
|
|
|
m.opSelInto(s, 0, sWidth);
|
|
|
|
|
m.opSetRange(sWidth, vtxp->width() - sWidth, '1');
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
2025-11-23 20:26:51 +01:00
|
|
|
void visit(DfgExtendS* vtxp) override {
|
|
|
|
|
const DfgVertex* const srcp = vtxp->srcp();
|
|
|
|
|
const uint32_t sWidth = srcp->width();
|
2026-07-05 12:40:08 +02:00
|
|
|
V3Number& s = MASK(srcp).num();
|
|
|
|
|
V3Number& m = MASK(vtxp).num();
|
2025-11-23 20:26:51 +01:00
|
|
|
m.opSelInto(s, 0, sWidth);
|
|
|
|
|
m.opSetRange(sWidth, vtxp->width() - sWidth, s.bitIs0(sWidth - 1) ? '0' : '1');
|
|
|
|
|
}
|
|
|
|
|
|
2025-07-11 20:19:09 +02:00
|
|
|
void visit(DfgNot* vtxp) override { //
|
|
|
|
|
MASK(vtxp) = MASK(vtxp->srcp());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgAnd* vtxp) override { //
|
2026-07-05 12:40:08 +02:00
|
|
|
MASK(vtxp).num().opAnd(MASK(vtxp->lhsp()).num(), MASK(vtxp->rhsp()).num());
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
void visit(DfgOr* vtxp) override { //
|
2026-07-05 12:40:08 +02:00
|
|
|
MASK(vtxp).num().opAnd(MASK(vtxp->lhsp()).num(), MASK(vtxp->rhsp()).num());
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
void visit(DfgXor* vtxp) override { //
|
2026-07-05 12:40:08 +02:00
|
|
|
MASK(vtxp).num().opAnd(MASK(vtxp->lhsp()).num(), MASK(vtxp->rhsp()).num());
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
2025-08-10 19:14:02 +02:00
|
|
|
void visit(DfgAdd* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
V3Number& m = MASK(vtxp).num();
|
|
|
|
|
m.opAnd(MASK(vtxp->lhsp()).num(), MASK(vtxp->rhsp()).num());
|
2025-08-10 19:14:02 +02:00
|
|
|
floodTowardsMsb(m);
|
|
|
|
|
}
|
|
|
|
|
void visit(DfgSub* vtxp) override { // Same as Add: 2's complement (a - b) == (a + ~b + 1)
|
2026-07-05 12:40:08 +02:00
|
|
|
V3Number& m = MASK(vtxp).num();
|
|
|
|
|
m.opAnd(MASK(vtxp->lhsp()).num(), MASK(vtxp->rhsp()).num());
|
2025-08-10 19:14:02 +02:00
|
|
|
floodTowardsMsb(m);
|
|
|
|
|
}
|
|
|
|
|
|
2026-07-05 12:40:08 +02:00
|
|
|
void visit(DfgRedAnd* vtxp) override {
|
|
|
|
|
const bool independent = MASK(vtxp->lhsp()).isOnes();
|
|
|
|
|
if (independent) MASK(vtxp).setOnes();
|
2025-11-29 20:01:22 +01:00
|
|
|
}
|
2026-07-05 12:40:08 +02:00
|
|
|
void visit(DfgRedOr* vtxp) override {
|
|
|
|
|
const bool independent = MASK(vtxp->lhsp()).isOnes();
|
|
|
|
|
if (independent) MASK(vtxp).setOnes();
|
2025-11-29 20:01:22 +01:00
|
|
|
}
|
2026-07-05 12:40:08 +02:00
|
|
|
void visit(DfgRedXor* vtxp) override {
|
|
|
|
|
const bool independent = MASK(vtxp->lhsp()).isOnes();
|
|
|
|
|
if (independent) MASK(vtxp).setOnes();
|
2025-11-29 20:01:22 +01:00
|
|
|
}
|
|
|
|
|
|
2025-08-10 19:14:02 +02:00
|
|
|
void visit(DfgEq* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
const bool independent = MASK(vtxp->lhsp()).isOnes() && MASK(vtxp->rhsp()).isOnes();
|
|
|
|
|
if (independent) MASK(vtxp).setOnes();
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
|
|
|
|
void visit(DfgNeq* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
const bool independent = MASK(vtxp->lhsp()).isOnes() && MASK(vtxp->rhsp()).isOnes();
|
|
|
|
|
if (independent) MASK(vtxp).setOnes();
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
|
|
|
|
void visit(DfgLt* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
const bool independent = MASK(vtxp->lhsp()).isOnes() && MASK(vtxp->rhsp()).isOnes();
|
|
|
|
|
if (independent) MASK(vtxp).setOnes();
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
|
|
|
|
void visit(DfgLte* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
const bool independent = MASK(vtxp->lhsp()).isOnes() && MASK(vtxp->rhsp()).isOnes();
|
|
|
|
|
if (independent) MASK(vtxp).setOnes();
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
|
|
|
|
void visit(DfgGt* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
const bool independent = MASK(vtxp->lhsp()).isOnes() && MASK(vtxp->rhsp()).isOnes();
|
|
|
|
|
if (independent) MASK(vtxp).setOnes();
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
|
|
|
|
void visit(DfgGte* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
const bool independent = MASK(vtxp->lhsp()).isOnes() && MASK(vtxp->rhsp()).isOnes();
|
|
|
|
|
if (independent) MASK(vtxp).setOnes();
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
|
|
|
|
|
2026-04-19 21:28:17 +02:00
|
|
|
void visit(DfgShiftRS* vtxp) override {
|
2025-07-11 20:19:09 +02:00
|
|
|
DfgVertex* const rhsp = vtxp->rhsp();
|
|
|
|
|
DfgVertex* const lhsp = vtxp->lhsp();
|
|
|
|
|
const uint32_t width = vtxp->width();
|
|
|
|
|
|
|
|
|
|
// Constant shift can be computed precisely
|
|
|
|
|
if (DfgConst* const rConstp = rhsp->cast<DfgConst>()) {
|
|
|
|
|
const uint32_t shiftAmount = rConstp->toU32();
|
2026-04-19 21:28:17 +02:00
|
|
|
if (shiftAmount >= width) {
|
2026-07-05 12:40:08 +02:00
|
|
|
if (MASK(lhsp).num().bitIs1(width - 1)) { MASK(vtxp).setOnes(); }
|
2026-04-19 21:28:17 +02:00
|
|
|
} else {
|
2026-07-05 12:40:08 +02:00
|
|
|
V3Number& m = MASK(vtxp).num();
|
|
|
|
|
m.opShiftRS(MASK(lhsp).num(), rConstp->num(), width);
|
2026-04-19 21:28:17 +02:00
|
|
|
m.opSetRange(width - shiftAmount, shiftAmount, '1');
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Otherwise, as the shift amount is non-negative, all independent
|
|
|
|
|
// and consecutive top bits in the lhs yield an independent result
|
|
|
|
|
// if the shift amount is independent.
|
2026-07-05 12:40:08 +02:00
|
|
|
if (MASK(rhsp).isOnes()) {
|
|
|
|
|
V3Number& m = MASK(vtxp).num();
|
|
|
|
|
m = MASK(lhsp).num();
|
2026-04-19 21:28:17 +02:00
|
|
|
floodTowardsLsb(m);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgShiftR* vtxp) override {
|
|
|
|
|
DfgVertex* const rhsp = vtxp->rhsp();
|
|
|
|
|
DfgVertex* const lhsp = vtxp->lhsp();
|
|
|
|
|
const uint32_t width = vtxp->width();
|
|
|
|
|
|
|
|
|
|
// Constant shift can be computed precisely
|
|
|
|
|
if (DfgConst* const rConstp = rhsp->cast<DfgConst>()) {
|
|
|
|
|
const uint32_t shiftAmount = rConstp->toU32();
|
2025-08-10 19:14:02 +02:00
|
|
|
if (shiftAmount >= width) {
|
2026-07-05 12:40:08 +02:00
|
|
|
MASK(vtxp).setOnes();
|
2025-08-10 19:14:02 +02:00
|
|
|
} else {
|
2026-07-05 12:40:08 +02:00
|
|
|
V3Number& m = MASK(vtxp).num();
|
|
|
|
|
m.opShiftR(MASK(lhsp).num(), rConstp->num());
|
2025-11-29 20:01:22 +01:00
|
|
|
m.opSetRange(width - shiftAmount, shiftAmount, '1');
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
2025-07-11 20:19:09 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
// Otherwise, as the shift amount is non-negative, all independent
|
|
|
|
|
// and consecutive top bits in the lhs yield an independent result
|
|
|
|
|
// if the shift amount is independent.
|
2026-07-05 12:40:08 +02:00
|
|
|
if (MASK(rhsp).isOnes()) {
|
|
|
|
|
V3Number& m = MASK(vtxp).num();
|
|
|
|
|
m = MASK(lhsp).num();
|
2025-12-08 19:43:21 +01:00
|
|
|
floodTowardsLsb(m);
|
|
|
|
|
}
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgShiftL* vtxp) override {
|
|
|
|
|
DfgVertex* const rhsp = vtxp->rhsp();
|
|
|
|
|
DfgVertex* const lhsp = vtxp->lhsp();
|
|
|
|
|
const uint32_t width = vtxp->width();
|
|
|
|
|
|
|
|
|
|
// Constant shift can be computed precisely
|
|
|
|
|
if (DfgConst* const rConstp = rhsp->cast<DfgConst>()) {
|
|
|
|
|
const uint32_t shiftAmount = rConstp->toU32();
|
2025-08-10 19:14:02 +02:00
|
|
|
if (shiftAmount >= width) {
|
2026-07-05 12:40:08 +02:00
|
|
|
MASK(vtxp).setOnes();
|
2025-08-10 19:14:02 +02:00
|
|
|
} else {
|
2026-07-05 12:40:08 +02:00
|
|
|
V3Number& m = MASK(vtxp).num();
|
|
|
|
|
m.opShiftL(MASK(lhsp).num(), rConstp->num());
|
2025-11-29 20:01:22 +01:00
|
|
|
m.opSetRange(0, shiftAmount, '1');
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
2025-07-11 20:19:09 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
// Otherwise, as the shift amount is non-negative, all independent
|
|
|
|
|
// and consecutive bottom bits in the lhs yield an independent result
|
|
|
|
|
// if the shift amount is independent.
|
2026-07-05 12:40:08 +02:00
|
|
|
if (MASK(rhsp).isOnes()) {
|
|
|
|
|
V3Number& m = MASK(vtxp).num();
|
|
|
|
|
m = MASK(lhsp).num();
|
2025-12-08 19:43:21 +01:00
|
|
|
floodTowardsMsb(m);
|
|
|
|
|
}
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(DfgCond* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
if (MASK(vtxp->condp()).isOnes()) {
|
|
|
|
|
MASK(vtxp).num().opAnd(MASK(vtxp->thenp()).num(), MASK(vtxp->elsep()).num());
|
2025-08-10 19:14:02 +02:00
|
|
|
}
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
|
2026-06-19 20:46:13 +02:00
|
|
|
void visit(DfgMatchMasked* vtxp) override {
|
2026-07-05 12:40:08 +02:00
|
|
|
if (MASK(vtxp->lhsp()).isOnes() && MASK(vtxp->matchp()).isOnes()) { MASK(vtxp).setOnes(); }
|
2026-06-19 20:46:13 +02:00
|
|
|
}
|
|
|
|
|
|
2025-07-11 20:19:09 +02:00
|
|
|
#undef MASK
|
|
|
|
|
|
2025-11-29 20:01:22 +01:00
|
|
|
// Enqueue sinks of vertex to work list for traversal - only called from constructor
|
|
|
|
|
void enqueueSinks(DfgVertex& vtx) {
|
|
|
|
|
vtx.foreachSink([&](DfgVertex& sink) {
|
|
|
|
|
// Ignore if sink is not part of an SCC, already has all bits marked independent
|
2026-06-19 23:28:50 +02:00
|
|
|
if (!m_sccInfo.get(sink)) return false;
|
2025-11-29 20:01:22 +01:00
|
|
|
// Otherwise just enqueue it
|
2026-04-19 20:48:02 +02:00
|
|
|
VertexState& state = m_vtxp2State.at(&sink);
|
|
|
|
|
if (!state.m_isOnWorkList) {
|
2025-12-08 19:43:21 +01:00
|
|
|
UINFO(9, "Enqueuing vertex " << &sink << " " << sink.typeName());
|
2026-04-19 20:48:02 +02:00
|
|
|
m_workQueue.push(state.m_rpoNumber);
|
2025-12-08 19:43:21 +01:00
|
|
|
}
|
2026-04-19 20:48:02 +02:00
|
|
|
state.m_isOnWorkList = true;
|
|
|
|
|
return false;
|
|
|
|
|
});
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void dfsPostOrder(std::unordered_set<DfgVertex*>& visited, //
|
|
|
|
|
std::vector<DfgVertex*>& postOrderEnumeration, //
|
|
|
|
|
DfgVertex& vtx) {
|
|
|
|
|
// Mark visited, skip if already visited
|
|
|
|
|
if (!visited.insert(&vtx).second) return;
|
|
|
|
|
// Visit un-visited successors
|
|
|
|
|
vtx.foreachSink([&](DfgVertex& snk) {
|
|
|
|
|
dfsPostOrder(visited, postOrderEnumeration, snk);
|
2025-11-29 20:01:22 +01:00
|
|
|
return false;
|
|
|
|
|
});
|
2026-04-19 20:48:02 +02:00
|
|
|
// Add to post order enumeration
|
|
|
|
|
postOrderEnumeration.emplace_back(&vtx);
|
2025-11-29 20:01:22 +01:00
|
|
|
};
|
|
|
|
|
|
2026-06-19 23:28:50 +02:00
|
|
|
IndependentBits(DfgGraph& dfg, const SccInfo& sccInfo)
|
|
|
|
|
: m_sccInfo{sccInfo} {
|
2025-08-10 19:14:02 +02:00
|
|
|
|
|
|
|
|
#ifdef VL_DEBUG
|
2025-07-11 20:19:09 +02:00
|
|
|
if (v3Global.opt.debugCheck()) {
|
|
|
|
|
m_lineCoverageFile.open( //
|
|
|
|
|
v3Global.opt.makeDir() + "/" + v3Global.opt.prefix()
|
|
|
|
|
+ "__V3DfgBreakCycles-IndependentBits-line-coverage.txt", //
|
|
|
|
|
std::ios_base::out | std::ios_base::app);
|
|
|
|
|
}
|
2025-08-10 19:14:02 +02:00
|
|
|
#endif
|
2025-07-11 20:19:09 +02:00
|
|
|
|
2026-04-19 20:48:02 +02:00
|
|
|
// Compute Reverse-Postorder enumeration of vertices
|
|
|
|
|
std::vector<DfgVertex*> rpoEnumeration;
|
|
|
|
|
std::unordered_set<DfgVertex*> visited;
|
|
|
|
|
dfg.forEachVertex([&](DfgVertex& vtx) {
|
|
|
|
|
if (!vtx.nInputs()) dfsPostOrder(visited, rpoEnumeration, vtx);
|
|
|
|
|
});
|
|
|
|
|
dfg.forEachVertex([&](DfgVertex& vtx) { //
|
|
|
|
|
dfsPostOrder(visited, rpoEnumeration, vtx);
|
|
|
|
|
});
|
|
|
|
|
std::reverse(rpoEnumeration.begin(), rpoEnumeration.end());
|
|
|
|
|
UASSERT(rpoEnumeration.size() == dfg.size(), "Inconsistent vertex count");
|
|
|
|
|
|
|
|
|
|
// Initialzie VertexState for each vertex
|
|
|
|
|
for (size_t i = 0; i < rpoEnumeration.size(); ++i) {
|
|
|
|
|
VertexState& state = m_vtxp2State[rpoEnumeration[i]];
|
|
|
|
|
state.m_rpoNumber = i;
|
|
|
|
|
state.m_isOnWorkList = false;
|
|
|
|
|
}
|
|
|
|
|
|
2025-11-29 20:01:22 +01:00
|
|
|
// Set up the initial conditions:
|
|
|
|
|
// - For vertices not in an SCC, mark all bits as independent
|
|
|
|
|
// - For vertices in an SCC, dispatch to analyse at least once, as some vertices
|
|
|
|
|
// always assign constants bits, which are always independent (eg Extend/Shift)
|
|
|
|
|
// Enqueue sinks of all SCC vertices that have at least one independent bit
|
2026-04-19 20:48:02 +02:00
|
|
|
for (DfgVertex* const vtxp : rpoEnumeration) {
|
2026-06-19 23:28:50 +02:00
|
|
|
if (m_sccInfo.get(*vtxp)) continue;
|
2026-07-05 12:40:08 +02:00
|
|
|
mask(*vtxp).setOnes();
|
2026-04-19 20:48:02 +02:00
|
|
|
}
|
|
|
|
|
for (DfgVertex* const vtxp : rpoEnumeration) {
|
2026-06-19 23:28:50 +02:00
|
|
|
if (!m_sccInfo.get(*vtxp)) continue;
|
2026-04-19 20:48:02 +02:00
|
|
|
iterate(vtxp);
|
2026-07-05 12:40:08 +02:00
|
|
|
UINFO(9, "Initial independent bits of " << vtxp << " " << vtxp->typeName()
|
|
|
|
|
<< " are: " << mask(*vtxp).toString());
|
|
|
|
|
if (!mask(*vtxp).isZero()) enqueueSinks(*vtxp);
|
2026-04-19 20:48:02 +02:00
|
|
|
}
|
2025-07-11 20:19:09 +02:00
|
|
|
|
2025-11-29 20:01:22 +01:00
|
|
|
// Propagate independent bits until no more changes are made
|
2026-04-19 20:48:02 +02:00
|
|
|
while (!m_workQueue.empty()) {
|
2025-07-11 20:19:09 +02:00
|
|
|
// Grab next item
|
2026-04-19 20:48:02 +02:00
|
|
|
DfgVertex* const currp = rpoEnumeration[m_workQueue.top()];
|
|
|
|
|
m_workQueue.pop();
|
|
|
|
|
m_vtxp2State.at(currp).m_isOnWorkList = false;
|
2025-11-29 20:01:22 +01:00
|
|
|
// Should not enqueue vertices that are not in an SCC
|
2026-06-19 23:28:50 +02:00
|
|
|
UASSERT_OBJ(m_sccInfo.get(*currp), currp, "Vertex should be in an SCC");
|
2025-07-14 23:09:34 +02:00
|
|
|
|
2025-07-11 20:19:09 +02:00
|
|
|
// Grab current mask of item
|
2026-07-05 12:40:08 +02:00
|
|
|
const BitMask& currMask = mask(*currp);
|
2025-11-29 20:01:22 +01:00
|
|
|
// Remember current mask so we can check if it changed
|
2026-07-05 12:40:08 +02:00
|
|
|
const BitMask prevMask = currMask;
|
2025-07-11 20:19:09 +02:00
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
UINFO(9, "Analyzing independent bits of " << currp << " " << currp->typeName());
|
|
|
|
|
|
2025-11-29 20:01:22 +01:00
|
|
|
// Dispatch it to update the mask in the visit methods
|
2025-07-11 20:19:09 +02:00
|
|
|
iterate(currp);
|
|
|
|
|
|
|
|
|
|
// If mask changed, enqueue sinks
|
2026-07-05 12:40:08 +02:00
|
|
|
if (prevMask != currMask) {
|
2025-12-08 19:43:21 +01:00
|
|
|
UINFO(9, "Independent bits of " //
|
|
|
|
|
<< currp << " " << currp->typeName() << " changed" //
|
2026-07-05 12:40:08 +02:00
|
|
|
<< "\n form: " << prevMask.toString()
|
|
|
|
|
<< "\n to: " << currMask.toString());
|
2025-11-29 20:01:22 +01:00
|
|
|
enqueueSinks(*currp);
|
|
|
|
|
// Check the mask only ever expands (no bit goes 1 -> 0)
|
2025-07-11 20:19:09 +02:00
|
|
|
if (VL_UNLIKELY(v3Global.opt.debugCheck())) {
|
2026-07-05 12:40:08 +02:00
|
|
|
UASSERT_OBJ(!currMask.isContractionOf(prevMask), currp,
|
|
|
|
|
"Mask should only expand");
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public:
|
2025-11-29 20:01:22 +01:00
|
|
|
// Given a DfgGraph, and a map from vertices to the SCCs they reside in,
|
|
|
|
|
// returns a map from vertices to a bit mask, where a bit in the mask is
|
|
|
|
|
// set if the corresponding bit in that vertex is known to be independent
|
|
|
|
|
// of the values of vertices in the same SCC as the vertex resides in.
|
2026-07-05 12:40:08 +02:00
|
|
|
static std::unordered_map<const DfgVertex*, BitMask> apply(DfgGraph& dfg,
|
|
|
|
|
const SccInfo& sccInfo) {
|
2026-06-19 23:28:50 +02:00
|
|
|
return std::move(IndependentBits{dfg, sccInfo}.m_vtxp2Mask);
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
class FixUp final {
|
2025-09-02 23:21:24 +02:00
|
|
|
DfgGraph& m_dfg; // The graph being processed
|
2026-06-19 23:28:50 +02:00
|
|
|
SccInfo& m_sccInfo; // The SccInfo instance
|
|
|
|
|
TraceDriver m_traceDriver{m_dfg, m_sccInfo};
|
2025-11-29 20:01:22 +01:00
|
|
|
// The independent bits map
|
2026-07-05 12:40:08 +02:00
|
|
|
const std::unordered_map<const DfgVertex*, BitMask> m_independentBits
|
2026-06-19 23:28:50 +02:00
|
|
|
= IndependentBits::apply(m_dfg, m_sccInfo);
|
2026-07-05 12:40:08 +02:00
|
|
|
size_t m_nImprovements = 0; // Number of improvements made
|
2025-09-02 23:21:24 +02:00
|
|
|
|
|
|
|
|
// Returns a bitmask set if that bit of 'vtx' is used (has a sink)
|
2026-07-05 12:40:08 +02:00
|
|
|
static BitMask computeUsedBits(DfgVertex& vtx) {
|
|
|
|
|
BitMask result{vtx};
|
2025-09-02 23:21:24 +02:00
|
|
|
vtx.foreachSink([&result](DfgVertex& sink) {
|
2025-07-11 20:19:09 +02:00
|
|
|
// If used via a Sel, mark the selected bits used
|
2025-08-20 19:21:24 +02:00
|
|
|
if (const DfgSel* const selp = sink.cast<DfgSel>()) {
|
2026-07-05 12:40:08 +02:00
|
|
|
result.num().opSetRange(selp->lsb(), selp->width(), '1');
|
2025-09-02 17:50:40 +02:00
|
|
|
return false;
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
// Used without a Sel, so all bits are used
|
2026-07-05 12:40:08 +02:00
|
|
|
result.setOnes();
|
2025-12-08 19:43:21 +01:00
|
|
|
return true;
|
2025-07-11 20:19:09 +02:00
|
|
|
});
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
static std::string debugStr(const DfgVertex& vtx) { // LCOV_EXCL_START
|
2025-09-02 23:21:24 +02:00
|
|
|
if (const DfgArraySel* const aselp = vtx.cast<DfgArraySel>()) {
|
2025-07-22 09:23:45 +02:00
|
|
|
const size_t i = aselp->bitp()->as<DfgConst>()->toSizeT();
|
2025-09-02 23:21:24 +02:00
|
|
|
return debugStr(*aselp->fromp()) + "[" + std::to_string(i) + "]";
|
2025-07-22 09:23:45 +02:00
|
|
|
}
|
2025-09-02 23:21:24 +02:00
|
|
|
if (const DfgVertexVar* const varp = vtx.cast<DfgVertexVar>()) {
|
2026-04-09 14:31:12 +02:00
|
|
|
return varp->vscp()->name();
|
2025-07-22 09:23:45 +02:00
|
|
|
}
|
2025-10-03 12:49:13 +02:00
|
|
|
vtx.v3fatalSrc("Unhandled node type");
|
2025-12-08 19:43:21 +01:00
|
|
|
} // LCOV_EXCL_STOP
|
2025-07-22 09:23:45 +02:00
|
|
|
|
|
|
|
|
// Trace drivers of independent bits of 'vtxp' in the range '[hi:lo]'
|
2025-12-08 19:43:21 +01:00
|
|
|
// append replacement terms to 'termps'.
|
2025-09-02 23:21:24 +02:00
|
|
|
void gatherTerms(std::vector<DfgVertex*>& termps, DfgVertex& vtx, const V3Number& indpBits,
|
|
|
|
|
const uint32_t hi, const uint32_t lo) {
|
2025-07-11 20:19:09 +02:00
|
|
|
// Iterate through consecutive dependent/non-dependet ranges within [hi:lo]
|
|
|
|
|
bool isIndependent = indpBits.bitIs1(lo);
|
|
|
|
|
uint32_t lsb = lo;
|
|
|
|
|
for (uint32_t msb = lo; msb <= hi; ++msb) {
|
|
|
|
|
const bool endRange = msb == hi || isIndependent != indpBits.bitIs1(msb + 1);
|
|
|
|
|
if (!endRange) continue;
|
|
|
|
|
const uint32_t width = msb - lsb + 1;
|
2025-12-08 19:43:21 +01:00
|
|
|
// Compute the term to use for this range
|
2025-07-11 20:19:09 +02:00
|
|
|
if (isIndependent) {
|
2025-12-08 19:43:21 +01:00
|
|
|
// If the range is independent of the cycles, trace its driver
|
|
|
|
|
++m_nImprovements;
|
|
|
|
|
termps.emplace_back(m_traceDriver.apply(vtx, lsb, width));
|
|
|
|
|
} else {
|
|
|
|
|
// If dependent, fall back on using the part of the variable
|
2025-09-07 21:38:50 +02:00
|
|
|
DfgSel* const selp = new DfgSel{m_dfg, vtx.fileline(), DfgDataType::packed(width)};
|
2025-07-24 16:31:09 +02:00
|
|
|
// Same component as 'vtxp', as reads 'vtxp' and will replace 'vtxp'
|
2026-06-19 23:28:50 +02:00
|
|
|
m_sccInfo.add(*selp, m_sccInfo.get(vtx));
|
2025-07-22 09:23:45 +02:00
|
|
|
// Do not connect selp->fromp yet, need to do afer replacing 'vtxp'
|
2025-07-11 20:19:09 +02:00
|
|
|
selp->lsb(lsb);
|
2025-12-08 19:43:21 +01:00
|
|
|
termps.emplace_back(selp);
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
// Next iteration
|
|
|
|
|
isIndependent = !isIndependent;
|
|
|
|
|
lsb = msb + 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2025-09-02 23:21:24 +02:00
|
|
|
void fixUpPacked(DfgVertex& vtx) {
|
|
|
|
|
UASSERT_OBJ(vtx.isPacked(), &vtx, "Should be a packed type");
|
2025-11-29 20:01:22 +01:00
|
|
|
UASSERT_OBJ(!vtx.is<DfgSplicePacked>(), &vtx, "Should not be a splice");
|
|
|
|
|
|
|
|
|
|
// Get which bits of 'vtxp' are independent of the SCCs
|
2026-07-05 12:40:08 +02:00
|
|
|
const BitMask& indpBits = m_independentBits.at(&vtx);
|
|
|
|
|
UINFO(9, "Independent bits of '" << debugStr(vtx) << "' are " << indpBits.toString());
|
2025-11-29 20:01:22 +01:00
|
|
|
// Can't do anything if all bits are dependent
|
2026-07-05 12:40:08 +02:00
|
|
|
if (indpBits.isZero()) return;
|
2025-07-11 20:19:09 +02:00
|
|
|
|
2025-07-22 09:23:45 +02:00
|
|
|
// Figure out which bits of 'vtxp' are used
|
2026-07-05 12:40:08 +02:00
|
|
|
const BitMask usedBits = computeUsedBits(vtx);
|
|
|
|
|
UINFO(9, "Used bits of '" << debugStr(vtx) << "' are " << usedBits.toString());
|
2025-12-08 19:43:21 +01:00
|
|
|
|
|
|
|
|
// Nothing to do if no used bits are independen (all used bits are dependent)
|
|
|
|
|
V3Number usedAndIndependent{vtx.fileline(), static_cast<int>(vtx.width()), 0};
|
2026-07-05 12:40:08 +02:00
|
|
|
usedAndIndependent.opAnd(usedBits.num(), indpBits.num());
|
2025-12-08 19:43:21 +01:00
|
|
|
if (usedAndIndependent.isEqZero()) return;
|
2025-07-11 20:19:09 +02:00
|
|
|
|
2025-07-22 09:23:45 +02:00
|
|
|
// We are computing the terms to concatenate and replace 'vtxp' with
|
2025-07-11 20:19:09 +02:00
|
|
|
std::vector<DfgVertex*> termps;
|
|
|
|
|
|
|
|
|
|
// Iterate through consecutive used/unused ranges
|
2025-09-02 23:21:24 +02:00
|
|
|
FileLine* const flp = vtx.fileline();
|
|
|
|
|
const uint32_t width = vtx.width();
|
2026-07-05 12:40:08 +02:00
|
|
|
bool isUsed = usedBits.num().bitIs1(0); // Is current range used
|
2025-07-11 20:19:09 +02:00
|
|
|
uint32_t lsb = 0; // LSB of current range
|
|
|
|
|
for (uint32_t msb = 0; msb < width; ++msb) {
|
2026-07-05 12:40:08 +02:00
|
|
|
const bool endRange = msb == width - 1 || isUsed != usedBits.num().bitIs1(msb + 1);
|
2025-07-11 20:19:09 +02:00
|
|
|
if (!endRange) continue;
|
|
|
|
|
if (isUsed) {
|
|
|
|
|
// The range is used, compute the replacement terms
|
2026-07-05 12:40:08 +02:00
|
|
|
gatherTerms(termps, vtx, indpBits.num(), msb, lsb);
|
2025-07-11 20:19:09 +02:00
|
|
|
} else {
|
|
|
|
|
// The range is not used, just use constant 0 as a placeholder
|
2025-09-02 23:21:24 +02:00
|
|
|
DfgConst* const constp = new DfgConst{m_dfg, flp, msb - lsb + 1, 0};
|
2026-06-19 23:28:50 +02:00
|
|
|
m_sccInfo.add(*constp, 0);
|
2025-07-24 16:31:09 +02:00
|
|
|
termps.emplace_back(constp);
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
// Next iteration
|
|
|
|
|
isUsed = !isUsed;
|
|
|
|
|
lsb = msb + 1;
|
|
|
|
|
}
|
|
|
|
|
|
2025-08-15 09:20:36 +02:00
|
|
|
// Concatenate all the terms to create the replacement
|
|
|
|
|
DfgVertex* replacementp = termps.front();
|
2026-06-19 23:28:50 +02:00
|
|
|
const uint64_t vComp = m_sccInfo.get(vtx);
|
2025-08-15 09:20:36 +02:00
|
|
|
for (size_t i = 1; i < termps.size(); ++i) {
|
|
|
|
|
DfgVertex* const termp = termps[i];
|
|
|
|
|
const uint32_t catWidth = replacementp->width() + termp->width();
|
2025-09-07 21:38:50 +02:00
|
|
|
DfgConcat* const catp = new DfgConcat{m_dfg, flp, DfgDataType::packed(catWidth)};
|
2025-08-15 09:20:36 +02:00
|
|
|
catp->rhsp(replacementp);
|
|
|
|
|
catp->lhsp(termp);
|
|
|
|
|
// Need to figure out which component the replacement vertex
|
|
|
|
|
// belongs to. If any of the terms are of the original
|
|
|
|
|
// component, it's part of that component, otherwise its not
|
|
|
|
|
// cyclic (all terms are from outside the original component,
|
|
|
|
|
// and feed into the original component).
|
2026-06-19 23:28:50 +02:00
|
|
|
const uint64_t tComp = m_sccInfo.get(*termp);
|
|
|
|
|
const uint64_t rComp = m_sccInfo.get(*replacementp);
|
|
|
|
|
m_sccInfo.add(*catp, tComp == vComp || rComp == vComp ? vComp : 0);
|
2025-08-15 09:20:36 +02:00
|
|
|
replacementp = catp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Replace the vertex
|
2025-09-02 23:21:24 +02:00
|
|
|
vtx.replaceWith(replacementp);
|
2025-08-15 09:20:36 +02:00
|
|
|
// Connect the Sel nodes in the replacement
|
|
|
|
|
for (DfgVertex* const termp : termps) {
|
|
|
|
|
if (DfgSel* const selp = termp->cast<DfgSel>()) {
|
2025-09-02 23:21:24 +02:00
|
|
|
if (!selp->fromp()) selp->fromp(&vtx);
|
2025-07-11 20:19:09 +02:00
|
|
|
}
|
|
|
|
|
}
|
2026-06-19 23:28:50 +02:00
|
|
|
|
|
|
|
|
// If the vertex still has sinks, then the replacement is still cyclic, and vice versa
|
|
|
|
|
UASSERT_OBJ(!vtx.hasSinks() == !m_sccInfo.get(*replacementp), &vtx,
|
|
|
|
|
"Replacement vertex SCC inconsistent");
|
|
|
|
|
|
|
|
|
|
// If we broke the cycle through this vertex we can update the SccInfo
|
|
|
|
|
if (!vtx.hasSinks()) {
|
|
|
|
|
m_sccInfo.updateAcyclic(vtx);
|
|
|
|
|
if (!m_sccInfo.get(*replacementp)) {
|
|
|
|
|
replacementp->foreachSink([&](DfgVertex& dst) {
|
|
|
|
|
if (!m_sccInfo.get(dst)) return false;
|
|
|
|
|
if (!m_sccInfo.stillCyclicFwd(dst)) m_sccInfo.updateAcyclic(dst);
|
|
|
|
|
return false;
|
|
|
|
|
});
|
|
|
|
|
}
|
|
|
|
|
}
|
2025-07-22 09:23:45 +02:00
|
|
|
}
|
|
|
|
|
|
2025-09-02 23:21:24 +02:00
|
|
|
void main(DfgVertexVar& var) {
|
2026-04-09 14:31:12 +02:00
|
|
|
UINFO(9, "FixUp of " << var.vscp()->name());
|
2025-07-22 09:23:45 +02:00
|
|
|
|
2025-09-02 23:21:24 +02:00
|
|
|
if (var.is<DfgVarPacked>()) {
|
2025-07-22 09:23:45 +02:00
|
|
|
// For Packed variables, fix up as whole
|
2025-09-02 23:21:24 +02:00
|
|
|
fixUpPacked(var);
|
|
|
|
|
} else if (var.is<DfgVarArray>()) {
|
2025-07-22 09:23:45 +02:00
|
|
|
// For array variables, fix up element-wise
|
2026-06-19 23:28:50 +02:00
|
|
|
const uint64_t component = m_sccInfo.get(var);
|
2025-09-02 23:21:24 +02:00
|
|
|
var.foreachSink([&](DfgVertex& sink) {
|
2025-07-24 16:31:09 +02:00
|
|
|
// Ignore if sink is not part of same cycle
|
2026-06-19 23:28:50 +02:00
|
|
|
if (m_sccInfo.get(sink) != component) return false;
|
2025-07-22 09:23:45 +02:00
|
|
|
// Only handle ArraySels with constant index
|
|
|
|
|
DfgArraySel* const aselp = sink.cast<DfgArraySel>();
|
2025-09-02 17:50:40 +02:00
|
|
|
if (!aselp) return false;
|
|
|
|
|
if (!aselp->bitp()->is<DfgConst>()) return false;
|
2025-07-22 09:23:45 +02:00
|
|
|
// Fix up the word
|
2025-09-02 23:21:24 +02:00
|
|
|
fixUpPacked(*aselp);
|
2025-09-02 17:50:40 +02:00
|
|
|
return false;
|
2025-07-22 09:23:45 +02:00
|
|
|
});
|
|
|
|
|
}
|
|
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
UINFO(9, "FixUp made " << m_nImprovements << " improvements");
|
2025-09-02 23:21:24 +02:00
|
|
|
}
|
|
|
|
|
|
2026-06-19 23:28:50 +02:00
|
|
|
FixUp(DfgGraph& dfg, SccInfo& sccInfo)
|
2025-09-02 23:21:24 +02:00
|
|
|
: m_dfg{dfg}
|
2026-06-19 23:28:50 +02:00
|
|
|
, m_sccInfo{sccInfo} {}
|
2025-09-02 23:21:24 +02:00
|
|
|
|
|
|
|
|
public:
|
2025-12-08 19:43:21 +01:00
|
|
|
// Compute which bits of vertices are independent of the SCC they reside
|
|
|
|
|
// in, and replace rferences to used independent bits with an equivalent
|
|
|
|
|
// vertex that is not part of the same SCC.
|
2026-06-19 23:28:50 +02:00
|
|
|
static size_t apply(DfgGraph& dfg, SccInfo& sccInfo) {
|
|
|
|
|
if (!sccInfo.isCyclic()) return 0;
|
|
|
|
|
|
|
|
|
|
FixUp fixUp{dfg, sccInfo};
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2025-12-08 19:43:21 +01:00
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// TODO: Compute minimal feedback vertex set and cut only those.
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// Sadly that is a computationally hard problem.
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2026-06-19 23:28:50 +02:00
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// Fix up cyclic variables, stop as soon as the graph becomes acyclic
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2025-12-08 19:43:21 +01:00
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for (DfgVertexVar& vtx : dfg.varVertices()) {
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2026-06-19 23:28:50 +02:00
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if (!sccInfo.get(vtx)) continue;
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fixUp.main(vtx);
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if (!sccInfo.isCyclic()) break;
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2025-12-08 19:43:21 +01:00
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}
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// Return the number of improvements made
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return fixUp.m_nImprovements;
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2025-07-11 20:19:09 +02:00
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}
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};
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2025-07-26 21:37:01 +02:00
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std::pair<std::unique_ptr<DfgGraph>, bool> //
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2025-12-08 19:43:21 +01:00
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breakCycles(const DfgGraph& dfg, V3DfgContext& ctx) {
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2025-07-10 19:46:45 +02:00
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// Shorthand for dumping graph at given dump level
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const auto dump = [&](int level, const DfgGraph& dfg, const std::string& name) {
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2026-04-09 14:31:12 +02:00
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if (dumpDfgLevel() >= level) dfg.dumpDotFilePrefixed("breakCycles-" + name);
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2025-07-10 19:46:45 +02:00
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};
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// Can't do much with trivial things ('a = a' or 'a[1] = a[0]'), so bail
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if (dfg.size() <= 2) {
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UINFO(7, "Graph is trivial");
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dump(9, dfg, "trivial");
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++ctx.m_breakCyclesContext.m_nTrivial;
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return {nullptr, false};
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}
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|
2025-09-04 16:02:33 +02:00
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|
// AstNetlist/AstNodeModule user2 used as sequence numbers for temporaries
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const VNUser2InUse user2InUse;
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|
2025-07-10 19:46:45 +02:00
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|
// Show input for debugging
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dump(7, dfg, "input");
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|
// We might fail to make any improvements, so first create a clone of the
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|
// graph. This is what we will be working on, and return if successful.
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|
// Do not touch the input graph.
|
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|
std::unique_ptr<DfgGraph> resultp = dfg.clone();
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|
|
// Just shorthand for code below
|
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|
|
DfgGraph& res = *resultp;
|
|
|
|
|
dump(9, res, "clone");
|
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|
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|
|
// How many improvements have we made
|
|
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|
|
size_t nImprovements = 0;
|
|
|
|
|
size_t prevNImprovements;
|
|
|
|
|
|
|
|
|
|
// Iterate while an improvement can be made and the graph is still cyclic
|
|
|
|
|
do {
|
2026-06-19 23:28:50 +02:00
|
|
|
// Compute SCCs
|
|
|
|
|
SccInfo sccInfo{res};
|
2025-07-10 19:46:45 +02:00
|
|
|
|
2025-12-08 19:43:21 +01:00
|
|
|
// Fix up independent ranges in vertices
|
2025-07-10 19:46:45 +02:00
|
|
|
UINFO(9, "New iteration after " << nImprovements << " improvements");
|
|
|
|
|
prevNImprovements = nImprovements;
|
2026-06-19 23:28:50 +02:00
|
|
|
const size_t nFixed = FixUp::apply(res, sccInfo);
|
2025-12-08 19:43:21 +01:00
|
|
|
if (nFixed) {
|
|
|
|
|
nImprovements += nFixed;
|
|
|
|
|
ctx.m_breakCyclesContext.m_nImprovements += nFixed;
|
|
|
|
|
dump(9, res, "FixUp");
|
2025-07-10 19:46:45 +02:00
|
|
|
}
|
2026-06-19 23:28:50 +02:00
|
|
|
|
|
|
|
|
// Validate SccInfo if in debug mode
|
|
|
|
|
if (v3Global.opt.debugCheck()) sccInfo.validate();
|
|
|
|
|
|
|
|
|
|
// Congrats if it has become acyclic
|
|
|
|
|
if (!sccInfo.isCyclic()) {
|
|
|
|
|
UINFO(7, "Graph became acyclic after " << nImprovements << " improvements");
|
|
|
|
|
dump(7, res, "result-acyclic");
|
|
|
|
|
++ctx.m_breakCyclesContext.m_nFixed;
|
|
|
|
|
return {std::move(resultp), true};
|
|
|
|
|
}
|
2025-07-10 19:46:45 +02:00
|
|
|
} while (nImprovements != prevNImprovements);
|
|
|
|
|
|
2025-08-10 10:19:16 +02:00
|
|
|
if (dumpDfgLevel() >= 9) {
|
2026-06-19 23:28:50 +02:00
|
|
|
const SccInfo sccInfo{res};
|
2026-04-09 14:31:12 +02:00
|
|
|
res.dumpDotFilePrefixed("breakCycles-remaining", [&](const DfgVertex& vtx) {
|
2026-06-19 23:28:50 +02:00
|
|
|
return sccInfo.get(vtx); //
|
2025-09-02 23:21:24 +02:00
|
|
|
});
|
2025-08-10 10:19:16 +02:00
|
|
|
}
|
|
|
|
|
|
2025-07-10 19:46:45 +02:00
|
|
|
// If an improvement was made, return the still cyclic improved graph
|
|
|
|
|
if (nImprovements) {
|
|
|
|
|
UINFO(7, "Graph was improved " << nImprovements << " times");
|
|
|
|
|
dump(7, res, "result-improved");
|
|
|
|
|
++ctx.m_breakCyclesContext.m_nImproved;
|
|
|
|
|
return {std::move(resultp), false};
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// No improvement was made
|
|
|
|
|
UINFO(7, "Graph NOT improved");
|
|
|
|
|
dump(7, res, "result-original");
|
|
|
|
|
++ctx.m_breakCyclesContext.m_nUnchanged;
|
|
|
|
|
return {nullptr, false};
|
|
|
|
|
}
|
2025-12-08 19:43:21 +01:00
|
|
|
|
|
|
|
|
} //namespace V3DfgBreakCycles
|
|
|
|
|
|
|
|
|
|
std::pair<std::unique_ptr<DfgGraph>, bool> //
|
|
|
|
|
V3DfgPasses::breakCycles(const DfgGraph& dfg, V3DfgContext& ctx) {
|
|
|
|
|
auto pair = V3DfgBreakCycles::breakCycles(dfg, ctx);
|
|
|
|
|
if (pair.first) {
|
|
|
|
|
if (v3Global.opt.debugCheck()) V3DfgPasses::typeCheck(*pair.first);
|
|
|
|
|
V3DfgPasses::removeUnused(*pair.first);
|
|
|
|
|
}
|
|
|
|
|
return pair;
|
|
|
|
|
}
|