verilator/test_regress/t/t_pp_lib.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2008 Wilson Snyder
// SPDX-License-Identifier: CC0-1.0

`include "t_pp_lib_inc.vh"
module t;
  wire [`WIDTH-1:0] a;
  library_cell n1(a);
endmodule
Fix definitions in main file.v, referenced in library. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@999 77ca24e4-aefa-0310-84f0-b9a241c72d87 2008-03-19 01:44:54 +01:00			`// DESCRIPTION: Verilator: Verilog Test module`
			`//`
Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-27 02:24:34 +01:00			`// This file ONLY is placed under the Creative Commons Public Domain.`
			`// SPDX-FileCopyrightText: 2008 Wilson Snyder`
Add SPDX license identifiers. No functional change. 2020-03-21 16:24:24 +01:00			`// SPDX-License-Identifier: CC0-1.0`
Fix definitions in main file.v, referenced in library. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@999 77ca24e4-aefa-0310-84f0-b9a241c72d87 2008-03-19 01:44:54 +01:00
Tests: Rename includes to .vh extensions 2010-07-09 02:51:54 +02:00			`include "t_pp_lib_inc.vh"
Verilog format 2026-03-03 13:21:24 +01:00			`module t;`
Tests: Verilog format 2026-03-10 02:38:29 +01:00			wire [`WIDTH-1:0] a;
			`library_cell n1(a);`
Fix definitions in main file.v, referenced in library. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@999 77ca24e4-aefa-0310-84f0-b9a241c72d87 2008-03-19 01:44:54 +01:00			`endmodule`