2006-09-01 16:05:20 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
|
|
|
// SPDX-FileCopyrightText: 2003-2007 Wilson Snyder
|
2020-03-21 16:24:24 +01:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
2006-09-01 16:05:20 +02:00
|
|
|
|
|
|
|
|
module t;
|
2026-03-08 23:26:40 +01:00
|
|
|
initial begin
|
|
|
|
|
$write("*-* All Finished *-*\n");
|
|
|
|
|
$finish;
|
|
|
|
|
end
|
2006-09-01 16:05:20 +02:00
|
|
|
endmodule
|