2025-10-01 13:05:02 +02:00
|
|
|
// -*- mode: C++; c-file-style: "cc-mode" -*-
|
|
|
|
|
//
|
|
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
|
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
|
|
|
// any use, without warranty, 2025 by Wilson Snyder.
|
|
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
|
|
|
|
|
|
#include <verilated.h>
|
|
|
|
|
|
|
|
|
|
#include <svdpi.h>
|
|
|
|
|
|
2025-10-22 08:58:39 +02:00
|
|
|
extern "C" int instrument_var(int id, int trigger, const svLogic* x) {
|
2025-10-01 14:26:14 +02:00
|
|
|
switch (id) {
|
2025-10-22 08:58:39 +02:00
|
|
|
case 0:
|
|
|
|
|
if ((VL_TIME_Q() >= 10 && VL_TIME_Q() < 20) || VL_TIME_Q() >= 85) {
|
|
|
|
|
return 0;
|
|
|
|
|
} else {
|
|
|
|
|
return *x;
|
|
|
|
|
}
|
|
|
|
|
//return 0;
|
2025-10-01 13:05:02 +02:00
|
|
|
case 1:
|
2025-10-23 09:34:55 +02:00
|
|
|
if ((VL_TIME_Q() < 3) || (VL_TIME_Q() >= 32 && VL_TIME_Q() < 69)) {
|
2025-10-22 08:58:39 +02:00
|
|
|
return 1;
|
|
|
|
|
} else {
|
|
|
|
|
return *x;
|
|
|
|
|
}
|
2025-10-01 14:26:14 +02:00
|
|
|
default: return *x;
|
2025-10-01 13:05:02 +02:00
|
|
|
}
|
|
|
|
|
}
|