31 lines
768 B
C++
31 lines
768 B
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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#include <svdpi.h>
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extern "C" int instrument_var(int id, int trigger, const svLogic* x) {
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switch (id) {
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case 0:
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if ((VL_TIME_Q() >= 10 && VL_TIME_Q() < 20) || VL_TIME_Q() >= 85) {
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return 0;
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} else {
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return *x;
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}
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//return 0;
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case 1:
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if ((VL_TIME_Q() < 3) || (VL_TIME_Q() >= 32 && VL_TIME_Q() < 69)) {
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return 1;
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} else {
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return *x;
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}
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default: return *x;
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}
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}
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