test: Add regression tests for instrumentation
This commit is contained in:
Jonathan Schröter
parent
5f2cb6545a
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300001bcdd
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include <fstream>
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#include VM_PREFIX_INCLUDE
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unsigned long long main_time = 0;
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double sc_time_stamp() { return main_time; }
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int main(int argc, char** argv) {
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Verilated::debug(0);
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Verilated::commandArgs(argc, argv);
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std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"top"}};
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std::ofstream logFile("obj_vlt/t_instrumentation/simulation_output.log");
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if (!logFile.is_open()) {
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printf("Error: Could not open log file\n");
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return 1;
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}
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while (main_time <= 100) {
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top->eval();
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logFile << "$time: " << main_time << " | "
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<< "Output outa: " << static_cast<int>(top->outa) << " | "
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<< "Output outb: " << static_cast<int>(top->outb) << std::endl;
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++main_time;
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}
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top->final();
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top.reset();
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printf("*-* All Finished *-*\n");
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return 0;
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}
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@ -0,0 +1,101 @@
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$time: 0 | Output outa: 0 | Output outb: 50
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$time: 1 | Output outa: 0 | Output outb: 50
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$time: 2 | Output outa: 0 | Output outb: 50
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$time: 3 | Output outa: 0 | Output outb: 50
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$time: 4 | Output outa: 0 | Output outb: 50
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$time: 5 | Output outa: 0 | Output outb: 50
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$time: 6 | Output outa: 0 | Output outb: 50
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$time: 7 | Output outa: 0 | Output outb: 50
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$time: 8 | Output outa: 0 | Output outb: 50
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$time: 9 | Output outa: 0 | Output outb: 50
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$time: 10 | Output outa: 0 | Output outb: 50
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$time: 11 | Output outa: 0 | Output outb: 50
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$time: 12 | Output outa: 0 | Output outb: 50
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$time: 13 | Output outa: 0 | Output outb: 50
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$time: 14 | Output outa: 0 | Output outb: 50
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$time: 15 | Output outa: 0 | Output outb: 50
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$time: 16 | Output outa: 0 | Output outb: 50
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$time: 17 | Output outa: 0 | Output outb: 50
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$time: 18 | Output outa: 0 | Output outb: 50
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$time: 19 | Output outa: 0 | Output outb: 50
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$time: 20 | Output outa: 0 | Output outb: 50
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$time: 21 | Output outa: 0 | Output outb: 50
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$time: 22 | Output outa: 0 | Output outb: 50
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$time: 23 | Output outa: 0 | Output outb: 50
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$time: 24 | Output outa: 0 | Output outb: 50
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$time: 25 | Output outa: 0 | Output outb: 50
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$time: 26 | Output outa: 0 | Output outb: 50
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$time: 27 | Output outa: 0 | Output outb: 50
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$time: 28 | Output outa: 0 | Output outb: 50
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$time: 29 | Output outa: 0 | Output outb: 50
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$time: 30 | Output outa: 0 | Output outb: 50
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$time: 31 | Output outa: 0 | Output outb: 50
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$time: 32 | Output outa: 0 | Output outb: 50
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$time: 33 | Output outa: 0 | Output outb: 50
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$time: 34 | Output outa: 0 | Output outb: 50
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$time: 35 | Output outa: 0 | Output outb: 50
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$time: 36 | Output outa: 0 | Output outb: 50
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$time: 37 | Output outa: 0 | Output outb: 50
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$time: 38 | Output outa: 0 | Output outb: 50
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$time: 39 | Output outa: 0 | Output outb: 50
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$time: 40 | Output outa: 0 | Output outb: 50
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$time: 41 | Output outa: 0 | Output outb: 50
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$time: 42 | Output outa: 0 | Output outb: 50
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$time: 43 | Output outa: 0 | Output outb: 50
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$time: 44 | Output outa: 0 | Output outb: 50
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$time: 45 | Output outa: 0 | Output outb: 50
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$time: 46 | Output outa: 0 | Output outb: 50
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$time: 47 | Output outa: 0 | Output outb: 50
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$time: 48 | Output outa: 0 | Output outb: 50
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$time: 49 | Output outa: 0 | Output outb: 50
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$time: 50 | Output outa: 0 | Output outb: 50
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$time: 51 | Output outa: 0 | Output outb: 50
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$time: 52 | Output outa: 0 | Output outb: 50
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$time: 53 | Output outa: 0 | Output outb: 50
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$time: 54 | Output outa: 0 | Output outb: 50
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$time: 55 | Output outa: 0 | Output outb: 50
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$time: 56 | Output outa: 0 | Output outb: 50
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$time: 57 | Output outa: 0 | Output outb: 50
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$time: 58 | Output outa: 0 | Output outb: 50
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$time: 59 | Output outa: 0 | Output outb: 50
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$time: 60 | Output outa: 0 | Output outb: 50
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$time: 61 | Output outa: 0 | Output outb: 50
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$time: 62 | Output outa: 0 | Output outb: 50
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$time: 63 | Output outa: 0 | Output outb: 50
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$time: 64 | Output outa: 0 | Output outb: 50
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$time: 65 | Output outa: 0 | Output outb: 50
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$time: 66 | Output outa: 0 | Output outb: 50
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$time: 67 | Output outa: 0 | Output outb: 50
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$time: 68 | Output outa: 0 | Output outb: 50
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$time: 69 | Output outa: 0 | Output outb: 50
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$time: 70 | Output outa: 0 | Output outb: 50
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$time: 71 | Output outa: 0 | Output outb: 50
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$time: 72 | Output outa: 0 | Output outb: 50
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$time: 73 | Output outa: 0 | Output outb: 50
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$time: 74 | Output outa: 0 | Output outb: 50
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$time: 75 | Output outa: 0 | Output outb: 50
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$time: 76 | Output outa: 0 | Output outb: 50
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$time: 77 | Output outa: 0 | Output outb: 50
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$time: 78 | Output outa: 0 | Output outb: 50
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$time: 79 | Output outa: 0 | Output outb: 50
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$time: 80 | Output outa: 0 | Output outb: 50
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$time: 81 | Output outa: 0 | Output outb: 50
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$time: 82 | Output outa: 0 | Output outb: 50
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$time: 83 | Output outa: 0 | Output outb: 50
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$time: 84 | Output outa: 0 | Output outb: 50
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$time: 85 | Output outa: 0 | Output outb: 50
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$time: 86 | Output outa: 0 | Output outb: 50
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$time: 87 | Output outa: 0 | Output outb: 50
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$time: 88 | Output outa: 0 | Output outb: 50
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$time: 89 | Output outa: 0 | Output outb: 50
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$time: 90 | Output outa: 0 | Output outb: 50
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$time: 91 | Output outa: 0 | Output outb: 50
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$time: 92 | Output outa: 0 | Output outb: 50
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$time: 93 | Output outa: 0 | Output outb: 50
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$time: 94 | Output outa: 0 | Output outb: 50
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$time: 95 | Output outa: 0 | Output outb: 50
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$time: 96 | Output outa: 0 | Output outb: 50
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$time: 97 | Output outa: 0 | Output outb: 50
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$time: 98 | Output outa: 0 | Output outb: 50
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$time: 99 | Output outa: 0 | Output outb: 50
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$time: 100 | Output outa: 0 | Output outb: 50
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_instrumentation.v"
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sim_filename = "t/" + test.name + ".cpp"
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dpi_filename = "t/t_instrumentationDPI.cpp"
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vlt_filename = "t/" + test.name + ".vlt"
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log_filename = "obj_vlt/t_instrumentation/simulation_output.log"
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test.compile(make_top_shell=False,
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make_main=False,
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v_flags2=["--trace --exe --instrument", sim_filename, vlt_filename, dpi_filename])
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test.execute()
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test.files_identical(log_filename, test.golden_filename)
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test.passes()
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module top_module(
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output logic [7:0] outa,
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output logic [7:0] outb
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);
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logic [7:0] in1a = 8'd5;
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logic [7:0] in2a = 8'd10;
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logic [7:0] in1b = 8'd20;
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logic [7:0] in2b = 8'd30;
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module_a a1 (.in1(in1a), .in2(in2a), .out(outa));
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module_a a2 (.in1(in1b), .in2(in2b), .out(outb));
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endmodule
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module module_a(
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input logic [7:0] in1,
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input logic [7:0] in2,
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output logic [7:0] out
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);
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module_b b1 (.in1(in1), .in2(in2), .out(out));
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endmodule
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module module_b (
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input logic [7:0] in1,
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input logic [7:0] in2,
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output logic [7:0] out
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);
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always_comb begin
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out = in1 + in2;
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end
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endmodule
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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instrument -model "instrument_var" -id 0 -target "top_module.a1.b1.out"
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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#include <iostream>
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#include <svdpi.h>
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extern "C" short instrument_var(int id, const svLogic *x) {
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switch (id)
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{
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case 0:
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return 0;
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case 1:
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// Stuck at 1 Fault Injection
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return 1;
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case 2:
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// Inverter/Bit flip Fault injection (provisional)
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return !x;
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default:
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return *x;
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}
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}
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