verilator/test_regress/t/t_wire_trireg_unsup.v

// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
//
// Simple bi-directional alias test.
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t;

   trireg unsup;
   trireg (small) unsup_s;
   trireg (medium) unsup_m;
   trireg (large) unsup_l;

endmodule