17 lines
401 B
Systemverilog
17 lines
401 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Simple bi-directional alias test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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trireg unsup;
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trireg (small) unsup_s;
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trireg (medium) unsup_m;
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trireg (large) unsup_l;
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endmodule
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