2015-08-13 01:29:06 +02:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This test examines Verilator against paramter definition with functions.
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// Particularly the function takes in argument which is multi-dimentional.
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2015 Roland Kruse and Jie Xu
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2020-03-21 16:24:24 +01:00
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// SPDX-License-Identifier: CC0-1.0
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2015-08-13 01:29:06 +02:00
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2026-03-10 02:38:29 +01:00
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module test #(
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2025-08-30 00:33:14 +02:00
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parameter SIZE = 4,
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2026-03-10 02:38:29 +01:00
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parameter P = sum({32'h1, 32'h2, 32'h3, 32'h4}, SIZE)
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) (
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input clk,
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input logic sel,
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output [P:0] res
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);
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2015-08-13 01:29:06 +02:00
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2026-03-10 02:38:29 +01:00
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logic [P:0] cc = 'h45;
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2015-08-13 01:29:06 +02:00
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2026-03-10 02:38:29 +01:00
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assign res = sel ? cc : {(P + 1) {1'b1}};
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2015-08-13 01:29:06 +02:00
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2026-03-10 02:38:29 +01:00
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function integer sum;
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input [3:0][31:0] values;
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input int size;
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2015-08-13 01:29:06 +02:00
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2026-03-10 02:38:29 +01:00
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sum = 0;
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2015-08-13 01:29:06 +02:00
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2026-03-10 02:38:29 +01:00
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begin
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for (int i = 0; i < size; i++) sum += values[i];
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end
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endfunction
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2015-08-13 01:29:06 +02:00
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endmodule
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