2020-01-03 13:44:45 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Stefan Wallentowitz
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2020-03-21 16:24:24 +01:00
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// SPDX-License-Identifier: CC0-1.0
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2020-01-03 13:44:45 +01:00
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2026-03-03 13:21:24 +01:00
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module t;
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logic din[0:15];
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2020-01-03 13:44:45 +01:00
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2026-03-03 13:21:24 +01:00
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array_test array_test_inst (.din(din));
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2020-01-03 13:44:45 +01:00
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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2026-03-03 13:21:24 +01:00
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module array_test (
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input din[0:15]
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);
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2020-01-11 00:49:23 +01:00
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endmodule
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