Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Emit C++ for model entry point class
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//
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// Code available from: https://verilator.org
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//
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//*************************************************************************
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//
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2025-01-01 14:30:25 +01:00
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// Copyright 2003-2025 by Wilson Snyder. This program is free software; you
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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2023-10-18 12:37:46 +02:00
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#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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#include "V3EmitC.h"
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#include "V3EmitCFunc.h"
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2021-07-14 23:37:37 +02:00
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#include "V3UniqueNames.h"
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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#include <algorithm>
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2021-11-27 23:07:27 +01:00
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#include <functional>
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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#include <vector>
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2022-09-18 21:53:42 +02:00
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VL_DEFINE_DEBUG_FUNCTIONS;
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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class EmitCModel final : public EmitCFunc {
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2021-11-27 23:07:27 +01:00
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// TYPES
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using CFuncVector = std::vector<const AstCFunc*>;
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// MEMBERS
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2021-07-14 23:37:37 +02:00
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V3UniqueNames m_uniqueNames; // For generating unique file names
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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// METHODS
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2021-11-27 23:07:27 +01:00
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CFuncVector findFuncps(std::function<bool(const AstCFunc*)> cb) {
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CFuncVector funcps;
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for (AstNode* nodep = m_modp->stmtsp(); nodep; nodep = nodep->nextp()) {
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if (const AstCFunc* const funcp = VN_CAST(nodep, CFunc)) {
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if (cb(funcp)) funcps.push_back(funcp);
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}
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}
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stable_sort(funcps.begin(), funcps.end(),
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[](const AstNode* ap, const AstNode* bp) { return ap->name() < bp->name(); });
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return funcps;
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}
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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void putSectionDelimiter(const string& name) {
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puts("\n");
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puts("//============================================================\n");
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puts("// " + name + "\n");
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}
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void emitHeader(AstNodeModule* modp) {
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2024-10-01 03:42:36 +02:00
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UASSERT(!ofp(), "Output file should not be open");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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2025-08-26 04:05:40 +02:00
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const string filename = v3Global.opt.makeDir() + "/" + EmitCUtil::topClassName() + ".h";
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2024-10-01 03:42:36 +02:00
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setOutputFile(v3Global.opt.systemC() ? new V3OutScFile{filename}
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: new V3OutCFile{filename},
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newCFile(filename, /* slow: */ false, /* source: */ false));
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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ofp()->putsHeader();
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puts("// DESCRIPTION: Verilator output: Primary model header\n");
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puts("//\n");
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puts("// This header should be included by all source files instantiating the design.\n");
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puts("// The class here is then constructed to instantiate the design.\n");
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puts("// See the Verilator manual for examples.\n");
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ofp()->putsGuard();
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// Include files
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puts("\n");
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ofp()->putsIntTopInclude();
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2021-07-24 16:00:33 +02:00
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puts("#include \"verilated.h\"\n");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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if (v3Global.opt.mtasks()) puts("#include \"verilated_threads.h\"\n");
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if (v3Global.opt.savable()) puts("#include \"verilated_save.h\"\n");
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if (v3Global.opt.coverage()) puts("#include \"verilated_cov.h\"\n");
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if (v3Global.dpi()) puts("#include \"svdpi.h\"\n");
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// Declare foreign instances up front to make C++ happy
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puts("\n");
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2025-08-26 04:05:40 +02:00
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puts("class " + EmitCUtil::symClassName() + ";\n");
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puts("class " + EmitCUtil::prefixNameProtect(modp) + ";\n"); // For rootp pointer only
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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if (v3Global.opt.trace()) puts("class " + v3Global.opt.traceClassLang() + ";\n");
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emitModCUse(modp, VUseType::INT_FWD_CLASS); // Note: This is needed for cell forwarding
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puts("\n");
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puts("// This class is the main interface to the Verilated model\n");
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2025-08-26 04:05:40 +02:00
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putns(modp, "class alignas(VL_CACHE_LINE_BYTES) " + EmitCUtil::topClassName()
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+ " VL_NOT_FINAL : ");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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if (optSystemC()) {
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2022-07-12 12:41:15 +02:00
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// SC_MODULE, but with multiple-inheritance of VerilatedModel
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puts("public ::sc_core::sc_module, ");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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}
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2022-07-12 12:41:15 +02:00
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puts("public VerilatedModel {\n");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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ofp()->resetPrivate();
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ofp()->putsPrivate(true); // private:
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puts("// Symbol table holding complete model state (owned by this class)\n");
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2025-08-26 04:05:40 +02:00
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puts(EmitCUtil::symClassName() + "* const vlSymsp;\n");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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puts("\n");
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ofp()->putsPrivate(false); // public:
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2024-05-04 02:18:06 +02:00
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puts("\n// CONSTEXPR CAPABILITIES\n");
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puts("// Verilated with --trace?\n");
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puts("static constexpr bool traceCapable = "s
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+ (v3Global.opt.trace() ? "true;\n"s : "false;\n"s));
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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// User accessible IO
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puts("\n// PORTS\n"
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"// The application code writes and reads these signals to\n"
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"// propagate new values into/out from the Verilated model.\n");
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for (const AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
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2021-10-22 16:15:42 +02:00
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if (const AstVar* const varp = VN_CAST(nodep, Var)) {
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (varp->isPrimaryIO()) { //
|
Add V3VariableOrder pass
A separate V3VariableOrder pass is now used to order module variables
before Emit. All variables are now ordered together, without
consideration for whether they are ports, signals form the design, or
additional internal variables added by Verilator (which used to be
ordered and emitted as separate groups in Emit). For single threaded
models, this is performance neutral. For multi-threaded models, the
MTask affinity based sorting was slightly modified, so variables with no
MTask affinity are emitted last, otherwise the MTask affinity sets are
sorted using the TSP sorter as before, but again, ports, signals, and
internal variables are not differentiated. This yields a 2%+ speedup for
the multithreaded model on OpenTitan.
2021-06-29 18:57:07 +02:00
|
|
|
emitVarDecl(varp, /* asRef: */ true);
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2024-07-06 14:13:35 +02:00
|
|
|
if (v3Global.opt.emitAccessors()) {
|
2024-07-06 14:12:53 +02:00
|
|
|
puts("\n// ACCESSORS\n"
|
|
|
|
|
"// The application code should use these methods to\n"
|
|
|
|
|
"// propagate new values into/out from the Verilated model\n"
|
|
|
|
|
"// instead of using signal variables directly.\n");
|
|
|
|
|
for (const AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
|
|
|
|
|
if (const AstVar* const varp = VN_CAST(nodep, Var)) {
|
|
|
|
|
if (varp->isPrimaryIO()) emitVarAccessors(varp);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2023-10-26 20:36:18 +02:00
|
|
|
if (optSystemC() && v3Global.usesTiming()) puts("sc_core::sc_event trigger_eval;\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
// Cells instantiated by the top level (for access to /* verilator public */)
|
|
|
|
|
puts("\n// CELLS\n"
|
|
|
|
|
"// Public to allow access to /* verilator public */ items.\n"
|
|
|
|
|
"// Otherwise the application code can consider these internals.\n");
|
|
|
|
|
for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
|
2021-10-22 16:15:42 +02:00
|
|
|
if (const AstCell* const cellp = VN_CAST(nodep, Cell)) {
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(cellp, EmitCUtil::prefixNameProtect(cellp->modp()) + "* const "
|
|
|
|
|
+ cellp->nameProtect() + ";\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// root instance pointer (for access to internals, including public_flat items).
|
|
|
|
|
puts("\n// Root instance pointer to allow access to model internals,\n"
|
|
|
|
|
"// including inlined /* verilator public_flat_* */ items.\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts(EmitCUtil::prefixNameProtect(modp) + "* const rootp;\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
puts("\n");
|
|
|
|
|
ofp()->putsPrivate(false); // public:
|
|
|
|
|
puts("// CONSTRUCTORS\n");
|
|
|
|
|
if (optSystemC()) {
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("SC_CTOR(" + EmitCUtil::topClassName() + ");\n");
|
|
|
|
|
puts("virtual ~" + EmitCUtil::topClassName() + "();\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
} else {
|
|
|
|
|
puts("/// Construct the model; called by application code\n");
|
|
|
|
|
puts("/// If contextp is null, then the model will use the default global "
|
|
|
|
|
"context\n");
|
|
|
|
|
puts("/// If name is \"\", then makes a wrapper with a\n");
|
|
|
|
|
puts("/// single model invisible with respect to DPI scope names.\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("explicit " + EmitCUtil::topClassName() + "(VerilatedContext* contextp,"
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
+ " const char* name = \"TOP\");\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("explicit " + EmitCUtil::topClassName() + "(const char* name = \"TOP\");\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("/// Destroy the model; called (often implicitly) by application code\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("virtual ~" + EmitCUtil::topClassName() + "();\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
ofp()->putsPrivate(true);
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("VL_UNCOPYABLE(" + EmitCUtil::topClassName() + "); ///< Copying not allowed\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
puts("\n");
|
|
|
|
|
ofp()->putsPrivate(false); // public:
|
|
|
|
|
puts("// API METHODS\n");
|
2021-11-26 23:55:36 +01:00
|
|
|
const string callEvalEndStep
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
= (v3Global.needTraceDumper() && !optSystemC()) ? "eval_end_step(); " : "";
|
|
|
|
|
if (optSystemC()) {
|
|
|
|
|
ofp()->putsPrivate(true); ///< eval() is invoked by our sensitive() calls.
|
|
|
|
|
}
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("/// Evaluate the model. Application must call when inputs change.\n");
|
|
|
|
|
}
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
if (optSystemC() && v3Global.usesTiming()) {
|
|
|
|
|
puts("void eval();\n");
|
|
|
|
|
puts("void eval_sens();\n");
|
|
|
|
|
} else {
|
|
|
|
|
puts("void eval() { eval_step(); " + callEvalEndStep + "}\n");
|
|
|
|
|
}
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("/// Evaluate when calling multiple units/models per time step.\n");
|
|
|
|
|
}
|
|
|
|
|
puts("void eval_step();\n");
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("/// Evaluate at end of a timestep for tracing, when using eval_step().\n");
|
|
|
|
|
puts("/// Application must call after all eval() and before time changes.\n");
|
|
|
|
|
puts("void eval_end_step()");
|
|
|
|
|
if (callEvalEndStep == "") {
|
|
|
|
|
puts(" {}\n");
|
|
|
|
|
} else {
|
|
|
|
|
puts(";\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("/// Simulation complete, run final blocks. Application "
|
|
|
|
|
"must call on completion.\n");
|
|
|
|
|
}
|
|
|
|
|
ofp()->putsPrivate(false); // public:
|
|
|
|
|
puts("void final();\n");
|
|
|
|
|
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
puts("/// Are there scheduled events to handle?\n");
|
|
|
|
|
puts("bool eventsPending();\n");
|
|
|
|
|
puts("/// Returns time at next time slot. Aborts if !eventsPending()\n");
|
|
|
|
|
puts("uint64_t nextTimeSlot();\n");
|
|
|
|
|
|
2023-09-27 03:07:43 +02:00
|
|
|
if (v3Global.opt.trace() || !optSystemC()) {
|
|
|
|
|
puts("/// Trace signals in the model; called by application code\n");
|
2024-03-30 21:00:52 +01:00
|
|
|
// Backward-compatible usage of calling trace() on the model - now part of context
|
|
|
|
|
puts("void trace(VerilatedTraceBaseC* tfp, int levels, int options = 0) {"
|
|
|
|
|
" contextp()->trace(tfp, levels, options); }\n");
|
2023-09-27 03:07:43 +02:00
|
|
|
}
|
2023-09-27 00:37:39 +02:00
|
|
|
if (v3Global.opt.trace() && optSystemC()) {
|
|
|
|
|
puts("/// SC tracing; avoid overloaded virtual function lint warning\n");
|
2023-10-26 20:36:18 +02:00
|
|
|
puts("void trace(sc_core::sc_trace_file* tfp) const override { "
|
2023-09-27 00:37:39 +02:00
|
|
|
"::sc_core::sc_module::trace(tfp); }\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("/// Retrieve name of this model instance (as passed to constructor).\n");
|
|
|
|
|
puts("const char* name() const;\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Emit DPI export dispatcher declarations
|
|
|
|
|
{
|
2021-11-27 23:07:27 +01:00
|
|
|
const CFuncVector funcps
|
|
|
|
|
= findFuncps([](const AstCFunc* nodep) { return nodep->dpiExportDispatcher(); });
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (!funcps.empty()) {
|
|
|
|
|
puts("\n/// DPI Export functions\n");
|
2021-11-27 23:07:27 +01:00
|
|
|
for (const AstCFunc* funcp : funcps) emitCFuncDecl(funcp, modp);
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (v3Global.opt.savable()) {
|
|
|
|
|
puts("\n");
|
|
|
|
|
puts("// Serialization functions\n");
|
|
|
|
|
puts("friend VerilatedSerialize& operator<<(VerilatedSerialize& os, " //
|
2025-08-26 04:05:40 +02:00
|
|
|
+ EmitCUtil::topClassName() + "& rhs);\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("friend VerilatedDeserialize& operator>>(VerilatedDeserialize& os, "
|
2025-08-26 04:05:40 +02:00
|
|
|
+ EmitCUtil::topClassName() + "& rhs);\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
|
2022-07-12 12:41:15 +02:00
|
|
|
puts("\n// Abstract methods from VerilatedModel\n");
|
2022-07-12 16:50:11 +02:00
|
|
|
puts("const char* hierName() const override final;\n");
|
|
|
|
|
puts("const char* modelName() const override final;\n");
|
|
|
|
|
puts("unsigned threads() const override final;\n");
|
2023-08-30 13:02:55 +02:00
|
|
|
puts("/// Prepare for cloning the model at the process level (e.g. fork in Linux)\n");
|
|
|
|
|
puts("/// Release necessary resources. Called before cloning.\n");
|
|
|
|
|
puts("void prepareClone() const;\n");
|
|
|
|
|
puts("/// Re-init after cloning the model at the process level (e.g. fork in Linux)\n");
|
|
|
|
|
puts("/// Re-allocate necessary resources. Called after cloning.\n");
|
|
|
|
|
puts("void atClone() const;\n");
|
2022-07-20 12:27:10 +02:00
|
|
|
if (v3Global.opt.trace()) {
|
|
|
|
|
puts("std::unique_ptr<VerilatedTraceConfig> traceConfig() const override final;\n");
|
|
|
|
|
}
|
2022-07-12 12:41:15 +02:00
|
|
|
|
2024-03-30 21:00:52 +01:00
|
|
|
ofp()->putsPrivate(true); // private:
|
|
|
|
|
puts("// Internal functions - trace registration\n");
|
|
|
|
|
puts("void traceBaseModel(VerilatedTraceBaseC* tfp, int levels, int options);\n");
|
|
|
|
|
|
2023-05-03 03:21:10 +02:00
|
|
|
puts("};\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
ofp()->putsEndGuard();
|
|
|
|
|
|
2024-10-01 03:42:36 +02:00
|
|
|
closeOutputFile();
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emitConstructorImplementation(AstNodeModule* modp) {
|
|
|
|
|
putSectionDelimiter("Constructors");
|
|
|
|
|
|
|
|
|
|
puts("\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, EmitCUtil::topClassName() + "::" + EmitCUtil::topClassName());
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (optSystemC()) {
|
2023-10-26 20:36:18 +02:00
|
|
|
puts("(sc_core::sc_module_name /* unused */)\n");
|
2022-07-12 16:38:24 +02:00
|
|
|
puts(" : VerilatedModel{*Verilated::threadContextp()}\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts(" , vlSymsp{new " + EmitCUtil::symClassName()
|
|
|
|
|
+ "(contextp(), name(), this)}\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
} else {
|
|
|
|
|
puts(+"(VerilatedContext* _vcontextp__, const char* _vcname__)\n");
|
2022-07-12 16:38:24 +02:00
|
|
|
puts(" : VerilatedModel{*_vcontextp__}\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts(" , vlSymsp{new " + EmitCUtil::symClassName()
|
|
|
|
|
+ "(contextp(), _vcname__, this)}\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Set up IO references
|
|
|
|
|
for (const AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
|
2021-10-22 16:15:42 +02:00
|
|
|
if (const AstVar* const varp = VN_CAST(nodep, Var)) {
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (varp->isPrimaryIO()) {
|
|
|
|
|
const string protName = varp->nameProtect();
|
2024-01-25 03:51:47 +01:00
|
|
|
puts(" , ");
|
|
|
|
|
putns(varp, protName + "{vlSymsp->TOP." + protName + "}\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Setup cell pointers
|
|
|
|
|
for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
|
2021-10-22 16:15:42 +02:00
|
|
|
if (const AstCell* const cellp = VN_CAST(nodep, Cell)) {
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
const string protName = cellp->nameProtect();
|
2024-01-25 03:51:47 +01:00
|
|
|
puts(" , ");
|
|
|
|
|
putns(cellp, protName + "{vlSymsp->TOP." + protName + "}\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Setup rootp root instance pointer,
|
|
|
|
|
puts(" , rootp{&(vlSymsp->TOP)}\n");
|
|
|
|
|
|
|
|
|
|
puts("{\n");
|
2022-07-12 12:41:15 +02:00
|
|
|
puts("// Register model with the context\n");
|
2022-07-12 16:38:24 +02:00
|
|
|
puts("contextp()->addModel(this);\n");
|
2024-03-30 21:00:52 +01:00
|
|
|
if (v3Global.opt.trace())
|
|
|
|
|
puts("contextp()->traceBaseModelCbAdd(\n"
|
|
|
|
|
"[this](VerilatedTraceBaseC* tfp, int levels, int options) {"
|
|
|
|
|
" traceBaseModel(tfp, levels, options); });\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
if (optSystemC()) {
|
|
|
|
|
// Create sensitivity list for when to evaluate the model.
|
2024-01-25 03:51:47 +01:00
|
|
|
putsDecoration(nullptr, "// Sensitivities on all clocks and combinational inputs\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("SC_METHOD(eval);\n");
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
if (v3Global.usesTiming()) puts("SC_METHOD(eval_sens);\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
|
|
|
|
|
if (const AstVar* const varp = VN_CAST(nodep, Var)) {
|
Deprecate clocker attribute and --clk option (#6463)
The only use for the clocker attribute and the AstVar::isUsedClock that
is actually necessary today for correctness is to mark top level inputs
of --lib-create blocks as being (or driving) a clock signal. Correctness
of --lib-create (and hence hierarchical blocks) actually used to depend
on having the right optimizations eliminate intermediate clocks (e.g.:
V3Gate), when the top level port was not used directly in a sensitivity
list, or marking top level signals manually via --clk or the clocker
attribute. However V3Sched::partition already needs to trace through the
logic to figure out what signals might drive a sensitivity list, so it
can very easily mark all top level inputs as such.
In this patch we remove the AstVar::attrClocker and AstVar::isUsedClock
attributes, and replace them with AstVar::isPrimaryClock, automatically
set by V3Sched::partition. This eliminates all need for manual
annotation so we are deprecating the --clk/--no-clk options and the
clocker/no_clocker attributes.
This also eliminates the opportunity for any further mis-optimization
similar to #6453.
Regarding the other uses of the removed AstVar attributes:
- As of 5.000, initial edges are triggered via a separate mechanism
applied in V3Sched, so the use in V3EmitCFunc.cpp is redundant
- Also as of 5.000, we can handle arbitrary sensitivity expressions, so
the restriction on eliminating clock signals in V3Gate is unnecessary
- Since the recent change when Dfg is applied after V3Scope, it does
perform the equivalent of GateClkDecomp, so we can delete that pass.
2025-09-20 16:50:22 +02:00
|
|
|
if (varp->isNonOutput() && (varp->isScSensitive() || varp->isPrimaryClock())) {
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
int vects = 0;
|
|
|
|
|
// This isn't very robust and may need cleanup for other data types
|
|
|
|
|
for (AstUnpackArrayDType* arrayp
|
|
|
|
|
= VN_CAST(varp->dtypeSkipRefp(), UnpackArrayDType);
|
|
|
|
|
arrayp;
|
|
|
|
|
arrayp = VN_CAST(arrayp->subDTypep()->skipRefp(), UnpackArrayDType)) {
|
|
|
|
|
const int vecnum = vects++;
|
|
|
|
|
UASSERT_OBJ(arrayp->hi() >= arrayp->lo(), varp,
|
|
|
|
|
"Should have swapped msb & lsb earlier.");
|
2024-01-29 02:24:28 +01:00
|
|
|
const string ivar = "__Vi"s + cvtToStr(vecnum);
|
2024-01-25 03:51:47 +01:00
|
|
|
putns(varp, "for (int __Vi" + cvtToStr(vecnum) + " = "
|
|
|
|
|
+ cvtToStr(arrayp->lo()));
|
2022-10-16 00:47:10 +02:00
|
|
|
puts("; " + ivar + " <= " + cvtToStr(arrayp->hi()));
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("; ++" + ivar + ") {\n");
|
|
|
|
|
}
|
2024-01-25 03:51:47 +01:00
|
|
|
putns(varp, "sensitive << " + varp->nameProtect());
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
for (int v = 0; v < vects; ++v) puts("[__Vi" + cvtToStr(v) + "]");
|
|
|
|
|
puts(";\n");
|
|
|
|
|
for (int v = 0; v < vects; ++v) puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
puts("\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
puts("}\n");
|
|
|
|
|
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
puts("\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts(EmitCUtil::topClassName() + "::" + EmitCUtil::topClassName()
|
|
|
|
|
+ "(const char* _vcname__)\n");
|
|
|
|
|
puts(" : " + EmitCUtil::topClassName()
|
|
|
|
|
+ "(Verilated::threadContextp(), _vcname__)\n{\n}\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emitDestructorImplementation() {
|
|
|
|
|
putSectionDelimiter("Destructor");
|
|
|
|
|
|
|
|
|
|
puts("\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts(EmitCUtil::topClassName() + "::~" + EmitCUtil::topClassName() + "() {\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("delete vlSymsp;\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
2021-09-24 04:59:36 +02:00
|
|
|
void emitStandardMethods1(AstNodeModule* modp) {
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
UASSERT_OBJ(modp->isTop(), modp, "Attempting to emitWrapEval for non-top class");
|
|
|
|
|
|
2025-08-26 04:05:40 +02:00
|
|
|
const string topModNameProtected = EmitCUtil::prefixNameProtect(modp);
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
const string selfDecl = "(" + topModNameProtected + "* vlSelf)";
|
|
|
|
|
|
2022-05-15 17:03:32 +02:00
|
|
|
putSectionDelimiter("Evaluation function");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
// Forward declarations
|
|
|
|
|
puts("\n");
|
|
|
|
|
puts("#ifdef VL_DEBUG\n");
|
|
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval_debug_assertions") + selfDecl
|
|
|
|
|
+ ";\n");
|
|
|
|
|
puts("#endif // VL_DEBUG\n");
|
2022-05-15 17:03:32 +02:00
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval_static") + selfDecl + ";\n");
|
|
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval_initial") + selfDecl + ";\n");
|
|
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval_settle") + selfDecl + ";\n");
|
|
|
|
|
puts("void " + topModNameProtected + "__" + protect("_eval") + selfDecl + ";\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
if (optSystemC() && v3Global.usesTiming()) {
|
|
|
|
|
// ::eval
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("\nvoid " + EmitCUtil::topClassName() + "::eval() {\n");
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
puts("eval_step();\n");
|
|
|
|
|
puts("if (eventsPending()) {\n");
|
2023-10-26 20:36:18 +02:00
|
|
|
puts("sc_core::sc_time dt = sc_core::sc_time::from_value(nextTimeSlot() - "
|
|
|
|
|
"contextp()->time());\n");
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
puts("next_trigger(dt, trigger_eval);\n");
|
|
|
|
|
puts("} else {\n");
|
|
|
|
|
puts("next_trigger(trigger_eval);\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
|
|
|
|
|
// ::eval_sens
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("\nvoid " + EmitCUtil::topClassName() + "::eval_sens() {\n");
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
puts("trigger_eval.notify();\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
// ::eval_step
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("\nvoid " + EmitCUtil::topClassName() + "::eval_step() {\n");
|
|
|
|
|
puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+++++TOP Evaluate " + EmitCUtil::topClassName()
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
+ "::eval_step\\n\"); );\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("#ifdef VL_DEBUG\n");
|
2024-01-25 03:51:47 +01:00
|
|
|
putsDecoration(nullptr, "// Debug assertions\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts(topModNameProtected + "__" + protect("_eval_debug_assertions")
|
|
|
|
|
+ "(&(vlSymsp->TOP));\n");
|
|
|
|
|
puts("#endif // VL_DEBUG\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
|
2022-05-15 17:03:32 +02:00
|
|
|
if (v3Global.opt.trace()) puts("vlSymsp->__Vm_activity = true;\n");
|
|
|
|
|
|
|
|
|
|
if (v3Global.hasEvents()) puts("vlSymsp->clearTriggeredEvents();\n");
|
2022-09-29 00:54:18 +02:00
|
|
|
if (v3Global.hasClasses()) puts("vlSymsp->__Vm_deleter.deleteAll();\n");
|
2022-05-15 17:03:32 +02:00
|
|
|
|
|
|
|
|
puts("if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {\n");
|
|
|
|
|
puts("vlSymsp->__Vm_didInit = true;\n");
|
|
|
|
|
puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+ Initial\\n\"););\n");
|
|
|
|
|
puts(topModNameProtected + "__" + protect("_eval_static") + "(&(vlSymsp->TOP));\n");
|
|
|
|
|
puts(topModNameProtected + "__" + protect("_eval_initial") + "(&(vlSymsp->TOP));\n");
|
|
|
|
|
puts(topModNameProtected + "__" + protect("_eval_settle") + "(&(vlSymsp->TOP));\n");
|
|
|
|
|
puts("}\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
2024-12-23 16:10:46 +01:00
|
|
|
if (v3Global.opt.profExec() && !v3Global.opt.hierChild())
|
|
|
|
|
puts("vlSymsp->__Vm_executionProfilerp->configure();\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
|
2022-05-15 17:03:32 +02:00
|
|
|
puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+ Eval\\n\"););\n");
|
|
|
|
|
puts(topModNameProtected + "__" + protect("_eval") + "(&(vlSymsp->TOP));\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
|
2024-01-25 03:51:47 +01:00
|
|
|
putsDecoration(nullptr, "// Evaluate cleanup\n");
|
2023-10-21 14:53:56 +02:00
|
|
|
puts("Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("}\n");
|
2021-09-24 04:59:36 +02:00
|
|
|
}
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
2022-05-15 17:03:32 +02:00
|
|
|
void emitStandardMethods2(AstNodeModule* modp) {
|
2025-08-26 04:05:40 +02:00
|
|
|
const string topModNameProtected = EmitCUtil::prefixNameProtect(modp);
|
2022-05-15 17:03:32 +02:00
|
|
|
const string selfDecl = "(" + topModNameProtected + "* vlSelf)";
|
|
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
// ::eval_end_step
|
|
|
|
|
if (v3Global.needTraceDumper() && !optSystemC()) {
|
2024-01-25 03:51:47 +01:00
|
|
|
puts("\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "void " + EmitCUtil::topClassName() + "::eval_end_step() {\n");
|
|
|
|
|
puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+eval_end_step " + EmitCUtil::topClassName()
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
+ "::eval_end_step\\n\"); );\n");
|
|
|
|
|
puts("#ifdef VM_TRACE\n");
|
2024-01-25 03:51:47 +01:00
|
|
|
putsDecoration(nullptr, "// Tracing\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
// SystemC's eval loop deals with calling trace, not us
|
|
|
|
|
puts("if (VL_UNLIKELY(vlSymsp->__Vm_dumping)) vlSymsp->_traceDump();\n");
|
|
|
|
|
puts("#endif // VM_TRACE\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
2022-10-06 00:16:05 +02:00
|
|
|
putSectionDelimiter("Events and timing");
|
|
|
|
|
if (auto* const delaySchedp = v3Global.rootp()->delaySchedulerp()) {
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "bool " + EmitCUtil::topClassName()
|
|
|
|
|
+ "::eventsPending() { return !vlSymsp->TOP.");
|
2022-10-06 00:16:05 +02:00
|
|
|
puts(delaySchedp->nameProtect());
|
|
|
|
|
puts(".empty(); }\n\n");
|
2024-01-25 03:51:47 +01:00
|
|
|
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "uint64_t " + EmitCUtil::topClassName()
|
|
|
|
|
+ "::nextTimeSlot() { return vlSymsp->TOP.");
|
2022-10-06 00:16:05 +02:00
|
|
|
puts(delaySchedp->nameProtect());
|
|
|
|
|
puts(".nextTimeSlot(); }\n");
|
|
|
|
|
} else {
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp,
|
|
|
|
|
"bool " + EmitCUtil::topClassName() + "::eventsPending() { return false; }\n\n");
|
|
|
|
|
puts("uint64_t " + EmitCUtil::topClassName() + "::nextTimeSlot() {\n");
|
2024-12-11 14:52:41 +01:00
|
|
|
puts("VL_FATAL_MT(__FILE__, __LINE__, \"\", \"No delays in the design\");\n");
|
2022-10-06 00:16:05 +02:00
|
|
|
puts("return 0;\n}\n");
|
Timing support (#3363)
Adds timing support to Verilator. It makes it possible to use delays,
event controls within processes (not just at the start), wait
statements, and forks.
Building a design with those constructs requires a compiler that
supports C++20 coroutines (GCC 10, Clang 5).
The basic idea is to have processes and tasks with delays/event controls
implemented as C++20 coroutines. This allows us to suspend and resume
them at any time.
There are five main runtime classes responsible for managing suspended
coroutines:
* `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle`
with move semantics and automatic cleanup.
* `VlDelayScheduler`, for coroutines suspended by delays. It resumes
them at a proper simulation time.
* `VlTriggerScheduler`, for coroutines suspended by event controls. It
resumes them if its corresponding trigger was set.
* `VlForkSync`, used for syncing `fork..join` and `fork..join_any`
blocks.
* `VlCoroutine`, the return type of all verilated coroutines. It allows
for suspending a stack of coroutines (normally, C++ coroutines are
stackless).
There is a new visitor in `V3Timing.cpp` which:
* scales delays according to the timescale,
* simplifies intra-assignment timing controls and net delays into
regular timing controls and assignments,
* simplifies wait statements into loops with event controls,
* marks processes and tasks with timing controls in them as
suspendable,
* creates delay, trigger scheduler, and fork sync variables,
* transforms timing controls and fork joins into C++ awaits
There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`)
that integrate static scheduling with timing. This involves providing
external domains for variables, so that the necessary combinational
logic gets triggered after coroutine resumption, as well as statements
that need to be injected into the design eval function to perform this
resumption at the correct time.
There is also a function that transforms forked processes into separate
functions.
See the comments in `verilated_timing.h`, `verilated_timing.cpp`,
`V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals
documentation for more details.
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
|
|
|
}
|
|
|
|
|
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
putSectionDelimiter("Utilities");
|
|
|
|
|
|
|
|
|
|
if (!optSystemC()) {
|
|
|
|
|
// ::name
|
2024-01-25 03:51:47 +01:00
|
|
|
puts("\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "const char* " + EmitCUtil::topClassName() + "::name() const {\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts(/**/ "return vlSymsp->name();\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
}
|
2021-11-14 17:05:20 +01:00
|
|
|
|
|
|
|
|
putSectionDelimiter("Invoke final blocks");
|
2022-05-15 17:03:32 +02:00
|
|
|
// Forward declarations
|
|
|
|
|
puts("\n");
|
2024-01-25 03:51:47 +01:00
|
|
|
putns(modp,
|
|
|
|
|
"void " + topModNameProtected + "__" + protect("_eval_final") + selfDecl + ";\n");
|
2021-11-14 17:05:20 +01:00
|
|
|
// ::final
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("\nVL_ATTR_COLD void " + EmitCUtil::topClassName() + "::final() {\n");
|
2022-05-15 17:03:32 +02:00
|
|
|
puts(/**/ topModNameProtected + "__" + protect("_eval_final") + "(&(vlSymsp->TOP));\n");
|
2021-11-14 17:05:20 +01:00
|
|
|
puts("}\n");
|
2022-07-12 12:41:15 +02:00
|
|
|
|
|
|
|
|
putSectionDelimiter("Implementations of abstract methods from VerilatedModel\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "const char* " + EmitCUtil::topClassName()
|
2024-01-25 03:51:47 +01:00
|
|
|
+ "::hierName() const { return vlSymsp->name(); }\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "const char* " + EmitCUtil::topClassName() + "::modelName() const { return \""
|
|
|
|
|
+ EmitCUtil::topClassName() + "\"; }\n");
|
2025-05-26 15:37:35 +02:00
|
|
|
const int threads = v3Global.opt.hierChild()
|
|
|
|
|
? v3Global.opt.threads()
|
|
|
|
|
: std::max(v3Global.opt.threads(), v3Global.opt.hierThreads());
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "unsigned " + EmitCUtil::topClassName() + "::threads() const { return "
|
2025-05-26 15:37:35 +02:00
|
|
|
+ cvtToStr(threads) + "; }\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "void " + EmitCUtil::topClassName()
|
2024-01-25 03:51:47 +01:00
|
|
|
+ "::prepareClone() const { contextp()->prepareClone(); }\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "void " + EmitCUtil::topClassName() + "::atClone() const {\n");
|
2023-08-30 13:02:55 +02:00
|
|
|
if (v3Global.opt.threads() > 1) {
|
|
|
|
|
puts("vlSymsp->__Vm_threadPoolp = static_cast<VlThreadPool*>(");
|
|
|
|
|
}
|
|
|
|
|
puts("contextp()->threadPoolpOnClone()");
|
|
|
|
|
if (v3Global.opt.threads() > 1) puts(")");
|
|
|
|
|
puts(";\n}\n");
|
2022-07-20 12:27:10 +02:00
|
|
|
|
|
|
|
|
if (v3Global.opt.trace()) {
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "std::unique_ptr<VerilatedTraceConfig> " + EmitCUtil::topClassName()
|
2024-01-25 03:51:47 +01:00
|
|
|
+ "::traceConfig() const {\n");
|
2022-07-20 12:27:10 +02:00
|
|
|
puts("return std::unique_ptr<VerilatedTraceConfig>{new VerilatedTraceConfig{");
|
|
|
|
|
puts(v3Global.opt.useTraceParallel() ? "true" : "false");
|
|
|
|
|
puts(v3Global.opt.useTraceOffload() ? ", true" : ", false");
|
|
|
|
|
puts(v3Global.opt.useFstWriterThread() ? ", true" : ", false");
|
|
|
|
|
puts("}};\n");
|
|
|
|
|
puts("};\n");
|
|
|
|
|
}
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emitTraceMethods(AstNodeModule* modp) {
|
2025-08-26 04:05:40 +02:00
|
|
|
const string topModNameProtected = EmitCUtil::prefixNameProtect(modp);
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
putSectionDelimiter("Trace configuration");
|
|
|
|
|
|
|
|
|
|
// Forward declaration
|
2024-01-25 03:51:47 +01:00
|
|
|
putns(modp, "\nvoid " + topModNameProtected + "__" + protect("trace_decl_types") + "("
|
|
|
|
|
+ v3Global.opt.traceClassBase() + "* tracep);\n");
|
|
|
|
|
putns(modp, "\nvoid " + topModNameProtected + "__" + protect("trace_init_top") + "("
|
|
|
|
|
+ topModNameProtected + "* vlSelf, " + v3Global.opt.traceClassBase()
|
|
|
|
|
+ "* tracep);\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
// Static helper function
|
2024-01-25 03:51:47 +01:00
|
|
|
puts("\n");
|
|
|
|
|
putns(modp, "VL_ATTR_COLD static void " + protect("trace_init") + "(void* voidSelf, "
|
|
|
|
|
+ v3Global.opt.traceClassBase() + "* tracep, uint32_t code) {\n");
|
|
|
|
|
putsDecoration(modp, "// Callback from tracep->open()\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts(EmitCUtil::voidSelfAssign(modp));
|
|
|
|
|
puts(EmitCUtil::symClassAssign());
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("if (!vlSymsp->_vm_contextp__->calcUnusedSigs()) {\n");
|
|
|
|
|
puts("VL_FATAL_MT(__FILE__, __LINE__, __FILE__,\n");
|
|
|
|
|
puts("\"Turning on wave traces requires Verilated::traceEverOn(true) call before time "
|
|
|
|
|
"0.\");\n");
|
|
|
|
|
puts("}\n");
|
|
|
|
|
puts("vlSymsp->__Vm_baseCode = code;\n");
|
2024-09-21 14:25:14 +02:00
|
|
|
puts("tracep->pushPrefix(std::string{vlSymsp->name()}, "
|
2023-10-24 17:33:29 +02:00
|
|
|
"VerilatedTracePrefixType::SCOPE_MODULE);\n");
|
2023-12-19 17:07:06 +01:00
|
|
|
puts(topModNameProtected + "__" + protect("trace_decl_types") + "(tracep);\n");
|
2021-06-22 14:16:23 +02:00
|
|
|
puts(topModNameProtected + "__" + protect("trace_init_top") + "(vlSelf, tracep);\n");
|
2024-09-21 14:25:14 +02:00
|
|
|
puts("tracep->popPrefix();\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("}\n");
|
|
|
|
|
|
|
|
|
|
// Forward declaration
|
2024-01-25 03:51:47 +01:00
|
|
|
puts("\n");
|
|
|
|
|
putns(modp, "VL_ATTR_COLD void " + topModNameProtected + "__" + protect("trace_register")
|
|
|
|
|
+ "(" + topModNameProtected + "* vlSelf, " + v3Global.opt.traceClassBase()
|
|
|
|
|
+ "* tracep);\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
2024-03-30 21:00:52 +01:00
|
|
|
// ::traceRegisterModel
|
2024-01-25 03:51:47 +01:00
|
|
|
puts("\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
putns(modp, "VL_ATTR_COLD void " + EmitCUtil::topClassName() + "::traceBaseModel(");
|
2024-03-30 21:00:52 +01:00
|
|
|
puts("VerilatedTraceBaseC* tfp, int levels, int options) {\n");
|
2021-12-23 00:41:11 +01:00
|
|
|
if (optSystemC()) {
|
|
|
|
|
puts(/**/ "if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) {\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts(/****/ "vl_fatal(__FILE__, __LINE__, name(), \"" + EmitCUtil::topClassName()
|
2021-12-23 00:41:11 +01:00
|
|
|
+ +"::trace() is called before sc_core::sc_start(). "
|
|
|
|
|
"Run sc_core::sc_start(sc_core::SC_ZERO_TIME) before trace() to complete "
|
|
|
|
|
"elaboration.\");\n");
|
|
|
|
|
puts(/**/ "}");
|
|
|
|
|
}
|
2024-03-30 21:00:52 +01:00
|
|
|
puts(/**/ "(void)levels; (void)options;\n"); // Prevent unused variable warning
|
|
|
|
|
puts(/**/ v3Global.opt.traceClassBase() + "C* const stfp = dynamic_cast<"
|
|
|
|
|
+ v3Global.opt.traceClassBase() + "C*>(tfp);\n");
|
|
|
|
|
puts(/**/ "if (VL_UNLIKELY(!stfp)) {\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts(/****/ "vl_fatal(__FILE__, __LINE__, __FILE__,\"'" + EmitCUtil::topClassName()
|
2024-03-30 21:00:52 +01:00
|
|
|
+ "::trace()' called on non-" + v3Global.opt.traceClassBase() + "C object;\"\n"
|
|
|
|
|
+ "\" use --trace-fst with VerilatedFst object,"
|
2025-04-05 16:46:39 +02:00
|
|
|
+ " and --trace-vcd with VerilatedVcd object\");\n");
|
2022-09-20 22:45:09 +02:00
|
|
|
puts(/**/ "}\n");
|
2024-03-30 21:00:52 +01:00
|
|
|
puts(/**/ "stfp->spTrace()->addModel(this);\n");
|
|
|
|
|
puts(/**/ "stfp->spTrace()->addInitCb(&" + protect("trace_init")
|
|
|
|
|
+ ", &(vlSymsp->TOP));\n");
|
2021-11-14 18:01:02 +01:00
|
|
|
puts(/**/ topModNameProtected + "__" + protect("trace_register")
|
2024-03-30 21:00:52 +01:00
|
|
|
+ "(&(vlSymsp->TOP), stfp->spTrace());\n");
|
2023-09-27 00:37:39 +02:00
|
|
|
puts("}\n");
|
|
|
|
|
}
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
void emitSerializationFunctions() {
|
|
|
|
|
putSectionDelimiter("Model serialization");
|
|
|
|
|
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("\nVerilatedSerialize& operator<<(VerilatedSerialize& os, "
|
|
|
|
|
+ EmitCUtil::topClassName() + "& rhs) {\n");
|
2021-11-14 18:01:02 +01:00
|
|
|
puts(/**/ "Verilated::quiesce();\n");
|
|
|
|
|
puts(/**/ "rhs.vlSymsp->" + protect("__Vserialize") + "(os);\n");
|
|
|
|
|
puts(/**/ "return os;\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("}\n");
|
|
|
|
|
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("\nVerilatedDeserialize& operator>>(VerilatedDeserialize& os, "
|
|
|
|
|
+ EmitCUtil::topClassName() + "& rhs) {\n");
|
2021-11-14 18:01:02 +01:00
|
|
|
puts(/**/ "Verilated::quiesce();\n");
|
|
|
|
|
puts(/**/ "rhs.vlSymsp->" + protect("__Vdeserialize") + "(os);\n");
|
|
|
|
|
puts(/**/ "return os;\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
puts("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emitImplementation(AstNodeModule* modp) {
|
2024-10-01 03:42:36 +02:00
|
|
|
UASSERT(!ofp(), "Output file should not be open");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
2025-08-26 04:05:40 +02:00
|
|
|
const string filename = v3Global.opt.makeDir() + "/" + EmitCUtil::topClassName() + ".cpp";
|
2024-10-01 03:42:36 +02:00
|
|
|
setOutputFile(v3Global.opt.systemC() ? new V3OutScFile{filename}
|
|
|
|
|
: new V3OutCFile{filename},
|
|
|
|
|
newCFile(filename, /* slow: */ false, /* source: */ true));
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
|
|
|
|
ofp()->putsHeader();
|
|
|
|
|
puts("// DESCRIPTION: Verilator output: "
|
|
|
|
|
"Model implementation (design independent parts)\n");
|
|
|
|
|
|
|
|
|
|
puts("\n");
|
2025-08-26 04:05:40 +02:00
|
|
|
puts("#include \"" + EmitCUtil::pchClassName() + ".h\"\n");
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
if (v3Global.opt.trace()) {
|
|
|
|
|
puts("#include \"" + v3Global.opt.traceSourceLang() + ".h\"\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
emitConstructorImplementation(modp);
|
|
|
|
|
emitDestructorImplementation();
|
2021-09-24 04:59:36 +02:00
|
|
|
emitStandardMethods1(modp);
|
|
|
|
|
emitStandardMethods2(modp);
|
2024-03-30 21:00:52 +01:00
|
|
|
if (v3Global.opt.trace()) emitTraceMethods(modp);
|
2023-09-27 00:37:39 +02:00
|
|
|
if (v3Global.opt.savable()) emitSerializationFunctions();
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
|
|
|
|
2024-10-01 03:42:36 +02:00
|
|
|
closeOutputFile();
|
Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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}
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void emitDpiExportDispatchers(AstNodeModule* modp) {
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2024-10-01 03:42:36 +02:00
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UASSERT(!ofp(), "Output file should not be open");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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// Emit DPI Export dispatchers
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for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) {
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AstCFunc* const funcp = VN_CAST(nodep, CFunc);
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if (!funcp || !funcp->dpiExportDispatcher()) continue;
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if (splitNeeded()) {
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// Splitting file, so using parallel build.
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v3Global.useParallelBuild(true);
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// Close old file
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2024-10-01 03:42:36 +02:00
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closeOutputFile();
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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}
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2024-10-01 03:42:36 +02:00
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if (!ofp()) {
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2025-08-26 04:05:40 +02:00
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string filename
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= v3Global.opt.makeDir() + "/" + EmitCUtil::topClassName() + "__Dpi_Export";
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2021-07-14 23:37:37 +02:00
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filename = m_uniqueNames.get(filename);
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filename += ".cpp";
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2024-10-01 03:42:36 +02:00
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setOutputFile(v3Global.opt.systemC() ? new V3OutScFile{filename}
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: new V3OutCFile{filename},
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newCFile(filename, /* slow: */ false, /* source: */ true));
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2021-07-14 23:37:37 +02:00
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splitSizeReset(); // Reset file size tracking
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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m_lazyDecls.reset();
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2024-10-01 03:42:36 +02:00
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ofp()->putsHeader();
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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puts(
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"// DESCRIPTION: Verilator output: Implementation of DPI export functions.\n");
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puts("//\n");
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2025-08-26 04:05:40 +02:00
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puts("#include \"" + EmitCUtil::topClassName() + ".h\"\n");
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puts("#include \"" + EmitCUtil::symClassName() + ".h\"\n");
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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puts("#include \"verilated_dpi.h\"\n");
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puts("\n");
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}
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2023-03-18 17:17:25 +01:00
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iterateConst(funcp);
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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}
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2024-10-01 03:42:36 +02:00
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if (ofp()) closeOutputFile();
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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}
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void main(AstNodeModule* modp) {
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m_modp = modp;
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emitHeader(modp);
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emitImplementation(modp);
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2024-03-27 22:57:49 +01:00
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if (v3Global.dpi()) emitDpiExportDispatchers(modp);
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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}
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// VISITORS
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public:
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2025-08-21 10:43:37 +02:00
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explicit EmitCModel(AstNodeModule* topModulep) { main(topModulep); }
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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};
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//######################################################################
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// EmitC class functions
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void V3EmitC::emitcModel() {
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2025-05-23 02:29:32 +02:00
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UINFO(2, __FUNCTION__ << ":");
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2025-08-21 10:43:37 +02:00
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{ EmitCModel{v3Global.rootp()->topModulep()}; }
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 16:30:20 +02:00
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}
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