luke
/
verilator
mirror of https://github.com/verilator/verilator.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
verilator/test_regress/t/t_xml_debugcheck.out

1857 lines
100 KiB
Plaintext
Raw Normal View History

Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
Support 1800-2023 keywords.
2024-03-02 15:01:37 +01:00
<file id="a" filename="&lt;built-in&gt;" language="1800-2023"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2023"/>
<file id="c" filename="input.vc" language="1800-2023"/>
<file id="d" filename="t/t_enum_type_methods.v" language="1800-2023"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</files>
<module_files>
Support 1800-2023 keywords.
2024-03-02 15:01:37 +01:00
<file id="d" filename="t/t_enum_type_methods.v" language="1800-2023"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</module_files>
<cells>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<cell loc="d,11,8,11,9" name="$root" submodname="$root" hier="$root">
Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
2022-01-17 22:22:07 +01:00
<cell loc="a,0,0,0,0" name="__PVT____024unit" submodname="__024unit" hier="$root.__PVT____024unit"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</cell>
</cells>
<cells>
Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
2022-01-17 22:22:07 +01:00
<cell loc="a,0,0,0,0" name="$unit" submodname="$unit" hier="$unit"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</cells>
<netlist>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<module loc="d,11,8,11,9" name="$root" origName="$root" topModule="1" public="true">
Deprecate clocker attribute and --clk option (#6463) The only use for the clocker attribute and the AstVar::isUsedClock that is actually necessary today for correctness is to mark top level inputs of --lib-create blocks as being (or driving) a clock signal. Correctness of --lib-create (and hence hierarchical blocks) actually used to depend on having the right optimizations eliminate intermediate clocks (e.g.: V3Gate), when the top level port was not used directly in a sensitivity list, or marking top level signals manually via --clk or the clocker attribute. However V3Sched::partition already needs to trace through the logic to figure out what signals might drive a sensitivity list, so it can very easily mark all top level inputs as such. In this patch we remove the AstVar::attrClocker and AstVar::isUsedClock attributes, and replace them with AstVar::isPrimaryClock, automatically set by V3Sched::partition. This eliminates all need for manual annotation so we are deprecating the --clk/--no-clk options and the clocker/no_clocker attributes. This also eliminates the opportunity for any further mis-optimization similar to #6453. Regarding the other uses of the removed AstVar attributes: - As of 5.000, initial edges are triggered via a separate mechanism applied in V3Sched, so the use in V3EmitCFunc.cpp is redundant - Also as of 5.000, we can handle arbitrary sensitivity expressions, so the restriction on eliminating clock signals in V3Gate is unnecessary - Since the recent change when Dfg is applied after V3Scope, it does perform the equivalent of GateClkDecomp, so we can delete that pass.
2025-09-20 16:50:22 +02:00
<var loc="d,15,10,15,13" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk" public="true"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<var loc="d,24,9,24,10" name="t.e" dtype_id="2" vartype="my_t" origName="e"/>
<var loc="d,11,8,11,9" name="__Vtrigprevexpr___TOP__clk__0" dtype_id="1" vartype="logic" origName="__Vtrigprevexpr___TOP__clk__0"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<var loc="d,23,17,23,20" name="t.cyc" dtype_id="3" vartype="integer" origName="cyc"/>
<var loc="d,11,8,11,9" name="__VactIterCount" dtype_id="4" vartype="bit" origName="__VactIterCount"/>
<var loc="d,11,8,11,9" name="__VactTriggered" dtype_id="5" vartype="" origName="__VactTriggered"/>
<var loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="5" vartype="" origName="__VnbaTriggered"/>
Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
2022-01-17 22:22:07 +01:00
<instance loc="a,0,0,0,0" name="$unit" defName="__024unit" origName="__024unit"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<topscope loc="d,11,8,11,9">
<scope loc="d,11,8,11,9" name="TOP"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</topscope>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
<cfunc loc="a,0,0,0,0" name="_eval_static">
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<stmtexpr loc="d,11,8,11,9">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<ccall loc="d,11,8,11,9" dtype_id="6" func="_eval_static__TOP"/>
Make all expressions derive from AstNodeExpr (#3721). Apart from the representational changes below, this patch renames AstNodeMath to AstNodeExpr, and AstCMath to AstCExpr. Now every expression (i.e.: those AstNodes that represent a [possibly void] value, with value being interpreted in a very general sense) has AstNodeExpr as a super class. This necessitates the introduction of an AstStmtExpr, which represents an expression in statement position, e.g : 'foo();' would be represented as AstStmtExpr(AstCCall(foo)). In exchange we can get rid of isStatement() in AstNodeStmt, which now really always represent a statement Peak memory consumption and verilation speed are not measurably changed. Partial step towards #3420
2022-10-12 11:19:21 +02:00
</stmtexpr>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,63,22,63,25" dtype_id="7">
<varref loc="d,63,22,63,25" name="clk" dtype_id="7"/>
<varref loc="d,63,22,63,25" name="__Vtrigprevexpr___TOP__clk__0" dtype_id="7"/>
Fix change detection at time 0 (#5864) Initialize "previous value" variables in the static initializer function, instead of the 'initial' blocks function. Fixes #5499
2025-03-18 14:34:04 +01:00
</assign>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</cfunc>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<cfunc loc="d,11,8,11,9" name="_eval_static__TOP">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,23,23,23,24" dtype_id="3">
<const loc="d,23,23,23,24" name="32&apos;sh0" dtype_id="8"/>
<varref loc="d,23,23,23,24" name="t.cyc" dtype_id="3"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assign>
</cfunc>
<cfunc loc="a,0,0,0,0" name="_eval_initial">
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<stmtexpr loc="d,11,8,11,9">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<ccall loc="d,11,8,11,9" dtype_id="6" func="_eval_initial__TOP"/>
Make all expressions derive from AstNodeExpr (#3721). Apart from the representational changes below, this patch renames AstNodeMath to AstNodeExpr, and AstCMath to AstCExpr. Now every expression (i.e.: those AstNodes that represent a [possibly void] value, with value being interpreted in a very general sense) has AstNodeExpr as a super class. This necessitates the introduction of an AstStmtExpr, which represents an expression in statement position, e.g : 'foo();' would be represented as AstStmtExpr(AstCCall(foo)). In exchange we can get rid of isStatement() in AstNodeStmt, which now really always represent a statement Peak memory consumption and verilation speed are not measurably changed. Partial step towards #3420
2022-10-12 11:19:21 +02:00
</stmtexpr>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</cfunc>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<cfunc loc="d,11,8,11,9" name="_eval_initial__TOP">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<var loc="d,49,120,49,121" name="__Vtemp_1" dtype_id="9" vartype="string" origName="__Vtemp_1"/>
<assign loc="d,32,9,32,10" dtype_id="10">
<const loc="d,32,11,32,14" name="4&apos;h3" dtype_id="10"/>
<varref loc="d,32,7,32,8" name="t.e" dtype_id="10"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assign>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<if loc="d,38,10,38,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,38,26,38,29" dtype_id="7">
<const loc="d,38,31,38,34" name="4&apos;h4" dtype_id="10"/>
<arraysel loc="d,38,15,38,16" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,38,15,38,16" dtype_id="12">
<const loc="d,38,15,38,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,38,15,38,16" dtype_id="12">
<varref loc="d,38,15,38,16" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</neq>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
<begin>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<display loc="d,38,43,38,49" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,38,43,38,49" name="%%Error: t/t_enum_type_methods.v:38: got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
<arraysel loc="d,38,122,38,123" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,38,122,38,123" dtype_id="12">
<const loc="d,38,122,38,123" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,38,122,38,123" dtype_id="12">
<varref loc="d,38,122,38,123" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</sformatf>
</display>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<stop loc="d,38,142,38,147"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
<if loc="d,39,10,39,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,39,34,39,37" dtype_id="7">
<const loc="d,39,39,39,42" name="4&apos;h1" dtype_id="10"/>
<arraysel loc="d,39,15,39,16" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,39,15,39,16" dtype_id="12">
<const loc="d,39,15,39,16" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,39,15,39,16" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,39,15,39,16" dtype_id="12">
<const loc="d,39,15,39,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,39,15,39,16" dtype_id="12">
<varref loc="d,39,15,39,16" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
</neq>
<begin>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<display loc="d,39,51,39,57" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,39,51,39,57" name="%%Error: t/t_enum_type_methods.v:39: got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
<arraysel loc="d,39,130,39,131" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,39,130,39,131" dtype_id="12">
<const loc="d,39,130,39,131" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,39,130,39,131" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,39,130,39,131" dtype_id="12">
<const loc="d,39,130,39,131" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,39,130,39,131" dtype_id="12">
<varref loc="d,39,130,39,131" name="t.e" dtype_id="12"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</ccast>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</sformatf>
</display>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<stop loc="d,39,158,39,163"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
<if loc="d,40,10,40,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,40,26,40,29" dtype_id="7">
<const loc="d,40,31,40,34" name="4&apos;h1" dtype_id="10"/>
<arraysel loc="d,40,15,40,16" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,40,15,40,16" dtype_id="12">
<const loc="d,40,15,40,16" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,40,15,40,16" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,40,15,40,16" dtype_id="12">
<const loc="d,40,15,40,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,40,15,40,16" dtype_id="12">
<varref loc="d,40,15,40,16" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</and>
</arraysel>
</neq>
<begin>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<display loc="d,40,43,40,49" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,40,43,40,49" name="%%Error: t/t_enum_type_methods.v:40: got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
<arraysel loc="d,40,122,40,123" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,40,122,40,123" dtype_id="12">
<const loc="d,40,122,40,123" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,40,122,40,123" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,40,122,40,123" dtype_id="12">
<const loc="d,40,122,40,123" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,40,122,40,123" dtype_id="12">
<varref loc="d,40,122,40,123" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</sformatf>
</display>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<stop loc="d,40,142,40,147"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
<if loc="d,41,10,41,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,41,42,41,45" dtype_id="7">
<const loc="d,41,47,41,50" name="4&apos;h3" dtype_id="10"/>
<arraysel loc="d,41,15,41,16" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,41,15,41,16" dtype_id="12">
<const loc="d,41,15,41,16" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,41,15,41,16" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,41,15,41,16" dtype_id="12">
<const loc="d,41,15,41,16" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,41,15,41,16" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,41,15,41,16" dtype_id="12">
<const loc="d,41,15,41,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,41,15,41,16" dtype_id="12">
<varref loc="d,41,15,41,16" name="t.e" dtype_id="12"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</ccast>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</and>
</arraysel>
</neq>
<begin>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<display loc="d,41,59,41,65" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,41,59,41,65" name="%%Error: t/t_enum_type_methods.v:41: got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
<arraysel loc="d,41,138,41,139" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,41,138,41,139" dtype_id="12">
<const loc="d,41,138,41,139" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,41,138,41,139" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,41,138,41,139" dtype_id="12">
<const loc="d,41,138,41,139" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,41,138,41,139" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,41,138,41,139" dtype_id="12">
<const loc="d,41,138,41,139" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,41,138,41,139" dtype_id="12">
<varref loc="d,41,138,41,139" name="t.e" dtype_id="12"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</ccast>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</and>
</arraysel>
</sformatf>
</display>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<stop loc="d,41,174,41,179"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
<if loc="d,42,10,42,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,42,34,42,37" dtype_id="7">
<const loc="d,42,39,42,42" name="4&apos;h3" dtype_id="10"/>
<arraysel loc="d,42,15,42,16" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,42,15,42,16" dtype_id="12">
<const loc="d,42,15,42,16" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,42,15,42,16" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,42,15,42,16" dtype_id="12">
<const loc="d,42,15,42,16" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,42,15,42,16" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,42,15,42,16" dtype_id="12">
<const loc="d,42,15,42,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,42,15,42,16" dtype_id="12">
<varref loc="d,42,15,42,16" name="t.e" dtype_id="12"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</ccast>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</and>
</arraysel>
</neq>
<begin>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<display loc="d,42,51,42,57" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,42,51,42,57" name="%%Error: t/t_enum_type_methods.v:42: got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
<arraysel loc="d,42,130,42,131" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,42,130,42,131" dtype_id="12">
<const loc="d,42,130,42,131" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,42,130,42,131" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,42,130,42,131" dtype_id="12">
<const loc="d,42,130,42,131" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,42,130,42,131" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,42,130,42,131" dtype_id="12">
<const loc="d,42,130,42,131" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,42,130,42,131" dtype_id="12">
<varref loc="d,42,130,42,131" name="t.e" dtype_id="12"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</sformatf>
</display>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<stop loc="d,42,158,42,163"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</begin>
</if>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
<if loc="d,43,10,43,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,43,30,43,33" dtype_id="7">
<const loc="d,43,35,43,38" name="4&apos;h3" dtype_id="10"/>
<arraysel loc="d,43,15,43,16" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,43,15,43,16" dtype_id="12">
<const loc="d,43,15,43,16" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,43,15,43,16" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,43,15,43,16" dtype_id="12">
<const loc="d,43,15,43,16" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,43,15,43,16" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,43,15,43,16" dtype_id="12">
<const loc="d,43,15,43,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,43,15,43,16" dtype_id="12">
<varref loc="d,43,15,43,16" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,43,47,43,53" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,43,47,43,53" name="%%Error: t/t_enum_type_methods.v:43: got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
<arraysel loc="d,43,126,43,127" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,43,126,43,127" dtype_id="12">
<const loc="d,43,126,43,127" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,43,126,43,127" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,43,126,43,127" dtype_id="12">
<const loc="d,43,126,43,127" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,43,126,43,127" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,43,126,43,127" dtype_id="12">
<const loc="d,43,126,43,127" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,43,126,43,127" dtype_id="12">
<varref loc="d,43,126,43,127" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,43,150,43,155"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</begin>
</if>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
<if loc="d,44,10,44,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,44,23,44,26" dtype_id="7">
<const loc="d,44,28,44,31" name="4&apos;h1" dtype_id="10"/>
<arraysel loc="d,44,15,44,16" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,44,15,44,16" dtype_id="12">
<const loc="d,44,15,44,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,44,15,44,16" dtype_id="12">
<varref loc="d,44,15,44,16" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
</neq>
<begin>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<display loc="d,44,40,44,46" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,44,40,44,46" name="%%Error: t/t_enum_type_methods.v:44: got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
<arraysel loc="d,44,119,44,120" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,44,119,44,120" dtype_id="12">
<const loc="d,44,119,44,120" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,44,119,44,120" dtype_id="12">
<varref loc="d,44,119,44,120" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
</sformatf>
</display>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<stop loc="d,44,136,44,141"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</begin>
</if>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
<if loc="d,45,10,45,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,45,26,45,29" dtype_id="7">
<const loc="d,45,31,45,34" name="4&apos;h1" dtype_id="10"/>
<arraysel loc="d,45,15,45,16" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,45,15,45,16" dtype_id="12">
<const loc="d,45,15,45,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,45,15,45,16" dtype_id="12">
<varref loc="d,45,15,45,16" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
</neq>
<begin>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<display loc="d,45,43,45,49" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,45,43,45,49" name="%%Error: t/t_enum_type_methods.v:45: got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
<arraysel loc="d,45,122,45,123" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,45,122,45,123" dtype_id="12">
<const loc="d,45,122,45,123" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,45,122,45,123" dtype_id="12">
<varref loc="d,45,122,45,123" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
</sformatf>
</display>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<stop loc="d,45,142,45,147"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</begin>
</if>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
<if loc="d,46,10,46,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,46,34,46,37" dtype_id="7">
<const loc="d,46,39,46,42" name="4&apos;h4" dtype_id="10"/>
<arraysel loc="d,46,15,46,16" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,46,15,46,16" dtype_id="12">
<const loc="d,46,15,46,16" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,46,15,46,16" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,46,15,46,16" dtype_id="12">
<const loc="d,46,15,46,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,46,15,46,16" dtype_id="12">
<varref loc="d,46,15,46,16" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
</and>
</arraysel>
</neq>
<begin>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<display loc="d,46,51,46,57" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,46,51,46,57" name="%%Error: t/t_enum_type_methods.v:46: got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
<arraysel loc="d,46,130,46,131" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,46,130,46,131" dtype_id="12">
<const loc="d,46,130,46,131" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,46,130,46,131" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,46,130,46,131" dtype_id="12">
<const loc="d,46,130,46,131" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,46,130,46,131" dtype_id="12">
<varref loc="d,46,130,46,131" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
</sformatf>
</display>
<stop loc="d,46,158,46,163"/>
</begin>
</if>
<if loc="d,47,10,47,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,47,26,47,29" dtype_id="7">
<const loc="d,47,31,47,34" name="4&apos;h4" dtype_id="10"/>
<arraysel loc="d,47,15,47,16" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,47,15,47,16" dtype_id="12">
<const loc="d,47,15,47,16" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,47,15,47,16" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,47,15,47,16" dtype_id="12">
<const loc="d,47,15,47,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,47,15,47,16" dtype_id="12">
<varref loc="d,47,15,47,16" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
</neq>
<begin>
<display loc="d,47,43,47,49" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,47,43,47,49" name="%%Error: t/t_enum_type_methods.v:47: got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
<arraysel loc="d,47,122,47,123" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,47,122,47,123" dtype_id="12">
<const loc="d,47,122,47,123" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,47,122,47,123" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,47,122,47,123" dtype_id="12">
<const loc="d,47,122,47,123" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,47,122,47,123" dtype_id="12">
<varref loc="d,47,122,47,123" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
</and>
</arraysel>
</sformatf>
</display>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<stop loc="d,47,142,47,147"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</begin>
</if>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<if loc="d,49,10,49,12">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neqn loc="d,49,23,49,25" dtype_id="7">
<const loc="d,49,27,49,32" name="&quot;E03&quot;" dtype_id="9"/>
<arraysel loc="d,49,15,49,16" dtype_id="9">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_name1" dtype_id="15"/>
<and loc="d,49,15,49,16" dtype_id="12">
<const loc="d,49,15,49,16" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,49,15,49,16" dtype_id="12">
<varref loc="d,49,15,49,16" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</neqn>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
<begin>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,49,120,49,121" dtype_id="9">
<arraysel loc="d,49,120,49,121" dtype_id="9">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_name1" dtype_id="15"/>
<and loc="d,49,120,49,121" dtype_id="12">
<const loc="d,49,120,49,121" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,49,120,49,121" dtype_id="12">
<varref loc="d,49,120,49,121" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,49,120,49,121" name="__Vtemp_1" dtype_id="9"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assign>
Tests: Fix string !== for other simulators.
2024-10-03 01:00:39 +02:00
<display loc="d,49,41,49,47" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,49,41,49,47" name="%%Error: t/t_enum_type_methods.v:49: got=&apos;%@&apos; exp=&apos;E03&apos;&#10;" dtype_id="9">
<varref loc="d,49,120,49,121" name="__Vtemp_1" dtype_id="9"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</sformatf>
</display>
Tests: Fix string !== for other simulators.
2024-10-03 01:00:39 +02:00
<stop loc="d,49,139,49,144"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,55,9,55,10" dtype_id="10">
<const loc="d,55,13,55,17" name="4&apos;h4" dtype_id="10"/>
<varref loc="d,55,7,55,8" name="t.e" dtype_id="10"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assign>
</cfunc>
<cfunc loc="a,0,0,0,0" name="_eval_final"/>
<cfunc loc="a,0,0,0,0" name="_eval_settle"/>
<cfunc loc="a,0,0,0,0" name="_eval_triggers__act">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,11,8,11,9" dtype_id="16">
<ccast loc="d,63,14,63,21" dtype_id="17">
<ccast loc="d,63,14,63,21" dtype_id="7">
<and loc="d,63,14,63,21" dtype_id="7">
<ccast loc="d,63,22,63,25" dtype_id="7">
<varref loc="d,63,22,63,25" name="clk" dtype_id="7"/>
Optimize trigger evaluation Pack the elements of VlTriggerVec as dense bits (instead of a 1 byte bool per bit), and check whether they are set on a word granularity. This effectively transforms conditions of the form `if (trig.at(0) | trig.at(2) | trig.at(64))` into `if (trig.word(0) & 0x5 | trig.word(1) & 0x1)`. This improves OpenTitan ST by about 1%, worth more on some other designs.
2023-04-13 14:44:54 +02:00
</ccast>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<not loc="d,63,14,63,21" dtype_id="7">
<ccast loc="d,63,14,63,21" dtype_id="7">
<varref loc="d,63,14,63,21" name="__Vtrigprevexpr___TOP__clk__0" dtype_id="7"/>
</ccast>
</not>
</and>
</ccast>
</ccast>
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="__VactTriggered" dtype_id="5"/>
<const loc="d,11,8,11,9" name="32&apos;h0" dtype_id="13"/>
</arraysel>
</assign>
<assign loc="d,63,22,63,25" dtype_id="7">
<varref loc="d,63,22,63,25" name="clk" dtype_id="7"/>
<varref loc="d,63,22,63,25" name="__Vtrigprevexpr___TOP__clk__0" dtype_id="7"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assign>
Internals: Refactor text based Ast constructs (#6280) (#6571) Remove the large variety of ways raw "text" is represented in the Ast. Particularly, the only thing that represents a string to be emitted in the output is AstText. There are 5 AstNodes that can contain AstText, and V3Emit will throw an error if an AstText is encountered anywhere else: - AstCStmt: Internally generated procedural statements involving raw text. - AstCStmtUser: This is the old AstUCStmt, renamed so it sorts next to AstCStmt, as it's largely equivalent. We should never create this internally unless used to represent user input. It is used for $c, statements in the input, and for some 'systemc_* blocks. - AstCExpr: Internally generaged expression involving raw text. - AstCExprUser: This is the old AstUCFunc, renamed so it sorts next to AstCExpr. It is largely equivalent, but also has more optimizations disabled. This should never be created internally, it is only used for $c expressions in the input. - AstTextBlock: Use by V3ProtectLib only, to generate the hierarchical wrappers. Text "tracking" for indentation is always on for AstCStmt, AstCExpr, and AstTextBlock, as these are always generated by us, and should always be well formed. Tracking is always off for AstCStmtUser and AstCExprUser, as these contain arbitrary user input that might not be safe to parse for indentation. Remove subsequently redundant AstNodeSimpleText and AstNodeText types. This patch also fixes incorrect indentation in emitted waveform tracing functions, and makes the output more readable for hier block SV stubs. With that, all raw text nodes are handled as a proper AstNodeStmt or AstNodeExpr as required for #6280.
2025-10-21 13:41:29 +02:00
<cstmt loc="d,11,8,11,9">
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<text loc="d,11,8,11,9"/>
<text loc="d,11,8,11,9"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<stmtexpr loc="d,11,8,11,9">
<ccall loc="d,11,8,11,9" dtype_id="6" func="_dump_triggers__act">
<varref loc="d,11,8,11,9" name="__VactTriggered" dtype_id="5"/>
<const loc="d,11,8,11,9" name="&quot;act&quot;" dtype_id="9"/>
</ccall>
Make all expressions derive from AstNodeExpr (#3721). Apart from the representational changes below, this patch renames AstNodeMath to AstNodeExpr, and AstCMath to AstCExpr. Now every expression (i.e.: those AstNodes that represent a [possibly void] value, with value being interpreted in a very general sense) has AstNodeExpr as a super class. This necessitates the introduction of an AstStmtExpr, which represents an expression in statement position, e.g : 'foo();' would be represented as AstStmtExpr(AstCCall(foo)). In exchange we can get rid of isStatement() in AstNodeStmt, which now really always represent a statement Peak memory consumption and verilation speed are not measurably changed. Partial step towards #3420
2022-10-12 11:19:21 +02:00
</stmtexpr>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<text loc="d,11,8,11,9"/>
<text loc="d,11,8,11,9"/>
Internals: Refactor text based Ast constructs (#6280) (#6571) Remove the large variety of ways raw "text" is represented in the Ast. Particularly, the only thing that represents a string to be emitted in the output is AstText. There are 5 AstNodes that can contain AstText, and V3Emit will throw an error if an AstText is encountered anywhere else: - AstCStmt: Internally generated procedural statements involving raw text. - AstCStmtUser: This is the old AstUCStmt, renamed so it sorts next to AstCStmt, as it's largely equivalent. We should never create this internally unless used to represent user input. It is used for $c, statements in the input, and for some 'systemc_* blocks. - AstCExpr: Internally generaged expression involving raw text. - AstCExprUser: This is the old AstUCFunc, renamed so it sorts next to AstCExpr. It is largely equivalent, but also has more optimizations disabled. This should never be created internally, it is only used for $c expressions in the input. - AstTextBlock: Use by V3ProtectLib only, to generate the hierarchical wrappers. Text "tracking" for indentation is always on for AstCStmt, AstCExpr, and AstTextBlock, as these are always generated by us, and should always be well formed. Tracking is always off for AstCStmtUser and AstCExprUser, as these contain arbitrary user input that might not be safe to parse for indentation. Remove subsequently redundant AstNodeSimpleText and AstNodeText types. This patch also fixes incorrect indentation in emitted waveform tracing functions, and makes the output more readable for hier block SV stubs. With that, all raw text nodes are handled as a proper AstNodeStmt or AstNodeExpr as required for #6280.
2025-10-21 13:41:29 +02:00
</cstmt>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</cfunc>
<cfunc loc="a,0,0,0,0" name="_dump_triggers__act">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<var loc="a,0,0,0,0" name="triggers" dtype_id="5" dir="const ref" vartype="unknown" origName="triggers"/>
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="triggers" dtype_id="5"/>
</creset>
<var loc="a,0,0,0,0" name="tag" dtype_id="9" dir="const ref" vartype="string" origName="tag"/>
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="tag" dtype_id="9"/>
</creset>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<if loc="d,11,8,11,9">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<and loc="d,11,8,11,9" dtype_id="7">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
<not loc="d,11,8,11,9" dtype_id="7">
<ccast loc="d,11,8,11,9" dtype_id="7">
<ccall loc="d,11,8,11,9" dtype_id="7" func="_trigger_anySet__act">
<varref loc="d,11,8,11,9" name="triggers" dtype_id="5"/>
</ccall>
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</not>
</and>
<begin>
Internals: Emit newlines for AstCStmt automatically. No functional change intended.
2025-09-26 14:25:47 +02:00
<cstmt loc="d,11,8,11,9">
<text loc="d,11,8,11,9"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,11,8,11,9" name="tag" dtype_id="9"/>
Internals: Refactor text based Ast constructs (#6280) (#6571) Remove the large variety of ways raw "text" is represented in the Ast. Particularly, the only thing that represents a string to be emitted in the output is AstText. There are 5 AstNodes that can contain AstText, and V3Emit will throw an error if an AstText is encountered anywhere else: - AstCStmt: Internally generated procedural statements involving raw text. - AstCStmtUser: This is the old AstUCStmt, renamed so it sorts next to AstCStmt, as it's largely equivalent. We should never create this internally unless used to represent user input. It is used for $c, statements in the input, and for some 'systemc_* blocks. - AstCExpr: Internally generaged expression involving raw text. - AstCExprUser: This is the old AstUCFunc, renamed so it sorts next to AstCExpr. It is largely equivalent, but also has more optimizations disabled. This should never be created internally, it is only used for $c expressions in the input. - AstTextBlock: Use by V3ProtectLib only, to generate the hierarchical wrappers. Text "tracking" for indentation is always on for AstCStmt, AstCExpr, and AstTextBlock, as these are always generated by us, and should always be well formed. Tracking is always off for AstCStmtUser and AstCExprUser, as these contain arbitrary user input that might not be safe to parse for indentation. Remove subsequently redundant AstNodeSimpleText and AstNodeText types. This patch also fixes incorrect indentation in emitted waveform tracing functions, and makes the output more readable for hier block SV stubs. With that, all raw text nodes are handled as a proper AstNodeStmt or AstNodeExpr as required for #6280.
2025-10-21 13:41:29 +02:00
<text loc="d,11,8,11,9"/>
</cstmt>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<if loc="d,11,8,11,9">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<and loc="d,11,8,11,9" dtype_id="7">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
<ccast loc="d,11,8,11,9" dtype_id="7">
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="triggers" dtype_id="5"/>
<const loc="d,11,8,11,9" name="32&apos;h0" dtype_id="13"/>
</arraysel>
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
<begin>
Internals: Emit newlines for AstCStmt automatically. No functional change intended.
2025-09-26 14:25:47 +02:00
<cstmt loc="d,11,8,11,9">
<text loc="d,11,8,11,9"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,11,8,11,9" name="tag" dtype_id="9"/>
Internals: Refactor text based Ast constructs (#6280) (#6571) Remove the large variety of ways raw "text" is represented in the Ast. Particularly, the only thing that represents a string to be emitted in the output is AstText. There are 5 AstNodes that can contain AstText, and V3Emit will throw an error if an AstText is encountered anywhere else: - AstCStmt: Internally generated procedural statements involving raw text. - AstCStmtUser: This is the old AstUCStmt, renamed so it sorts next to AstCStmt, as it's largely equivalent. We should never create this internally unless used to represent user input. It is used for $c, statements in the input, and for some 'systemc_* blocks. - AstCExpr: Internally generaged expression involving raw text. - AstCExprUser: This is the old AstUCFunc, renamed so it sorts next to AstCExpr. It is largely equivalent, but also has more optimizations disabled. This should never be created internally, it is only used for $c expressions in the input. - AstTextBlock: Use by V3ProtectLib only, to generate the hierarchical wrappers. Text "tracking" for indentation is always on for AstCStmt, AstCExpr, and AstTextBlock, as these are always generated by us, and should always be well formed. Tracking is always off for AstCStmtUser and AstCExprUser, as these contain arbitrary user input that might not be safe to parse for indentation. Remove subsequently redundant AstNodeSimpleText and AstNodeText types. This patch also fixes incorrect indentation in emitted waveform tracing functions, and makes the output more readable for hier block SV stubs. With that, all raw text nodes are handled as a proper AstNodeStmt or AstNodeExpr as required for #6280.
2025-10-21 13:41:29 +02:00
<text loc="d,11,8,11,9"/>
</cstmt>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
</cfunc>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<cfunc loc="a,0,0,0,0" name="_trigger_anySet__act">
<var loc="a,0,0,0,0" name="in" dtype_id="5" dir="const ref" vartype="unknown" origName="in"/>
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="in" dtype_id="5"/>
</creset>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<var loc="a,0,0,0,0" name="n" dtype_id="18" vartype="IData" origName="n"/>
<assign loc="a,0,0,0,0" dtype_id="18">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="a,0,0,0,0" name="32&apos;h0" dtype_id="13"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</assign>
<loop loc="d,11,8,11,9">
Split V3Order into further part and decouple various components (#4953) Continuing the idea of decoupling the implementations of the various algorithms. The main points: -Move the former "processDomain" stuff, dealing with assigning combinational logic into the relevant sensitivity domains into V3OrderProcessDomains.cpp -Move the parallel code construction in V3OrderParallel.cpp (Could combine this with some parts of V3Partition - those not called from V3Partition::finalize - but that's not for this patch). -Move the serial code construction into V3OrderSerial.cpp -Factored the very small common code between the parallel and serial code construction (processMoveOneLogic) into V3OrderCFuncEmitter.cpp
2024-03-09 13:43:09 +01:00
<begin>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<if loc="d,11,8,11,9">
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="in" dtype_id="5"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</arraysel>
<begin>
<creturn loc="d,11,8,11,9">
<const loc="d,11,8,11,9" name="1&apos;h1" dtype_id="7"/>
</creturn>
</begin>
</if>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<assign loc="a,0,0,0,0" dtype_id="18">
<add loc="a,0,0,0,0" dtype_id="18">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<ccast loc="a,0,0,0,0" dtype_id="13">
<const loc="a,0,0,0,0" name="32&apos;h1" dtype_id="13"/>
</ccast>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</add>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</assign>
<looptest loc="d,11,8,11,9">
<gt loc="d,11,8,11,9" dtype_id="7">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</gt>
</looptest>
Split V3Order into further part and decouple various components (#4953) Continuing the idea of decoupling the implementations of the various algorithms. The main points: -Move the former "processDomain" stuff, dealing with assigning combinational logic into the relevant sensitivity domains into V3OrderProcessDomains.cpp -Move the parallel code construction in V3OrderParallel.cpp (Could combine this with some parts of V3Partition - those not called from V3Partition::finalize - but that's not for this patch). -Move the serial code construction into V3OrderSerial.cpp -Factored the very small common code between the parallel and serial code construction (processMoveOneLogic) into V3OrderCFuncEmitter.cpp
2024-03-09 13:43:09 +01:00
</begin>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</loop>
<creturn loc="d,11,8,11,9">
<const loc="d,11,8,11,9" name="1&apos;h0" dtype_id="7"/>
</creturn>
Split V3Order into further part and decouple various components (#4953) Continuing the idea of decoupling the implementations of the various algorithms. The main points: -Move the former "processDomain" stuff, dealing with assigning combinational logic into the relevant sensitivity domains into V3OrderProcessDomains.cpp -Move the parallel code construction in V3OrderParallel.cpp (Could combine this with some parts of V3Partition - those not called from V3Partition::finalize - but that's not for this patch). -Move the serial code construction into V3OrderSerial.cpp -Factored the very small common code between the parallel and serial code construction (processMoveOneLogic) into V3OrderCFuncEmitter.cpp
2024-03-09 13:43:09 +01:00
</cfunc>
Refactor V3Delay for extensibility (#5516) * Refactor V3Delay for extensibility Introduce the concept of an "NBA Scheme", which is the lowering pattern we can use for various variables that are the targets of NBAs. E.g.: - ShadowVariable (old default scheme) - FlagShared (old array set flag scheme) - ValueQueueWhole (recent dynamic commit queue) We now analyse all AstAssignDly before making any decisions on which scheme to apply. We then choose a specific scheme for each variable that is the target of an NBA, and then all NBAs targeting that variable use the same scheme. This enables easy mix and match of schemes as needed, while remaining consistent by design after extensions. Output is perturbed due to node insertion order, but no functional or performance change is intended.
2024-10-09 11:39:40 +02:00
<cfunc loc="d,23,17,23,20" name="_nba_sequent__TOP__0">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<var loc="d,23,17,23,20" name="__Vdly__t.cyc" dtype_id="3" vartype="integer" origName="__Vdly__t__DOT__cyc"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<creset loc="d,23,17,23,20">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,23,17,23,20" name="__Vdly__t.cyc" dtype_id="3"/>
Fix initiation of function variables (#3815).
2022-12-23 16:51:52 +01:00
</creset>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<var loc="d,24,9,24,10" name="__Vdly__t.e" dtype_id="2" vartype="my_t" origName="__Vdly__t__DOT__e"/>
<creset loc="d,24,9,24,10">
<varref loc="d,24,9,24,10" name="__Vdly__t.e" dtype_id="2"/>
Fix initiation of function variables (#3815).
2022-12-23 16:51:52 +01:00
</creset>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<var loc="d,70,123,70,124" name="__Vtemp_1" dtype_id="9" vartype="string" origName="__Vtemp_1"/>
<var loc="d,80,123,80,124" name="__Vtemp_2" dtype_id="9" vartype="string" origName="__Vtemp_2"/>
<var loc="d,90,123,90,124" name="__Vtemp_3" dtype_id="9" vartype="string" origName="__Vtemp_3"/>
<assign loc="d,23,17,23,20" dtype_id="3">
<varref loc="d,23,17,23,20" name="t.cyc" dtype_id="3"/>
<varref loc="d,23,17,23,20" name="__Vdly__t.cyc" dtype_id="3"/>
Iternals: Remove AstAssignPre/AstAssignPost (#6307) Replace with AstAlwaysPre/AstAlwaysPost with AstAssign under them. Step towards #6280
2025-08-19 10:27:59 +02:00
</assign>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,24,9,24,10" dtype_id="10">
<varref loc="d,24,9,24,10" name="t.e" dtype_id="10"/>
<varref loc="d,24,9,24,10" name="__Vdly__t.e" dtype_id="10"/>
Iternals: Remove AstAssignPre/AstAssignPost (#6307) Replace with AstAlwaysPre/AstAlwaysPost with AstAssign under them. Step towards #6280
2025-08-19 10:27:59 +02:00
</assign>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assigndly loc="d,64,11,64,13" dtype_id="3">
<add loc="d,64,18,64,19" dtype_id="3">
<ccast loc="d,64,20,64,21" dtype_id="13">
<const loc="d,64,20,64,21" name="32&apos;sh1" dtype_id="8"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,64,14,64,17" name="t.cyc" dtype_id="3"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</add>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,64,7,64,10" name="__Vdly__t.cyc" dtype_id="3"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assigndly>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,65,7,65,9">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<eq loc="d,65,14,65,16" dtype_id="7">
<const loc="d,65,16,65,17" name="32&apos;sh0" dtype_id="8"/>
<varref loc="d,65,11,65,14" name="t.cyc" dtype_id="3"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</eq>
<begin>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assigndly loc="d,67,12,67,14" dtype_id="10">
<const loc="d,67,15,67,18" name="4&apos;h1" dtype_id="10"/>
<varref loc="d,67,10,67,11" name="__Vdly__t.e" dtype_id="10"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assigndly>
</begin>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,69,12,69,14">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<eq loc="d,69,19,69,21" dtype_id="7">
<const loc="d,69,21,69,22" name="32&apos;sh1" dtype_id="8"/>
<varref loc="d,69,16,69,19" name="t.cyc" dtype_id="3"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</eq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,70,13,70,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neqn loc="d,70,26,70,28" dtype_id="7">
<const loc="d,70,30,70,35" name="&quot;E01&quot;" dtype_id="9"/>
<arraysel loc="d,70,18,70,19" dtype_id="9">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_name1" dtype_id="15"/>
<and loc="d,70,18,70,19" dtype_id="12">
<const loc="d,70,18,70,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,70,18,70,19" dtype_id="12">
<varref loc="d,70,18,70,19" name="t.e" dtype_id="12"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</ccast>
</and>
</arraysel>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</neqn>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
<begin>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,70,123,70,124" dtype_id="9">
<arraysel loc="d,70,123,70,124" dtype_id="9">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_name1" dtype_id="15"/>
<and loc="d,70,123,70,124" dtype_id="12">
<const loc="d,70,123,70,124" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,70,123,70,124" dtype_id="12">
<varref loc="d,70,123,70,124" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,70,123,70,124" name="__Vtemp_1" dtype_id="9"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</assign>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,70,44,70,50" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,70,44,70,50" name="%%Error: t/t_enum_type_methods.v:70: got=&apos;%@&apos; exp=&apos;E01&apos;&#10;" dtype_id="9">
<varref loc="d,70,123,70,124" name="__Vtemp_1" dtype_id="9"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,70,142,70,147"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,71,13,71,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,71,26,71,29" dtype_id="7">
<const loc="d,71,31,71,34" name="4&apos;h3" dtype_id="10"/>
<arraysel loc="d,71,18,71,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,71,18,71,19" dtype_id="12">
<const loc="d,71,18,71,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,71,18,71,19" dtype_id="12">
<varref loc="d,71,18,71,19" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,71,43,71,49" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,71,43,71,49" name="%%Error: t/t_enum_type_methods.v:71: got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
<arraysel loc="d,71,122,71,123" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,71,122,71,123" dtype_id="12">
<const loc="d,71,122,71,123" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,71,122,71,123" dtype_id="12">
<varref loc="d,71,122,71,123" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,71,139,71,144"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,72,13,72,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,72,29,72,32" dtype_id="7">
<const loc="d,72,34,72,37" name="4&apos;h3" dtype_id="10"/>
<arraysel loc="d,72,18,72,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,72,18,72,19" dtype_id="12">
<const loc="d,72,18,72,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,72,18,72,19" dtype_id="12">
<varref loc="d,72,18,72,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,72,46,72,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,72,46,72,52" name="%%Error: t/t_enum_type_methods.v:72: got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
<arraysel loc="d,72,125,72,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,72,125,72,126" dtype_id="12">
<const loc="d,72,125,72,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,72,125,72,126" dtype_id="12">
<varref loc="d,72,125,72,126" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,72,145,72,150"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,73,13,73,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,73,29,73,32" dtype_id="7">
<const loc="d,73,34,73,37" name="4&apos;h4" dtype_id="10"/>
<arraysel loc="d,73,18,73,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,73,18,73,19" dtype_id="12">
<const loc="d,73,18,73,19" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,73,18,73,19" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,73,18,73,19" dtype_id="12">
<const loc="d,73,18,73,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,73,18,73,19" dtype_id="12">
<varref loc="d,73,18,73,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,73,46,73,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,73,46,73,52" name="%%Error: t/t_enum_type_methods.v:73: got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
<arraysel loc="d,73,125,73,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,73,125,73,126" dtype_id="12">
<const loc="d,73,125,73,126" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,73,125,73,126" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,73,125,73,126" dtype_id="12">
<const loc="d,73,125,73,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,73,125,73,126" dtype_id="12">
<varref loc="d,73,125,73,126" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,73,145,73,150"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,74,13,74,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,74,26,74,29" dtype_id="7">
<const loc="d,74,31,74,34" name="4&apos;h4" dtype_id="10"/>
<arraysel loc="d,74,18,74,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,74,18,74,19" dtype_id="12">
<const loc="d,74,18,74,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,74,18,74,19" dtype_id="12">
<varref loc="d,74,18,74,19" name="t.e" dtype_id="12"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</ccast>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,74,43,74,49" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,74,43,74,49" name="%%Error: t/t_enum_type_methods.v:74: got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
<arraysel loc="d,74,122,74,123" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,74,122,74,123" dtype_id="12">
<const loc="d,74,122,74,123" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,74,122,74,123" dtype_id="12">
<varref loc="d,74,122,74,123" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,74,139,74,144"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,75,13,75,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,75,29,75,32" dtype_id="7">
<const loc="d,75,34,75,37" name="4&apos;h4" dtype_id="10"/>
<arraysel loc="d,75,18,75,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,75,18,75,19" dtype_id="12">
<const loc="d,75,18,75,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,75,18,75,19" dtype_id="12">
<varref loc="d,75,18,75,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,75,46,75,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,75,46,75,52" name="%%Error: t/t_enum_type_methods.v:75: got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
<arraysel loc="d,75,125,75,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,75,125,75,126" dtype_id="12">
<const loc="d,75,125,75,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,75,125,75,126" dtype_id="12">
<varref loc="d,75,125,75,126" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,75,145,75,150"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,76,13,76,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,76,29,76,32" dtype_id="7">
<const loc="d,76,34,76,37" name="4&apos;h3" dtype_id="10"/>
<arraysel loc="d,76,18,76,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,76,18,76,19" dtype_id="12">
<const loc="d,76,18,76,19" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,76,18,76,19" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,76,18,76,19" dtype_id="12">
<const loc="d,76,18,76,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,76,18,76,19" dtype_id="12">
<varref loc="d,76,18,76,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,76,46,76,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,76,46,76,52" name="%%Error: t/t_enum_type_methods.v:76: got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
<arraysel loc="d,76,125,76,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,76,125,76,126" dtype_id="12">
<const loc="d,76,125,76,126" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,76,125,76,126" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,76,125,76,126" dtype_id="12">
<const loc="d,76,125,76,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,76,125,76,126" dtype_id="12">
<varref loc="d,76,125,76,126" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,76,145,76,150"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assigndly loc="d,77,12,77,14" dtype_id="10">
<const loc="d,77,15,77,18" name="4&apos;h3" dtype_id="10"/>
<varref loc="d,77,10,77,11" name="__Vdly__t.e" dtype_id="10"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assigndly>
</begin>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,79,12,79,14">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<eq loc="d,79,19,79,21" dtype_id="7">
<const loc="d,79,21,79,22" name="32&apos;sh2" dtype_id="8"/>
<varref loc="d,79,16,79,19" name="t.cyc" dtype_id="3"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</eq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,80,13,80,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neqn loc="d,80,26,80,28" dtype_id="7">
<const loc="d,80,30,80,35" name="&quot;E03&quot;" dtype_id="9"/>
<arraysel loc="d,80,18,80,19" dtype_id="9">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_name1" dtype_id="15"/>
<and loc="d,80,18,80,19" dtype_id="12">
<const loc="d,80,18,80,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,80,18,80,19" dtype_id="12">
<varref loc="d,80,18,80,19" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</neqn>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
<begin>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,80,123,80,124" dtype_id="9">
<arraysel loc="d,80,123,80,124" dtype_id="9">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_name1" dtype_id="15"/>
<and loc="d,80,123,80,124" dtype_id="12">
<const loc="d,80,123,80,124" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,80,123,80,124" dtype_id="12">
<varref loc="d,80,123,80,124" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,80,123,80,124" name="__Vtemp_2" dtype_id="9"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</assign>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,80,44,80,50" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,80,44,80,50" name="%%Error: t/t_enum_type_methods.v:80: got=&apos;%@&apos; exp=&apos;E03&apos;&#10;" dtype_id="9">
<varref loc="d,80,123,80,124" name="__Vtemp_2" dtype_id="9"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,80,142,80,147"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,81,13,81,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,81,26,81,29" dtype_id="7">
<const loc="d,81,31,81,34" name="4&apos;h4" dtype_id="10"/>
<arraysel loc="d,81,18,81,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,81,18,81,19" dtype_id="12">
<const loc="d,81,18,81,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,81,18,81,19" dtype_id="12">
<varref loc="d,81,18,81,19" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,81,43,81,49" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,81,43,81,49" name="%%Error: t/t_enum_type_methods.v:81: got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
<arraysel loc="d,81,122,81,123" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,81,122,81,123" dtype_id="12">
<const loc="d,81,122,81,123" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,81,122,81,123" dtype_id="12">
<varref loc="d,81,122,81,123" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,81,139,81,144"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,82,13,82,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,82,29,82,32" dtype_id="7">
<const loc="d,82,34,82,37" name="4&apos;h4" dtype_id="10"/>
<arraysel loc="d,82,18,82,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,82,18,82,19" dtype_id="12">
<const loc="d,82,18,82,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,82,18,82,19" dtype_id="12">
<varref loc="d,82,18,82,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,82,46,82,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,82,46,82,52" name="%%Error: t/t_enum_type_methods.v:82: got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
<arraysel loc="d,82,125,82,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,82,125,82,126" dtype_id="12">
<const loc="d,82,125,82,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,82,125,82,126" dtype_id="12">
<varref loc="d,82,125,82,126" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,82,145,82,150"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,83,13,83,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,83,29,83,32" dtype_id="7">
<const loc="d,83,34,83,37" name="4&apos;h1" dtype_id="10"/>
<arraysel loc="d,83,18,83,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,83,18,83,19" dtype_id="12">
<const loc="d,83,18,83,19" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,83,18,83,19" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,83,18,83,19" dtype_id="12">
<const loc="d,83,18,83,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,83,18,83,19" dtype_id="12">
<varref loc="d,83,18,83,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,83,46,83,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,83,46,83,52" name="%%Error: t/t_enum_type_methods.v:83: got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
<arraysel loc="d,83,125,83,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,83,125,83,126" dtype_id="12">
<const loc="d,83,125,83,126" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,83,125,83,126" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,83,125,83,126" dtype_id="12">
<const loc="d,83,125,83,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,83,125,83,126" dtype_id="12">
<varref loc="d,83,125,83,126" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,83,145,83,150"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,84,13,84,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,84,26,84,29" dtype_id="7">
<const loc="d,84,31,84,34" name="4&apos;h1" dtype_id="10"/>
<arraysel loc="d,84,18,84,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,84,18,84,19" dtype_id="12">
<const loc="d,84,18,84,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,84,18,84,19" dtype_id="12">
<varref loc="d,84,18,84,19" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,84,43,84,49" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,84,43,84,49" name="%%Error: t/t_enum_type_methods.v:84: got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
<arraysel loc="d,84,122,84,123" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,84,122,84,123" dtype_id="12">
<const loc="d,84,122,84,123" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,84,122,84,123" dtype_id="12">
<varref loc="d,84,122,84,123" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,84,139,84,144"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,85,13,85,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,85,29,85,32" dtype_id="7">
<const loc="d,85,34,85,37" name="4&apos;h1" dtype_id="10"/>
<arraysel loc="d,85,18,85,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,85,18,85,19" dtype_id="12">
<const loc="d,85,18,85,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,85,18,85,19" dtype_id="12">
<varref loc="d,85,18,85,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,85,46,85,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,85,46,85,52" name="%%Error: t/t_enum_type_methods.v:85: got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
<arraysel loc="d,85,125,85,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,85,125,85,126" dtype_id="12">
<const loc="d,85,125,85,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,85,125,85,126" dtype_id="12">
<varref loc="d,85,125,85,126" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,85,145,85,150"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,86,13,86,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,86,29,86,32" dtype_id="7">
<const loc="d,86,34,86,37" name="4&apos;h4" dtype_id="10"/>
<arraysel loc="d,86,18,86,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,86,18,86,19" dtype_id="12">
<const loc="d,86,18,86,19" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,86,18,86,19" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,86,18,86,19" dtype_id="12">
<const loc="d,86,18,86,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,86,18,86,19" dtype_id="12">
<varref loc="d,86,18,86,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,86,46,86,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,86,46,86,52" name="%%Error: t/t_enum_type_methods.v:86: got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
<arraysel loc="d,86,125,86,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,86,125,86,126" dtype_id="12">
<const loc="d,86,125,86,126" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,86,125,86,126" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,86,125,86,126" dtype_id="12">
<const loc="d,86,125,86,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,86,125,86,126" dtype_id="12">
<varref loc="d,86,125,86,126" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,86,145,86,150"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assigndly loc="d,87,12,87,14" dtype_id="10">
<const loc="d,87,15,87,18" name="4&apos;h4" dtype_id="10"/>
<varref loc="d,87,10,87,11" name="__Vdly__t.e" dtype_id="10"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assigndly>
</begin>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,89,12,89,14">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<eq loc="d,89,19,89,21" dtype_id="7">
<const loc="d,89,21,89,22" name="32&apos;sh3" dtype_id="8"/>
<varref loc="d,89,16,89,19" name="t.cyc" dtype_id="3"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</eq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,90,13,90,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neqn loc="d,90,26,90,28" dtype_id="7">
<const loc="d,90,30,90,35" name="&quot;E04&quot;" dtype_id="9"/>
<arraysel loc="d,90,18,90,19" dtype_id="9">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_name1" dtype_id="15"/>
<and loc="d,90,18,90,19" dtype_id="12">
<const loc="d,90,18,90,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,90,18,90,19" dtype_id="12">
<varref loc="d,90,18,90,19" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</neqn>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
<begin>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,90,123,90,124" dtype_id="9">
<arraysel loc="d,90,123,90,124" dtype_id="9">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_name1" dtype_id="15"/>
<and loc="d,90,123,90,124" dtype_id="12">
<const loc="d,90,123,90,124" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,90,123,90,124" dtype_id="12">
<varref loc="d,90,123,90,124" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,90,123,90,124" name="__Vtemp_3" dtype_id="9"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</assign>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,90,44,90,50" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,90,44,90,50" name="%%Error: t/t_enum_type_methods.v:90: got=&apos;%@&apos; exp=&apos;E04&apos;&#10;" dtype_id="9">
<varref loc="d,90,123,90,124" name="__Vtemp_3" dtype_id="9"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,90,142,90,147"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,91,13,91,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,91,26,91,29" dtype_id="7">
<const loc="d,91,31,91,34" name="4&apos;h1" dtype_id="10"/>
<arraysel loc="d,91,18,91,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,91,18,91,19" dtype_id="12">
<const loc="d,91,18,91,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,91,18,91,19" dtype_id="12">
<varref loc="d,91,18,91,19" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,91,43,91,49" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,91,43,91,49" name="%%Error: t/t_enum_type_methods.v:91: got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
<arraysel loc="d,91,122,91,123" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,91,122,91,123" dtype_id="12">
<const loc="d,91,122,91,123" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,91,122,91,123" dtype_id="12">
<varref loc="d,91,122,91,123" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,91,139,91,144"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,92,13,92,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,92,29,92,32" dtype_id="7">
<const loc="d,92,34,92,37" name="4&apos;h1" dtype_id="10"/>
<arraysel loc="d,92,18,92,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,92,18,92,19" dtype_id="12">
<const loc="d,92,18,92,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,92,18,92,19" dtype_id="12">
<varref loc="d,92,18,92,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,92,46,92,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,92,46,92,52" name="%%Error: t/t_enum_type_methods.v:92: got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
<arraysel loc="d,92,125,92,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,92,125,92,126" dtype_id="12">
<const loc="d,92,125,92,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,92,125,92,126" dtype_id="12">
<varref loc="d,92,125,92,126" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,92,145,92,150"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,93,13,93,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,93,29,93,32" dtype_id="7">
<const loc="d,93,34,93,37" name="4&apos;h3" dtype_id="10"/>
<arraysel loc="d,93,18,93,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,93,18,93,19" dtype_id="12">
<const loc="d,93,18,93,19" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,93,18,93,19" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,93,18,93,19" dtype_id="12">
<const loc="d,93,18,93,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,93,18,93,19" dtype_id="12">
<varref loc="d,93,18,93,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,93,46,93,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,93,46,93,52" name="%%Error: t/t_enum_type_methods.v:93: got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
<arraysel loc="d,93,125,93,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,93,125,93,126" dtype_id="12">
<const loc="d,93,125,93,126" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,93,125,93,126" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
<and loc="d,93,125,93,126" dtype_id="12">
<const loc="d,93,125,93,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,93,125,93,126" dtype_id="12">
<varref loc="d,93,125,93,126" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,93,145,93,150"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,94,13,94,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,94,26,94,29" dtype_id="7">
<const loc="d,94,31,94,34" name="4&apos;h3" dtype_id="10"/>
<arraysel loc="d,94,18,94,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,94,18,94,19" dtype_id="12">
<const loc="d,94,18,94,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,94,18,94,19" dtype_id="12">
<varref loc="d,94,18,94,19" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,94,43,94,49" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,94,43,94,49" name="%%Error: t/t_enum_type_methods.v:94: got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
<arraysel loc="d,94,122,94,123" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,94,122,94,123" dtype_id="12">
<const loc="d,94,122,94,123" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,94,122,94,123" dtype_id="12">
<varref loc="d,94,122,94,123" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,94,139,94,144"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,95,13,95,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,95,29,95,32" dtype_id="7">
<const loc="d,95,34,95,37" name="4&apos;h3" dtype_id="10"/>
<arraysel loc="d,95,18,95,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,95,18,95,19" dtype_id="12">
<const loc="d,95,18,95,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,95,18,95,19" dtype_id="12">
<varref loc="d,95,18,95,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,95,46,95,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,95,46,95,52" name="%%Error: t/t_enum_type_methods.v:95: got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
<arraysel loc="d,95,125,95,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,95,125,95,126" dtype_id="12">
<const loc="d,95,125,95,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,95,125,95,126" dtype_id="12">
<varref loc="d,95,125,95,126" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,95,145,95,150"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</begin>
</if>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,96,13,96,15">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<neq loc="d,96,29,96,32" dtype_id="7">
<const loc="d,96,34,96,37" name="4&apos;h1" dtype_id="10"/>
<arraysel loc="d,96,18,96,19" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,96,18,96,19" dtype_id="12">
<const loc="d,96,18,96,19" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,96,18,96,19" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,96,18,96,19" dtype_id="12">
<const loc="d,96,18,96,19" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,96,18,96,19" dtype_id="12">
<varref loc="d,96,18,96,19" name="t.e" dtype_id="12"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
</neq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,96,46,96,52" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,96,46,96,52" name="%%Error: t/t_enum_type_methods.v:96: got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
<arraysel loc="d,96,125,96,126" dtype_id="10">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,96,125,96,126" dtype_id="12">
<const loc="d,96,125,96,126" name="32&apos;h7" dtype_id="13"/>
<arraysel loc="d,96,125,96,126" dtype_id="12">
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
<and loc="d,96,125,96,126" dtype_id="12">
<const loc="d,96,125,96,126" name="32&apos;h7" dtype_id="13"/>
<ccast loc="d,96,125,96,126" dtype_id="12">
<varref loc="d,96,125,96,126" name="t.e" dtype_id="12"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</ccast>
</and>
</arraysel>
</and>
</arraysel>
</sformatf>
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<stop loc="d,96,145,96,150"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assigndly loc="d,97,12,97,14" dtype_id="10">
<const loc="d,97,15,97,18" name="4&apos;h1" dtype_id="10"/>
<varref loc="d,97,10,97,11" name="__Vdly__t.e" dtype_id="10"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assigndly>
</begin>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<if loc="d,99,12,99,14">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<eq loc="d,99,19,99,21" dtype_id="7">
<const loc="d,99,21,99,23" name="32&apos;sh63" dtype_id="8"/>
<varref loc="d,99,16,99,19" name="t.cyc" dtype_id="3"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</eq>
<begin>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<display loc="d,100,10,100,16" displaytype="$write">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<sformatf loc="d,100,10,100,16" name="*-* All Finished *-*&#10;" dtype_id="9"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</display>
Support enum.next with a parameter
2025-08-17 03:06:35 +02:00
<finish loc="d,101,10,101,17"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
</if>
</begin>
</if>
</begin>
</if>
</begin>
</if>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</begin>
</if>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,23,17,23,20" dtype_id="3">
<varref loc="d,23,17,23,20" name="__Vdly__t.cyc" dtype_id="3"/>
<varref loc="d,23,17,23,20" name="t.cyc" dtype_id="3"/>
Iternals: Remove AstAssignPre/AstAssignPost (#6307) Replace with AstAlwaysPre/AstAlwaysPost with AstAssign under them. Step towards #6280
2025-08-19 10:27:59 +02:00
</assign>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,24,9,24,10" dtype_id="10">
<varref loc="d,24,9,24,10" name="__Vdly__t.e" dtype_id="10"/>
<varref loc="d,24,9,24,10" name="t.e" dtype_id="10"/>
Iternals: Remove AstAssignPre/AstAssignPost (#6307) Replace with AstAlwaysPre/AstAlwaysPost with AstAssign under them. Step towards #6280
2025-08-19 10:27:59 +02:00
</assign>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</cfunc>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<cfunc loc="a,0,0,0,0" name="_eval_nba">
<if loc="d,11,8,11,9">
<and loc="d,11,8,11,9" dtype_id="17">
<const loc="d,11,8,11,9" name="64&apos;h1" dtype_id="17"/>
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="5"/>
<const loc="d,11,8,11,9" name="32&apos;h0" dtype_id="13"/>
</arraysel>
</and>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
<begin>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<stmtexpr loc="d,23,17,23,20">
<ccall loc="d,23,17,23,20" dtype_id="6" func="_nba_sequent__TOP__0"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</stmtexpr>
</begin>
</if>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</cfunc>
<cfunc loc="a,0,0,0,0" name="_trigger_orInto__act">
<var loc="a,0,0,0,0" name="out" dtype_id="5" dir="inout" vartype="unknown" origName="out"/>
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="out" dtype_id="5"/>
</creset>
<var loc="a,0,0,0,0" name="in" dtype_id="5" dir="const ref" vartype="unknown" origName="in"/>
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="in" dtype_id="5"/>
</creset>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<var loc="a,0,0,0,0" name="n" dtype_id="18" vartype="IData" origName="n"/>
<assign loc="a,0,0,0,0" dtype_id="18">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="a,0,0,0,0" name="32&apos;h0" dtype_id="13"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</assign>
<loop loc="d,11,8,11,9">
<begin>
<assign loc="d,11,8,11,9" dtype_id="16">
<or loc="d,11,8,11,9" dtype_id="16">
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="out" dtype_id="5"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</arraysel>
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="in" dtype_id="5"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</arraysel>
</or>
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="out" dtype_id="5"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</arraysel>
</assign>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<assign loc="a,0,0,0,0" dtype_id="18">
<add loc="a,0,0,0,0" dtype_id="18">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<ccast loc="a,0,0,0,0" dtype_id="13">
<const loc="a,0,0,0,0" name="32&apos;h1" dtype_id="13"/>
</ccast>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</add>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</assign>
<looptest loc="d,11,8,11,9">
<gt loc="d,11,8,11,9" dtype_id="7">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</gt>
</looptest>
</begin>
</loop>
</cfunc>
<cfunc loc="a,0,0,0,0" name="_eval_phase__act">
<stmtexpr loc="d,11,8,11,9">
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<ccall loc="d,11,8,11,9" dtype_id="6" func="_eval_triggers__act"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</stmtexpr>
<stmtexpr loc="d,11,8,11,9">
<ccall loc="d,11,8,11,9" dtype_id="6" func="_trigger_orInto__act">
<varref loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="5"/>
<varref loc="d,11,8,11,9" name="__VactTriggered" dtype_id="5"/>
</ccall>
</stmtexpr>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
<creturn loc="a,0,0,0,0">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="a,0,0,0,0" name="1&apos;h0" dtype_id="7"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</creturn>
</cfunc>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<cfunc loc="a,0,0,0,0" name="_trigger_clear__act">
<var loc="a,0,0,0,0" name="out" dtype_id="5" dir="output" vartype="unknown" origName="out"/>
<creset loc="a,0,0,0,0">
<varref loc="a,0,0,0,0" name="out" dtype_id="5"/>
</creset>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<var loc="a,0,0,0,0" name="n" dtype_id="18" vartype="IData" origName="n"/>
<assign loc="a,0,0,0,0" dtype_id="18">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="a,0,0,0,0" name="32&apos;h0" dtype_id="13"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</assign>
<loop loc="d,11,8,11,9">
<begin>
<assign loc="d,11,8,11,9" dtype_id="16">
<const loc="d,11,8,11,9" name="64&apos;h0" dtype_id="17"/>
<arraysel loc="d,11,8,11,9" dtype_id="16">
<varref loc="d,11,8,11,9" name="out" dtype_id="5"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</arraysel>
</assign>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<assign loc="a,0,0,0,0" dtype_id="18">
<add loc="a,0,0,0,0" dtype_id="18">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<ccast loc="a,0,0,0,0" dtype_id="13">
<const loc="a,0,0,0,0" name="32&apos;h1" dtype_id="13"/>
</ccast>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</add>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="a,0,0,0,0" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</assign>
<looptest loc="d,11,8,11,9">
<gt loc="d,11,8,11,9" dtype_id="7">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<varref loc="d,11,8,11,9" name="n" dtype_id="18"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
</gt>
</looptest>
</begin>
</loop>
</cfunc>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
<cfunc loc="a,0,0,0,0" name="_eval_phase__nba">
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<var loc="d,11,8,11,9" name="__VnbaExecute" dtype_id="19" vartype="bit" origName="__VnbaExecute"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="a,0,0,0,0" dtype_id="7">
<ccall loc="d,11,8,11,9" dtype_id="7" func="_trigger_anySet__act">
<varref loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="5"/>
</ccall>
<varref loc="a,0,0,0,0" name="__VnbaExecute" dtype_id="7"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</assign>
<if loc="a,0,0,0,0">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="a,0,0,0,0" name="__VnbaExecute" dtype_id="7"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
<begin>
<stmtexpr loc="a,0,0,0,0">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<ccall loc="a,0,0,0,0" dtype_id="6" func="_eval_nba"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</stmtexpr>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<stmtexpr loc="d,11,8,11,9">
<ccall loc="d,11,8,11,9" dtype_id="6" func="_trigger_clear__act">
<varref loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="5"/>
</ccall>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</stmtexpr>
</begin>
</if>
<creturn loc="a,0,0,0,0">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="a,0,0,0,0" name="__VnbaExecute" dtype_id="7"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</creturn>
</cfunc>
<cfunc loc="a,0,0,0,0" name="_eval">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<var loc="d,11,8,11,9" name="__VnbaIterCount" dtype_id="4" vartype="bit" origName="__VnbaIterCount"/>
<assign loc="d,11,8,11,9" dtype_id="4">
<const loc="d,11,8,11,9" name="32&apos;h0" dtype_id="13"/>
<varref loc="d,11,8,11,9" name="__VnbaIterCount" dtype_id="4"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</assign>
Improve Loop unrolling (#6480) (#6493) This patch implements #6480. All loop statements are represented using AstLoop and AstLoopTest. This necessitates rework of the loop unroller to handle loops of arbitrary form. To enable this, I have split the old unroller used for 'generate for' statements and moved it into V3Param, and subsequently rewrote V3Unroll to handle the new representation. V3Unroll can now unroll more complex loops, including with loop conditions containing multiple variable references or inlined functions. Handling the more generic code also requires some restrictions. If a loop contains any of the following, it cannot be unrolled: - A timing control that might suspend the loop - A non-inlined call to a non-pure function These constructs can change the values of variables in the loop, so are generally not safe to unroll if they are present. (We could still unroll if all the variables needed for unrolling are automatic, however we don't do that right now.) These restrictions seem ok in the benchmark suite, where the new unroller can generally unroll many more loops than before.
2025-09-29 16:25:25 +02:00
<loop loc="a,0,0,0,0">
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
<begin>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
<if loc="a,0,0,0,0">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<lt loc="a,0,0,0,0" dtype_id="7">
<const loc="a,0,0,0,0" name="32&apos;h64" dtype_id="13"/>
<varref loc="a,0,0,0,0" name="__VnbaIterCount" dtype_id="4"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</lt>
<begin>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<cstmt loc="d,11,8,11,9">
<text loc="d,11,8,11,9"/>
<stmtexpr loc="d,11,8,11,9">
<ccall loc="d,11,8,11,9" dtype_id="6" func="_dump_triggers__act">
<varref loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="5"/>
<const loc="d,11,8,11,9" name="&quot;nba&quot;" dtype_id="9"/>
</ccall>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</stmtexpr>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<text loc="d,11,8,11,9"/>
</cstmt>
<cstmt loc="a,0,0,0,0">
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
<text loc="a,0,0,0,0"/>
Internals: Refactor text based Ast constructs (#6280) (#6571) Remove the large variety of ways raw "text" is represented in the Ast. Particularly, the only thing that represents a string to be emitted in the output is AstText. There are 5 AstNodes that can contain AstText, and V3Emit will throw an error if an AstText is encountered anywhere else: - AstCStmt: Internally generated procedural statements involving raw text. - AstCStmtUser: This is the old AstUCStmt, renamed so it sorts next to AstCStmt, as it's largely equivalent. We should never create this internally unless used to represent user input. It is used for $c, statements in the input, and for some 'systemc_* blocks. - AstCExpr: Internally generaged expression involving raw text. - AstCExprUser: This is the old AstUCFunc, renamed so it sorts next to AstCExpr. It is largely equivalent, but also has more optimizations disabled. This should never be created internally, it is only used for $c expressions in the input. - AstTextBlock: Use by V3ProtectLib only, to generate the hierarchical wrappers. Text "tracking" for indentation is always on for AstCStmt, AstCExpr, and AstTextBlock, as these are always generated by us, and should always be well formed. Tracking is always off for AstCStmtUser and AstCExprUser, as these contain arbitrary user input that might not be safe to parse for indentation. Remove subsequently redundant AstNodeSimpleText and AstNodeText types. This patch also fixes incorrect indentation in emitted waveform tracing functions, and makes the output more readable for hier block SV stubs. With that, all raw text nodes are handled as a proper AstNodeStmt or AstNodeExpr as required for #6280.
2025-10-21 13:41:29 +02:00
</cstmt>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</begin>
</if>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,11,8,11,9" dtype_id="4">
<add loc="d,11,8,11,9" dtype_id="4">
<ccast loc="d,11,8,11,9" dtype_id="13">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</ccast>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,11,8,11,9" name="__VnbaIterCount" dtype_id="4"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</add>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,11,8,11,9" name="__VnbaIterCount" dtype_id="4"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</assign>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,11,8,11,9" dtype_id="4">
<const loc="d,11,8,11,9" name="32&apos;h0" dtype_id="13"/>
<varref loc="d,11,8,11,9" name="__VactIterCount" dtype_id="4"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</assign>
Improve Loop unrolling (#6480) (#6493) This patch implements #6480. All loop statements are represented using AstLoop and AstLoopTest. This necessitates rework of the loop unroller to handle loops of arbitrary form. To enable this, I have split the old unroller used for 'generate for' statements and moved it into V3Param, and subsequently rewrote V3Unroll to handle the new representation. V3Unroll can now unroll more complex loops, including with loop conditions containing multiple variable references or inlined functions. Handling the more generic code also requires some restrictions. If a loop contains any of the following, it cannot be unrolled: - A timing control that might suspend the loop - A non-inlined call to a non-pure function These constructs can change the values of variables in the loop, so are generally not safe to unroll if they are present. (We could still unroll if all the variables needed for unrolling are automatic, however we don't do that right now.) These restrictions seem ok in the benchmark suite, where the new unroller can generally unroll many more loops than before.
2025-09-29 16:25:25 +02:00
<loop loc="a,0,0,0,0">
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
<begin>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
<if loc="a,0,0,0,0">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<lt loc="a,0,0,0,0" dtype_id="7">
<const loc="a,0,0,0,0" name="32&apos;h64" dtype_id="13"/>
<varref loc="a,0,0,0,0" name="__VactIterCount" dtype_id="4"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</lt>
<begin>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<cstmt loc="d,11,8,11,9">
<text loc="d,11,8,11,9"/>
<stmtexpr loc="d,11,8,11,9">
<ccall loc="d,11,8,11,9" dtype_id="6" func="_dump_triggers__act">
<varref loc="d,11,8,11,9" name="__VactTriggered" dtype_id="5"/>
<const loc="d,11,8,11,9" name="&quot;act&quot;" dtype_id="9"/>
</ccall>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</stmtexpr>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<text loc="d,11,8,11,9"/>
</cstmt>
<cstmt loc="a,0,0,0,0">
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
<text loc="a,0,0,0,0"/>
Internals: Refactor text based Ast constructs (#6280) (#6571) Remove the large variety of ways raw "text" is represented in the Ast. Particularly, the only thing that represents a string to be emitted in the output is AstText. There are 5 AstNodes that can contain AstText, and V3Emit will throw an error if an AstText is encountered anywhere else: - AstCStmt: Internally generated procedural statements involving raw text. - AstCStmtUser: This is the old AstUCStmt, renamed so it sorts next to AstCStmt, as it's largely equivalent. We should never create this internally unless used to represent user input. It is used for $c, statements in the input, and for some 'systemc_* blocks. - AstCExpr: Internally generaged expression involving raw text. - AstCExprUser: This is the old AstUCFunc, renamed so it sorts next to AstCExpr. It is largely equivalent, but also has more optimizations disabled. This should never be created internally, it is only used for $c expressions in the input. - AstTextBlock: Use by V3ProtectLib only, to generate the hierarchical wrappers. Text "tracking" for indentation is always on for AstCStmt, AstCExpr, and AstTextBlock, as these are always generated by us, and should always be well formed. Tracking is always off for AstCStmtUser and AstCExprUser, as these contain arbitrary user input that might not be safe to parse for indentation. Remove subsequently redundant AstNodeSimpleText and AstNodeText types. This patch also fixes incorrect indentation in emitted waveform tracing functions, and makes the output more readable for hier block SV stubs. With that, all raw text nodes are handled as a proper AstNodeStmt or AstNodeExpr as required for #6280.
2025-10-21 13:41:29 +02:00
</cstmt>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</begin>
</if>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<assign loc="d,11,8,11,9" dtype_id="4">
<add loc="d,11,8,11,9" dtype_id="4">
<ccast loc="d,11,8,11,9" dtype_id="13">
<const loc="d,11,8,11,9" name="32&apos;h1" dtype_id="13"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</ccast>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,11,8,11,9" name="__VactIterCount" dtype_id="4"/>
Make eval loop construction more unified and the output more readable
2023-10-28 09:14:38 +02:00
</add>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,11,8,11,9" name="__VactIterCount" dtype_id="4"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</assign>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<looptest loc="a,0,0,0,0">
<ccall loc="a,0,0,0,0" dtype_id="7" func="_eval_phase__act"/>
</looptest>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</begin>
Improve Loop unrolling (#6480) (#6493) This patch implements #6480. All loop statements are represented using AstLoop and AstLoopTest. This necessitates rework of the loop unroller to handle loops of arbitrary form. To enable this, I have split the old unroller used for 'generate for' statements and moved it into V3Param, and subsequently rewrote V3Unroll to handle the new representation. V3Unroll can now unroll more complex loops, including with loop conditions containing multiple variable references or inlined functions. Handling the more generic code also requires some restrictions. If a loop contains any of the following, it cannot be unrolled: - A timing control that might suspend the loop - A non-inlined call to a non-pure function These constructs can change the values of variables in the loop, so are generally not safe to unroll if they are present. (We could still unroll if all the variables needed for unrolling are automatic, however we don't do that right now.) These restrictions seem ok in the benchmark suite, where the new unroller can generally unroll many more loops than before.
2025-09-29 16:25:25 +02:00
</loop>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<looptest loc="a,0,0,0,0">
<ccall loc="a,0,0,0,0" dtype_id="7" func="_eval_phase__nba"/>
</looptest>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</begin>
Improve Loop unrolling (#6480) (#6493) This patch implements #6480. All loop statements are represented using AstLoop and AstLoopTest. This necessitates rework of the loop unroller to handle loops of arbitrary form. To enable this, I have split the old unroller used for 'generate for' statements and moved it into V3Param, and subsequently rewrote V3Unroll to handle the new representation. V3Unroll can now unroll more complex loops, including with loop conditions containing multiple variable references or inlined functions. Handling the more generic code also requires some restrictions. If a loop contains any of the following, it cannot be unrolled: - A timing control that might suspend the loop - A non-inlined call to a non-pure function These constructs can change the values of variables in the loop, so are generally not safe to unroll if they are present. (We could still unroll if all the variables needed for unrolling are automatic, however we don't do that right now.) These restrictions seem ok in the benchmark suite, where the new unroller can generally unroll many more loops than before.
2025-09-29 16:25:25 +02:00
</loop>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</cfunc>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<cfunc loc="d,11,8,11,9" name="_eval_debug_assertions">
<if loc="d,15,10,15,13">
<and loc="d,15,10,15,13" dtype_id="1">
<varref loc="d,15,10,15,13" name="clk" dtype_id="1"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<const loc="d,15,10,15,13" name="8&apos;hfe" dtype_id="20"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</and>
<begin>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<cstmt loc="d,15,10,15,13">
<text loc="d,15,10,15,13"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</cstmt>
</begin>
</if>
</cfunc>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<cfunc loc="d,11,8,11,9" name="_ctor_var_reset">
<creset loc="d,15,10,15,13">
<varref loc="d,15,10,15,13" name="clk" dtype_id="1"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</creset>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<creset loc="d,23,17,23,20">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,23,17,23,20" name="t.cyc" dtype_id="3"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</creset>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<creset loc="d,24,9,24,10">
<varref loc="d,24,9,24,10" name="t.e" dtype_id="2"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</creset>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<creset loc="d,11,8,11,9">
<varref loc="d,11,8,11,9" name="__VactTriggered" dtype_id="5"/>
</creset>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<creset loc="d,11,8,11,9">
<varref loc="d,11,8,11,9" name="__Vtrigprevexpr___TOP__clk__0" dtype_id="1"/>
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
2022-05-15 17:03:32 +02:00
</creset>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<creset loc="d,11,8,11,9">
<varref loc="d,11,8,11,9" name="__VnbaTriggered" dtype_id="5"/>
</creset>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</cfunc>
Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
2022-01-17 22:22:07 +01:00
<cuse loc="a,0,0,0,0" name="$unit"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</module>
Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
2022-01-17 22:22:07 +01:00
<package loc="a,0,0,0,0" name="$unit" origName="__024unit">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<var loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11" vartype="" origName="__Venumtab_enum_next1">
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
<initarray>
<inititem index="1">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,19,30,19,31" name="4&apos;h3" dtype_id="10"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</inititem>
<inititem index="3">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,20,30,20,31" name="4&apos;h4" dtype_id="10"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</inititem>
<inititem index="4">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,18,30,18,31" name="4&apos;h1" dtype_id="10"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</inititem>
</initarray>
</var>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<var loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14" vartype="" origName="__Venumtab_enum_prev1">
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
<initarray>
<inititem index="1">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,20,30,20,31" name="4&apos;h4" dtype_id="10"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</inititem>
<inititem index="3">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,18,30,18,31" name="4&apos;h1" dtype_id="10"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</inititem>
<inititem index="4">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,19,30,19,31" name="4&apos;h3" dtype_id="10"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</inititem>
</initarray>
</var>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<var loc="d,17,12,17,16" name="__Venumtab_enum_name1" dtype_id="15" vartype="" origName="__Venumtab_enum_name1">
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
<initarray>
<inititem index="1">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,17,12,17,16" name="&quot;E01&quot;" dtype_id="9"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</inititem>
<inititem index="3">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,17,12,17,16" name="&quot;E03&quot;" dtype_id="9"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</inititem>
<inititem index="4">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,17,12,17,16" name="&quot;E04&quot;" dtype_id="9"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</inititem>
</initarray>
</var>
Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
2022-01-17 22:22:07 +01:00
<scope loc="a,0,0,0,0" name="$unit"/>
<cfunc loc="a,0,0,0,0" name="_ctor_var_reset">
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<creset loc="d,17,12,17,16">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,17,12,17,16" name="__Venumtab_enum_next1" dtype_id="11"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</creset>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<creset loc="d,17,12,17,16">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,17,12,17,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</creset>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<creset loc="d,17,12,17,16">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<varref loc="d,17,12,17,16" name="__Venumtab_enum_name1" dtype_id="15"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</creset>
</cfunc>
</package>
Fix splitting of Syms constructor/destructor bodies (#6662) Splitting of the Syms constructor/destructor were a bit arbitrarily enforced with some parts splitable, while others not. There was also an issue that even if the constructor and destructor bodies were split, we would still end up with both in the same file that was double the size of the intended split limit. To fix, first all statements required in the Syms constructor and destructor are gathered into a vector, then if the total number of statements required for both is bigger than the split limit, the implementations are split into sub-functions, one per file, as before, ensuring that none of the functions are bigger than the split limit. Also add __Slow suffix to the names of the files. Patch 2 of 3 to fix long compile times of the Syms module in some scenarios.
2025-11-08 11:36:12 +01:00
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck__Syms__Slow.cpp"/>
Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
2022-01-17 22:22:07 +01:00
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck__Syms.h"/>
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck.h"/>
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck.cpp"/>
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$root.h"/>
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$unit.h"/>
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$root__Slow.cpp"/>
Remove obsolete DepSet from output file names (#6564)
2025-10-17 02:34:09 +02:00
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$root__0__Slow.cpp"/>
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$root__0.cpp"/>
Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
2022-01-17 22:22:07 +01:00
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$unit__Slow.cpp"/>
Remove obsolete DepSet from output file names (#6564)
2025-10-17 02:34:09 +02:00
<cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$unit__0__Slow.cpp"/>
Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
2022-01-17 22:22:07 +01:00
<typetable loc="a,0,0,0,0">
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<basicdtype loc="d,33,24,33,27" id="1" name="logic"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<basicdtype loc="d,53,16,53,17" id="13" name="logic" left="31" right="0"/>
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<basicdtype loc="d,17,17,17,18" id="2" name="logic" left="3" right="0"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<enumdtype loc="d,17,12,17,16" id="21" name="t.my_t" sub_dtype_id="2">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<enumitem loc="d,18,24,18,27" name="E01" dtype_id="10">
<const loc="d,18,30,18,31" name="4&apos;h1" dtype_id="10"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</enumitem>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<enumitem loc="d,19,24,19,27" name="E03" dtype_id="10">
<const loc="d,19,30,19,31" name="4&apos;h3" dtype_id="10"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</enumitem>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<enumitem loc="d,20,24,20,27" name="E04" dtype_id="10">
<const loc="d,20,30,20,31" name="4&apos;h4" dtype_id="10"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</enumitem>
</enumdtype>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<basicdtype loc="d,23,4,23,11" id="3" name="integer" left="31" right="0" signed="true"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<refdtype loc="d,24,4,24,8" id="22" name="my_t" sub_dtype_id="2"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<basicdtype loc="d,28,4,28,10" id="9" name="string"/>
<unpackarraydtype loc="d,17,12,17,16" id="11" sub_dtype_id="2">
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<range loc="d,17,12,17,16">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,17,12,17,16" name="32&apos;h7" dtype_id="13"/>
<const loc="d,17,12,17,16" name="32&apos;h0" dtype_id="13"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</range>
</unpackarraydtype>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<unpackarraydtype loc="d,17,12,17,16" id="14" sub_dtype_id="2">
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<range loc="d,17,12,17,16">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,17,12,17,16" name="32&apos;h7" dtype_id="13"/>
<const loc="d,17,12,17,16" name="32&apos;h0" dtype_id="13"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</range>
</unpackarraydtype>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<unpackarraydtype loc="d,17,12,17,16" id="15" sub_dtype_id="9">
Tests: Define stop uniformly. No functional change.
2024-02-09 00:39:13 +01:00
<range loc="d,17,12,17,16">
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<const loc="d,17,12,17,16" name="32&apos;h7" dtype_id="13"/>
<const loc="d,17,12,17,16" name="32&apos;h0" dtype_id="13"/>
</range>
</unpackarraydtype>
<basicdtype loc="d,23,23,23,24" id="8" name="logic" left="31" right="0" signed="true"/>
<voiddtype loc="a,0,0,0,0" id="6"/>
<basicdtype loc="a,0,0,0,0" id="16" name="bit" left="63" right="0"/>
<unpackarraydtype loc="d,11,8,11,9" id="5" sub_dtype_id="16">
<range loc="d,11,8,11,9">
<const loc="d,11,8,11,9" name="32&apos;h0" dtype_id="13"/>
<const loc="d,11,8,11,9" name="32&apos;h0" dtype_id="13"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</range>
</unpackarraydtype>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<basicdtype loc="a,0,0,0,0" id="18" name="IData" left="31" right="0"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<basicdtype loc="d,63,14,63,21" id="17" name="logic" left="63" right="0"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<basicdtype loc="d,11,8,11,9" id="19" name="bit"/>
<basicdtype loc="d,11,8,11,9" id="4" name="bit" left="31" right="0"/>
Internals: Replace VlTriggerVec with unpacked array (#6616) Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same.
2025-10-31 19:29:11 +01:00
<basicdtype loc="d,63,22,63,25" id="7" name="logic" left="31" right="0"/>
<basicdtype loc="d,32,11,32,14" id="10" name="logic" left="31" right="0"/>
<basicdtype loc="d,38,15,38,16" id="12" name="logic" left="31" right="0"/>
Internals: Make all scheduling region use a single trigger vector. (#6620) The 'act' region used to have 2 trigger vectors ('act' and 'pre'), now it uses a single "extended" trigger vector where the top bits are what used to be the used bits in the 'pre' trigger vector. Please see the description above `TriggerKit`. Also move the extra triggers from the low end to the high end in the trigger vectors.
2025-11-01 16:43:20 +01:00
<basicdtype loc="d,15,10,15,13" id="20" name="logic" left="7" right="0"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</typetable>
<constpool>
Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
2022-01-17 22:22:07 +01:00
<module loc="a,0,0,0,0" name="@CONST-POOL@" origName="@CONST-POOL@">
<scope loc="a,0,0,0,0" name="TOP"/>
Add XML ccall, constpool, initarray, and if/while begins (#3080) * EmitXml: Added <ccall>, <constpool>, <initarray>/<inititem>, wrapped children of <if> and <while> with <begin> elements to prevent ambiguity * EmitXml: added signed="true" to signed basicdtypes
2021-07-25 03:06:06 +02:00
</module>
</constpool>
</netlist>
</verilator_xml>