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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain.
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t ;
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import "DPI-C" function string func (
input string arg
) /*verilator dpi_c_decl "char* func(const char*)"*/ ;
import "DPI-C" function string func_with_specifier (
input string arg
) /*verilator dpi_c_decl "char* func_with_specifier(const char*) throw()"*/ ;
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initial begin
`checks ( func ( " arg " ) , " abc " ) ;
`checks ( func_with_specifier ( " arg " ) , " efd " ) ;
$write ( " *-* All Finished *-* \n " ) ;
$finish ;
end
endmodule