27 lines
874 B
Systemverilog
27 lines
874 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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import "DPI-C" function string func(
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input string arg
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) /*verilator dpi_c_decl "char* func(const char*)"*/;
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import "DPI-C" function string func_with_specifier(
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input string arg
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) /*verilator dpi_c_decl "char* func_with_specifier(const char*) throw()"*/;
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initial begin
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`checks(func("arg"), "abc");
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`checks(func_with_specifier("arg"), "efd");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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