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Commentary: Changes update

This commit is contained in:
Wilson Snyder 2026-07-10 08:43:12 -04:00
parent 3bd04a70bd
commit 3191d98391
9 changed files with 76 additions and 34 deletions
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15
Changes
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@ -16,12 +16,27 @@ Verilator 5.051 devel
**Other:**
* Add comments as a branch description in coverage .info files (#7843). [Eryk Szpotanski]
* Add --enable-light-debug configure option (#7886). [Geza Lore, Testorrent USA, Inc.]
* Add user-provided DPI-C function declarations (#7626) (#7893). [Jakub Michalski]
* Support a sequence used as an event control (#7797) (#7846). [Yilou Wang]
* Optimize random initialization. [Geza Lore, Testorrent USA, Inc.]
* Optimize more always blocks in DFG (#7775). [Geza Lore, Testorrent USA, Inc.]
* Optimize assertion NFAs using bit-vector ring buffers (#7885). [Artur Bieniek, Antmicro Ltd.]
* Fix $display accepting streaming concat arguments (#7663) (#7890). [Jaeuk Lee]
* Fix DFG misoptimizing bound checks (#7755). [Jakub Michalski]
* Fix unique0 case side effects (#7787). [Pawel Klopotek]
* Fix cleaning purity cache after assertions. [Geza Lore, Testorrent USA, Inc.]
* Fix internal error for coverpoints that reference a covergroup formal parameter (#7853 partial) (#7889). [Matthew Ballance]
* Fix clang++ ambiguous overload of '==' operator (#7863). [Pawel Kojma, Antmicro Ltd.]
* Fix heap-use-after-free in `VlRNG::VlRNG()` (#7865). [Dragon-Git]
* Fix mixed-width inside and dist range bounds failing randomization (#7875). [Yilou Wang]
* Fix range delays with parameter bounds (#7882). [Artur Bieniek, Antmicro Ltd.]
* Fix --coverage on labeled inline assert/cover property (#7898) (#7904). [Patrick Creighton]
* Fix memory leak in VerilatedFst::close() (#7899). [Jakub Michalski]
* Fix independent force of multiply instantiated signals (#7905). [Artur Bieniek, Antmicro Ltd.]
* Fix release of forced port nets (#7907) (#7901). [Artur Bieniek, Antmicro Ltd.]
* Fix VL_TO_STRING function for array of structs (#7912). [Kornel Uriasz, Antmicro Ltd.]
* Fix queues falling into wrong template spec (#7914). [Adam Kostrzewski, Antmicro Ltd.]
Verilator 5.050 2026-07-01

9
test_regress/t/t_assert_inline_coverage.v
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@ -22,15 +22,18 @@ module t (
if (!rst_n) begin
q <= 1'b0;
cnt <= '0;
end else if (en) begin
end
else if (en) begin
q <= ~q;
cnt <= cnt + 8'd1;
end
end
a : assert property (@(posedge clk) !rst_n |=> q == 1'b0);
a :
assert property (@(posedge clk) !rst_n |=> q == 1'b0);
c : cover property (@(posedge clk) disable iff (!rst_n) en && cnt == $past(cnt));
c :
cover property (@(posedge clk) disable iff (!rst_n) en && cnt == $past(cnt));
always @(posedge clk) begin
cyc <= cyc + 1;

10
test_regress/t/t_dpi_decl.v
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@ -4,12 +4,18 @@
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
// verilog_format: off
`define stop $stop
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
// verilog_format: on
module t;
import "DPI-C" function string func(input string arg) /*verilator dpi_c_decl "char* func(const char*)"*/;
import "DPI-C" function string func_with_specifier(input string arg) /*verilator dpi_c_decl "char* func_with_specifier(const char*) throw()"*/;
import "DPI-C" function string func(
input string arg
) /*verilator dpi_c_decl "char* func(const char*)"*/;
import "DPI-C" function string func_with_specifier(
input string arg
) /*verilator dpi_c_decl "char* func_with_specifier(const char*) throw()"*/;
initial begin
`checks(func("arg"), "abc");

6
test_regress/t/t_dpi_decl_bad.out
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@ -1,5 +1,5 @@
%Error-BADVLTPRAGMA: t/t_dpi_decl_bad.v:8:57: No function declaration provided in /*verilator dpi_c_decl*/ meta-comment
8 | import "DPI-C" function string func(input string arg) /*verilator dpi_c_decl*/;
| ^~~~~~~~~~~~~~~~~~~~~~~~
%Error-BADVLTPRAGMA: t/t_dpi_decl_bad.v:8:58: No function declaration provided in /*verilator dpi_c_decl*/ meta-comment
8 | import "DPI-C" function string func(input string arg) /*verilator dpi_c_decl*/;
| ^~~~~~~~~~~~~~~~~~~~~~~~
... For error description see https://verilator.org/warn/BADVLTPRAGMA?v=latest
%Error: Exiting due to

2
test_regress/t/t_dpi_decl_bad.v
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@ -5,7 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
module t;
import "DPI-C" function string func(input string arg) /*verilator dpi_c_decl*/;
import "DPI-C" function string func(input string arg) /*verilator dpi_c_decl*/;
initial begin
$write("*-* All Finished *-*\n");

24
test_regress/t/t_force_immediate_release_port_net.v
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@ -16,12 +16,12 @@ module t;
wire [7:0] f;
wire [31:0] g;
logic [4:0] idx = 0;
sub s(b);
sub8 s_sel(d[7:0]);
sub8 s_const(8'h7c);
subout s_out(e[idx+:8]);
subout s_out_simple(f);
subout s_out_slice(g[15:8]);
sub s (b);
sub8 s_sel (d[7:0]);
sub8 s_const (8'h7c);
subout s_out (e[idx+:8]);
subout s_out_simple (f);
subout s_out_slice (g[15:8]);
initial begin
#1;
@ -76,12 +76,18 @@ module t;
endmodule
module sub(input logic [31:0] c);
module sub (
input logic [31:0] c
);
endmodule
module sub8(input logic [7:0] c);
module sub8 (
input logic [7:0] c
);
endmodule
module subout(output logic [7:0] c);
module subout (
output logic [7:0] c
);
assign c = 8'h5a;
endmodule

26
test_regress/t/t_force_scope.v
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@ -4,22 +4,24 @@
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
module child(input wire i);
/*verilator no_inline_module*/
module child (
input wire i
);
/*verilator no_inline_module*/
endmodule
module t;
child a(.i(1'b0));
child b(.i(1'b0));
child a (.i(1'b0));
child b (.i(1'b0));
initial begin
force a.i = 1'b1;
initial begin
force a.i = 1'b1;
if (a.i !== 1'b1) $stop;
if (b.i !== 1'b0) $stop;
if (a.i === b.i) $stop;
if (a.i !== 1'b1) $stop;
if (b.i !== 1'b0) $stop;
if (a.i === b.i) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

15
test_regress/t/t_force_scope_assign.v
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@ -4,7 +4,10 @@
// SPDX-FileCopyrightText: 2026 Antmicro
// SPDX-License-Identifier: CC0-1.0
module child(input wire drive, output wire observed);
module child (
input wire drive,
output wire observed
);
/*verilator no_inline_module*/
logic value;
@ -22,8 +25,14 @@ module t;
wire b_observed;
bit done;
child a(.drive(1'b1), .observed(a_observed));
child b(.drive(1'b0), .observed(b_observed));
child a (
.drive(1'b1),
.observed(a_observed)
);
child b (
.drive(1'b0),
.observed(b_observed)
);
always @(a_observed or b_observed) begin
if (!done && a_observed === 1'b1) begin

3
test_regress/t/t_property_delay_large.v
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@ -45,7 +45,8 @@ module t (
assert property (@(posedge clk) fixed_a |-> ##1024 fixed_b)
else fixed_fail_q.push_back($sampled(cyc) + 1);
cover property (@(posedge clk) range_a ##[5:300] range_b) range_pass_q.push_back($sampled(cyc) + 1);
cover property (@(posedge clk) range_a ##[5:300] range_b)
range_pass_q.push_back($sampled(cyc) + 1);
assert property (@(posedge clk) range_a |-> ##[5:300] range_b)
else range_fail_q.push_back($sampled(cyc) + 1);